[PATCH v4 0/3] Adding the Sparx5 Switch Reset Driver

[PATCH v4 0/3] Adding the Sparx5 Switch Reset Driver

[Steen Hegelund]

This series provides the Microchip Sparx5 Switch Reset Driver

The Sparx5 Switch SoC has a number of components that can be reset
individually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.

The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.

The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.

The Sparx5 Chip Register Model can be browsed at this location:
https://github.com/microchip-ung/sparx-5_reginfo

History:

v3 -> v4 Added commit message descriptions

v2 -> v3 Removed unused headers
         Renamed the reset controller dev member.
         Use regmap_read_poll_timeout instead of polling a function.
         Used two separate syscon entries in the binding
         Simplified the syscon error handling.
         Simplified the devm_reset_controller_register error handling.
         Moved the contents of the mchp_sparx5_reset_config function into
         the probe function.

v1 -> v2 Removed debug prints
         Changed the error handling to save the error code before jumping.

Steen Hegelund (3):
  dt-bindings: reset: microchip sparx5 reset driver bindings
  reset: mchp: sparx5: add switch reset driver
  arm64: dts: reset: add microchip sparx5 switch reset driver

 .../bindings/reset/microchip,rst.yaml         |  59 +++++++++
 arch/arm64/boot/dts/microchip/sparx5.dtsi     |  14 +-
 drivers/reset/Kconfig                         |   8 ++
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-microchip-sparx5.c        | 120 ++++++++++++++++++
 5 files changed, 199 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
 create mode 100644 drivers/reset/reset-microchip-sparx5.c

-- 
2.29.2

[PATCH v4 0/3] Adding the Sparx5 Switch Reset Driver

[Steen Hegelund]

This series provides the Microchip Sparx5 Switch Reset Driver

The Sparx5 Switch SoC has a number of components that can be reset
individually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.

The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.

The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.

The Sparx5 Chip Register Model can be browsed at this location:
https://github.com/microchip-ung/sparx-5_reginfo

History:

v3 -> v4 Added commit message descriptions

v2 -> v3 Removed unused headers
         Renamed the reset controller dev member.
         Use regmap_read_poll_timeout instead of polling a function.
         Used two separate syscon entries in the binding
         Simplified the syscon error handling.
         Simplified the devm_reset_controller_register error handling.
         Moved the contents of the mchp_sparx5_reset_config function into
         the probe function.

v1 -> v2 Removed debug prints
         Changed the error handling to save the error code before jumping.

Steen Hegelund (3):
  dt-bindings: reset: microchip sparx5 reset driver bindings
  reset: mchp: sparx5: add switch reset driver
  arm64: dts: reset: add microchip sparx5 switch reset driver

 .../bindings/reset/microchip,rst.yaml         |  59 +++++++++
 arch/arm64/boot/dts/microchip/sparx5.dtsi     |  14 +-
 drivers/reset/Kconfig                         |   8 ++
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-microchip-sparx5.c        | 120 ++++++++++++++++++
 5 files changed, 199 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
 create mode 100644 drivers/reset/reset-microchip-sparx5.c

-- 
2.29.2


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[PATCH v4 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings

[Steen Hegelund]

Document the Sparx5 reset device driver bindings

The driver uses two syscons on sparx5 for access to
the reset control and the reset status.

Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
---
 .../bindings/reset/microchip,rst.yaml         | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml

diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index 000000000000..af01016e246f
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+  - Steen Hegelund <steen.hegelund@microchip.com>
+  - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+  The Microchip Sparx5 Switch provides reset control and implements the following
+  functions
+    - One Time Switch Core Reset (Soft Reset)
+
+properties:
+  $nodename:
+    pattern: "^reset-controller@[0-9a-f]+$"
+
+  compatible:
+    const: microchip,sparx5-switch-reset
+
+  reg:
+    maxItems: 1
+
+  "#reset-cells":
+    const: 1
+
+  cpu-syscon:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+    description: syscon used to access CPU reset
+    maxItems: 1
+
+  gcb-syscon:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+    description: syscon used to access Global Control Block
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#reset-cells"
+  - cpu-syscon
+  - gcb-syscon
+
+additionalProperties: false
+
+examples:
+  - |
+    reset: reset-controller@0 {
+        compatible = "microchip,sparx5-switch-reset";
+        reg = <0x0 0x0>;
+        #reset-cells = <1>;
+        cpu-syscon = <&cpu_ctrl>;
+        gcb-syscon = <&gcb_ctrl>;
+    };
+
-- 
2.29.2

[PATCH v4 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings

[Steen Hegelund]

Document the Sparx5 reset device driver bindings

The driver uses two syscons on sparx5 for access to
the reset control and the reset status.

Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
---
 .../bindings/reset/microchip,rst.yaml         | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml

diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index 000000000000..af01016e246f
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+  - Steen Hegelund <steen.hegelund@microchip.com>
+  - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+  The Microchip Sparx5 Switch provides reset control and implements the following
+  functions
+    - One Time Switch Core Reset (Soft Reset)
+
+properties:
+  $nodename:
+    pattern: "^reset-controller@[0-9a-f]+$"
+
+  compatible:
+    const: microchip,sparx5-switch-reset
+
+  reg:
+    maxItems: 1
+
+  "#reset-cells":
+    const: 1
+
+  cpu-syscon:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+    description: syscon used to access CPU reset
+    maxItems: 1
+
+  gcb-syscon:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+    description: syscon used to access Global Control Block
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#reset-cells"
+  - cpu-syscon
+  - gcb-syscon
+
+additionalProperties: false
+
+examples:
+  - |
+    reset: reset-controller@0 {
+        compatible = "microchip,sparx5-switch-reset";
+        reg = <0x0 0x0>;
+        #reset-cells = <1>;
+        cpu-syscon = <&cpu_ctrl>;
+        gcb-syscon = <&gcb_ctrl>;
+    };
+
-- 
2.29.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 2/3] reset: mchp: sparx5: add switch reset driver

[Steen Hegelund]

The Sparx5 Switch SoC has a number of components that can be reset
indiviually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.

The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.

The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.

Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
---
 drivers/reset/Kconfig                  |   8 ++
 drivers/reset/Makefile                 |   1 +
 drivers/reset/reset-microchip-sparx5.c | 120 +++++++++++++++++++++++++
 3 files changed, 129 insertions(+)
 create mode 100644 drivers/reset/reset-microchip-sparx5.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..05c240c47a8a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -101,6 +101,14 @@ config RESET_LPC18XX
 	help
 	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
 
+config RESET_MCHP_SPARX5
+	bool "Microchip Sparx5 reset driver"
+	depends on HAS_IOMEM || COMPILE_TEST
+	default y if SPARX5_SWITCH
+	select MFD_SYSCON
+	help
+	  This driver supports switch core reset for the Microchip Sparx5 SoC.
+
 config RESET_MESON
 	tristate "Meson Reset Driver"
 	depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..341fd9ab4bf6 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
 obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
 obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index 000000000000..0dbd2b6161ef
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#define PROTECT_REG    0x84
+#define PROTECT_BIT    BIT(10)
+#define SOFT_RESET_REG 0x08
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+	struct regmap *cpu_ctrl;
+	struct regmap *gcb_ctrl;
+	struct reset_controller_dev rcdev;
+};
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	struct mchp_reset_context *ctx =
+		container_of(rcdev, struct mchp_reset_context, rcdev);
+	u32 val;
+
+	/* Make sure the core is PROTECTED from reset */
+	regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT);
+
+	/* Start soft reset */
+	regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+	/* Wait for soft reset done */
+	return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
+					(val & SOFT_RESET_BIT) == 0,
+					1, 100);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+	.reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_reset_probe(struct platform_device *pdev)
+{
+	struct device_node *dn = pdev->dev.of_node;
+	struct regmap *cpu_ctrl, *gcb_ctrl;
+	struct device *dev = &pdev->dev;
+	struct mchp_reset_context *ctx;
+	struct device_node *syscon_np;
+	int err;
+
+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	syscon_np = of_parse_phandle(dn, "cpu-syscon", 0);
+	if (!syscon_np)
+		return -ENODEV;
+	cpu_ctrl = syscon_node_to_regmap(syscon_np);
+	of_node_put(syscon_np);
+	if (IS_ERR(cpu_ctrl)) {
+		err = PTR_ERR(cpu_ctrl);
+		dev_err(dev, "No cpu-syscon map: %d\n", err);
+		return err;
+	}
+
+	syscon_np = of_parse_phandle(dn, "gcb-syscon", 0);
+	if (!syscon_np)
+		return -ENODEV;
+	gcb_ctrl = syscon_node_to_regmap(syscon_np);
+	of_node_put(syscon_np);
+	if (IS_ERR(gcb_ctrl)) {
+		err = PTR_ERR(gcb_ctrl);
+		dev_err(dev, "No gcb-syscon map: %d\n", err);
+		return err;
+	}
+
+	ctx->cpu_ctrl = cpu_ctrl;
+	ctx->gcb_ctrl = gcb_ctrl;
+
+	ctx->rcdev.owner = THIS_MODULE;
+	ctx->rcdev.nr_resets = 1;
+	ctx->rcdev.ops = &sparx5_reset_ops;
+	ctx->rcdev.of_node = dn;
+
+	return devm_reset_controller_register(dev, &ctx->rcdev);
+}
+
+static const struct of_device_id mchp_sparx5_reset_of_match[] = {
+	{
+		.compatible = "microchip,sparx5-switch-reset",
+	},
+	{ /*sentinel*/ }
+};
+
+static struct platform_driver mchp_sparx5_reset_driver = {
+	.probe = mchp_sparx5_reset_probe,
+	.driver = {
+		.name = "sparx5-switch-reset",
+		.of_match_table = mchp_sparx5_reset_of_match,
+	},
+};
+
+static int __init mchp_sparx5_reset_init(void)
+{
+	return platform_driver_register(&mchp_sparx5_reset_driver);
+}
+
+postcore_initcall(mchp_sparx5_reset_init);
+
+MODULE_DESCRIPTION("Microchip Sparx5 switch reset driver");
+MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
+MODULE_LICENSE("Dual MIT/GPL");
-- 
2.29.2

[PATCH v4 2/3] reset: mchp: sparx5: add switch reset driver

[Steen Hegelund]

The Sparx5 Switch SoC has a number of components that can be reset
indiviually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.

The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.

The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.

Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
---
 drivers/reset/Kconfig                  |   8 ++
 drivers/reset/Makefile                 |   1 +
 drivers/reset/reset-microchip-sparx5.c | 120 +++++++++++++++++++++++++
 3 files changed, 129 insertions(+)
 create mode 100644 drivers/reset/reset-microchip-sparx5.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..05c240c47a8a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -101,6 +101,14 @@ config RESET_LPC18XX
 	help
 	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
 
+config RESET_MCHP_SPARX5
+	bool "Microchip Sparx5 reset driver"
+	depends on HAS_IOMEM || COMPILE_TEST
+	default y if SPARX5_SWITCH
+	select MFD_SYSCON
+	help
+	  This driver supports switch core reset for the Microchip Sparx5 SoC.
+
 config RESET_MESON
 	tristate "Meson Reset Driver"
 	depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..341fd9ab4bf6 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
 obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
 obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index 000000000000..0dbd2b6161ef
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#define PROTECT_REG    0x84
+#define PROTECT_BIT    BIT(10)
+#define SOFT_RESET_REG 0x08
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+	struct regmap *cpu_ctrl;
+	struct regmap *gcb_ctrl;
+	struct reset_controller_dev rcdev;
+};
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	struct mchp_reset_context *ctx =
+		container_of(rcdev, struct mchp_reset_context, rcdev);
+	u32 val;
+
+	/* Make sure the core is PROTECTED from reset */
+	regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT);
+
+	/* Start soft reset */
+	regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+	/* Wait for soft reset done */
+	return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
+					(val & SOFT_RESET_BIT) == 0,
+					1, 100);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+	.reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_reset_probe(struct platform_device *pdev)
+{
+	struct device_node *dn = pdev->dev.of_node;
+	struct regmap *cpu_ctrl, *gcb_ctrl;
+	struct device *dev = &pdev->dev;
+	struct mchp_reset_context *ctx;
+	struct device_node *syscon_np;
+	int err;
+
+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	syscon_np = of_parse_phandle(dn, "cpu-syscon", 0);
+	if (!syscon_np)
+		return -ENODEV;
+	cpu_ctrl = syscon_node_to_regmap(syscon_np);
+	of_node_put(syscon_np);
+	if (IS_ERR(cpu_ctrl)) {
+		err = PTR_ERR(cpu_ctrl);
+		dev_err(dev, "No cpu-syscon map: %d\n", err);
+		return err;
+	}
+
+	syscon_np = of_parse_phandle(dn, "gcb-syscon", 0);
+	if (!syscon_np)
+		return -ENODEV;
+	gcb_ctrl = syscon_node_to_regmap(syscon_np);
+	of_node_put(syscon_np);
+	if (IS_ERR(gcb_ctrl)) {
+		err = PTR_ERR(gcb_ctrl);
+		dev_err(dev, "No gcb-syscon map: %d\n", err);
+		return err;
+	}
+
+	ctx->cpu_ctrl = cpu_ctrl;
+	ctx->gcb_ctrl = gcb_ctrl;
+
+	ctx->rcdev.owner = THIS_MODULE;
+	ctx->rcdev.nr_resets = 1;
+	ctx->rcdev.ops = &sparx5_reset_ops;
+	ctx->rcdev.of_node = dn;
+
+	return devm_reset_controller_register(dev, &ctx->rcdev);
+}
+
+static const struct of_device_id mchp_sparx5_reset_of_match[] = {
+	{
+		.compatible = "microchip,sparx5-switch-reset",
+	},
+	{ /*sentinel*/ }
+};
+
+static struct platform_driver mchp_sparx5_reset_driver = {
+	.probe = mchp_sparx5_reset_probe,
+	.driver = {
+		.name = "sparx5-switch-reset",
+		.of_match_table = mchp_sparx5_reset_of_match,
+	},
+};
+
+static int __init mchp_sparx5_reset_init(void)
+{
+	return platform_driver_register(&mchp_sparx5_reset_driver);
+}
+
+postcore_initcall(mchp_sparx5_reset_init);
+
+MODULE_DESCRIPTION("Microchip Sparx5 switch reset driver");
+MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
+MODULE_LICENSE("Dual MIT/GPL");
-- 
2.29.2


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[PATCH v4 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver

[Steen Hegelund]

This provides reset driver support for the Microchip Sparx5 PCB134 and
PCB135 reference boards.

Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
---
 arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..4edbb9fcdce0 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,17 @@ mux: mux-controller {
 			};
 		};
 
-		reset@611010008 {
-			compatible = "microchip,sparx5-chip-reset";
-			reg = <0x6 0x11010008 0x4>;
+		gcb_ctrl: syscon@611010000 {
+			compatible = "microchip,sparx5-gcb-syscon", "syscon";
+			reg = <0x6 0x11010000 0x10000>;
+		};
+
+		reset: reset-controller@0 {
+			compatible = "microchip,sparx5-switch-reset";
+			reg = <0x6 0x0 0x0>;
+			#reset-cells = <1>;
+			cpu-syscon = <&cpu_ctrl>;
+			gcb-syscon = <&gcb_ctrl>;
 		};
 
 		uart0: serial@600100000 {
-- 
2.29.2

[PATCH v4 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver

[Steen Hegelund]

This provides reset driver support for the Microchip Sparx5 PCB134 and
PCB135 reference boards.

Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
---
 arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..4edbb9fcdce0 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,17 @@ mux: mux-controller {
 			};
 		};
 
-		reset@611010008 {
-			compatible = "microchip,sparx5-chip-reset";
-			reg = <0x6 0x11010008 0x4>;
+		gcb_ctrl: syscon@611010000 {
+			compatible = "microchip,sparx5-gcb-syscon", "syscon";
+			reg = <0x6 0x11010000 0x10000>;
+		};
+
+		reset: reset-controller@0 {
+			compatible = "microchip,sparx5-switch-reset";
+			reg = <0x6 0x0 0x0>;
+			#reset-cells = <1>;
+			cpu-syscon = <&cpu_ctrl>;
+			gcb-syscon = <&gcb_ctrl>;
 		};
 
 		uart0: serial@600100000 {
-- 
2.29.2


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Re: [PATCH v4 0/3] Adding the Sparx5 Switch Reset Driver

[Steen Hegelund]

Hi Philipp,

I just wanted to know if there are any outstanding items that you
would like me to handle, or you think that the driver is acceptable as
it is now?

BR
Steen

On Wed, 2021-01-20 at 09:19 +0100, Steen Hegelund wrote:
> This series provides the Microchip Sparx5 Switch Reset Driver
> 
> The Sparx5 Switch SoC has a number of components that can be reset
> individually, but at least the Switch Core needs to be in a well
> defined
> state at power on, when any of the Sparx5 drivers starts to access
> the
> Switch Core, this reset driver is available.
> 
> The reset driver is loaded early via the postcore_initcall interface,
> and
> will then be available for the other Sparx5 drivers (SGPIO, SwitchDev
> etc)
> that are loaded next, and the first of them to be loaded can perform
> the
> one-time Switch Core reset that is needed.
> 
> The driver has protection so that the system busses, DDR controller,
> PCI-E
> and ARM A53 CPU and a few other subsystems are not touched by the
> reset.
> 
> The Sparx5 Chip Register Model can be browsed at this location:
> https://github.com/microchip-ung/sparx-5_reginfo
> 
> History:
> 
> v3 -> v4 Added commit message descriptions
> 
> v2 -> v3 Removed unused headers
>          Renamed the reset controller dev member.
>          Use regmap_read_poll_timeout instead of polling a function.
>          Used two separate syscon entries in the binding
>          Simplified the syscon error handling.
>          Simplified the devm_reset_controller_register error
> handling.
>          Moved the contents of the mchp_sparx5_reset_config function
> into
>          the probe function.
> 
> v1 -> v2 Removed debug prints
>          Changed the error handling to save the error code before
> jumping.
> 
> Steen Hegelund (3):
>   dt-bindings: reset: microchip sparx5 reset driver bindings
>   reset: mchp: sparx5: add switch reset driver
>   arm64: dts: reset: add microchip sparx5 switch reset driver
> 
>  .../bindings/reset/microchip,rst.yaml         |  59 +++++++++
>  arch/arm64/boot/dts/microchip/sparx5.dtsi     |  14 +-
>  drivers/reset/Kconfig                         |   8 ++
>  drivers/reset/Makefile                        |   1 +
>  drivers/reset/reset-microchip-sparx5.c        | 120
> ++++++++++++++++++
>  5 files changed, 199 insertions(+), 3 deletions(-)
>  create mode 100644
> Documentation/devicetree/bindings/reset/microchip,rst.yaml
>  create mode 100644 drivers/reset/reset-microchip-sparx5.c
> 

Re: [PATCH v4 0/3] Adding the Sparx5 Switch Reset Driver

[Steen Hegelund]

Hi Philipp,

I just wanted to know if there are any outstanding items that you
would like me to handle, or you think that the driver is acceptable as
it is now?

BR
Steen

On Wed, 2021-01-20 at 09:19 +0100, Steen Hegelund wrote:
> This series provides the Microchip Sparx5 Switch Reset Driver
> 
> The Sparx5 Switch SoC has a number of components that can be reset
> individually, but at least the Switch Core needs to be in a well
> defined
> state at power on, when any of the Sparx5 drivers starts to access
> the
> Switch Core, this reset driver is available.
> 
> The reset driver is loaded early via the postcore_initcall interface,
> and
> will then be available for the other Sparx5 drivers (SGPIO, SwitchDev
> etc)
> that are loaded next, and the first of them to be loaded can perform
> the
> one-time Switch Core reset that is needed.
> 
> The driver has protection so that the system busses, DDR controller,
> PCI-E
> and ARM A53 CPU and a few other subsystems are not touched by the
> reset.
> 
> The Sparx5 Chip Register Model can be browsed at this location:
> https://github.com/microchip-ung/sparx-5_reginfo
> 
> History:
> 
> v3 -> v4 Added commit message descriptions
> 
> v2 -> v3 Removed unused headers
>          Renamed the reset controller dev member.
>          Use regmap_read_poll_timeout instead of polling a function.
>          Used two separate syscon entries in the binding
>          Simplified the syscon error handling.
>          Simplified the devm_reset_controller_register error
> handling.
>          Moved the contents of the mchp_sparx5_reset_config function
> into
>          the probe function.
> 
> v1 -> v2 Removed debug prints
>          Changed the error handling to save the error code before
> jumping.
> 
> Steen Hegelund (3):
>   dt-bindings: reset: microchip sparx5 reset driver bindings
>   reset: mchp: sparx5: add switch reset driver
>   arm64: dts: reset: add microchip sparx5 switch reset driver
> 
>  .../bindings/reset/microchip,rst.yaml         |  59 +++++++++
>  arch/arm64/boot/dts/microchip/sparx5.dtsi     |  14 +-
>  drivers/reset/Kconfig                         |   8 ++
>  drivers/reset/Makefile                        |   1 +
>  drivers/reset/reset-microchip-sparx5.c        | 120
> ++++++++++++++++++
>  5 files changed, 199 insertions(+), 3 deletions(-)
>  create mode 100644
> Documentation/devicetree/bindings/reset/microchip,rst.yaml
>  create mode 100644 drivers/reset/reset-microchip-sparx5.c
> 



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Re: [PATCH v4 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver

[Rob Herring]

On Wed, Jan 20, 2021 at 09:19:21AM +0100, Steen Hegelund wrote:
> This provides reset driver support for the Microchip Sparx5 PCB134 and
> PCB135 reference boards.

This isn't a compatible change. You need an explanation why that's okay 
if that's intended.

> 
> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
> ---
>  arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> index 380281f312d8..4edbb9fcdce0 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> @@ -132,9 +132,17 @@ mux: mux-controller {
>  			};
>  		};
>  
> -		reset@611010008 {
> -			compatible = "microchip,sparx5-chip-reset";
> -			reg = <0x6 0x11010008 0x4>;
> +		gcb_ctrl: syscon@611010000 {
> +			compatible = "microchip,sparx5-gcb-syscon", "syscon";
> +			reg = <0x6 0x11010000 0x10000>;
> +		};
> +
> +		reset: reset-controller@0 {
> +			compatible = "microchip,sparx5-switch-reset";
> +			reg = <0x6 0x0 0x0>;

Your register length is 0?

> +			#reset-cells = <1>;
> +			cpu-syscon = <&cpu_ctrl>;

Can't you accomplish the same thing adding these to 
"microchip,sparx5-chip-reset"? Or possibly as a child node.

Define nodes based on h/w blocks, not as containers of things you happen 
to want for some driver.

> +			gcb-syscon = <&gcb_ctrl>;
>  		};
>  
>  		uart0: serial@600100000 {
> -- 
> 2.29.2
> 

Re: [PATCH v4 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver

[Rob Herring]

On Wed, Jan 20, 2021 at 09:19:21AM +0100, Steen Hegelund wrote:
> This provides reset driver support for the Microchip Sparx5 PCB134 and
> PCB135 reference boards.

This isn't a compatible change. You need an explanation why that's okay 
if that's intended.

> 
> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
> ---
>  arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> index 380281f312d8..4edbb9fcdce0 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> @@ -132,9 +132,17 @@ mux: mux-controller {
>  			};
>  		};
>  
> -		reset@611010008 {
> -			compatible = "microchip,sparx5-chip-reset";
> -			reg = <0x6 0x11010008 0x4>;
> +		gcb_ctrl: syscon@611010000 {
> +			compatible = "microchip,sparx5-gcb-syscon", "syscon";
> +			reg = <0x6 0x11010000 0x10000>;
> +		};
> +
> +		reset: reset-controller@0 {
> +			compatible = "microchip,sparx5-switch-reset";
> +			reg = <0x6 0x0 0x0>;

Your register length is 0?

> +			#reset-cells = <1>;
> +			cpu-syscon = <&cpu_ctrl>;

Can't you accomplish the same thing adding these to 
"microchip,sparx5-chip-reset"? Or possibly as a child node.

Define nodes based on h/w blocks, not as containers of things you happen 
to want for some driver.

> +			gcb-syscon = <&gcb_ctrl>;
>  		};
>  
>  		uart0: serial@600100000 {
> -- 
> 2.29.2
> 

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Re: [PATCH v4 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver

[Steen Hegelund]

Hi Rob,

On Fri, 2021-02-05 at 16:35 -0600, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Wed, Jan 20, 2021 at 09:19:21AM +0100, Steen Hegelund wrote:
> > This provides reset driver support for the Microchip Sparx5 PCB134
> > and
> > PCB135 reference boards.
> 
> This isn't a compatible change. You need an explanation why that's
> okay
> if that's intended.
> 
> > 
> > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
> > ---
> >  arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +++++++++++---
> >  1 file changed, 11 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > index 380281f312d8..4edbb9fcdce0 100644
> > --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > @@ -132,9 +132,17 @@ mux: mux-controller {
> >                       };
> >               };
> > 
> > -             reset@611010008 {
> > -                     compatible = "microchip,sparx5-chip-reset";
> > -                     reg = <0x6 0x11010008 0x4>;
> > +             gcb_ctrl: syscon@611010000 {
> > +                     compatible = "microchip,sparx5-gcb-syscon",
> > "syscon";
> > +                     reg = <0x6 0x11010000 0x10000>;
> > +             };
> > +
> > +             reset: reset-controller@0 {
> > +                     compatible = "microchip,sparx5-switch-reset";
> > +                     reg = <0x6 0x0 0x0>;
> 
> Your register length is 0?

Yes, I only use the syscons.

> 
> > +                     #reset-cells = <1>;
> > +                     cpu-syscon = <&cpu_ctrl>;
> 
> Can't you accomplish the same thing adding these to
> "microchip,sparx5-chip-reset"? Or possibly as a child node.
> 
> Define nodes based on h/w blocks, not as containers of things you
> happen
> to want for some driver.

Yes - I think the idea of using syscons came from another reset driver,
but it probably makes more sense to just use IO ranges directly.
I will try that out.

> 
> > +                     gcb-syscon = <&gcb_ctrl>;
> >               };
> > 
> >               uart0: serial@600100000 {
> > --
> > 2.29.2
> > 

Thanks for your comments

BR
Steen

Re: [PATCH v4 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver

[Steen Hegelund]

Hi Rob,

On Fri, 2021-02-05 at 16:35 -0600, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Wed, Jan 20, 2021 at 09:19:21AM +0100, Steen Hegelund wrote:
> > This provides reset driver support for the Microchip Sparx5 PCB134
> > and
> > PCB135 reference boards.
> 
> This isn't a compatible change. You need an explanation why that's
> okay
> if that's intended.
> 
> > 
> > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
> > ---
> >  arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +++++++++++---
> >  1 file changed, 11 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > index 380281f312d8..4edbb9fcdce0 100644
> > --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > @@ -132,9 +132,17 @@ mux: mux-controller {
> >                       };
> >               };
> > 
> > -             reset@611010008 {
> > -                     compatible = "microchip,sparx5-chip-reset";
> > -                     reg = <0x6 0x11010008 0x4>;
> > +             gcb_ctrl: syscon@611010000 {
> > +                     compatible = "microchip,sparx5-gcb-syscon",
> > "syscon";
> > +                     reg = <0x6 0x11010000 0x10000>;
> > +             };
> > +
> > +             reset: reset-controller@0 {
> > +                     compatible = "microchip,sparx5-switch-reset";
> > +                     reg = <0x6 0x0 0x0>;
> 
> Your register length is 0?

Yes, I only use the syscons.

> 
> > +                     #reset-cells = <1>;
> > +                     cpu-syscon = <&cpu_ctrl>;
> 
> Can't you accomplish the same thing adding these to
> "microchip,sparx5-chip-reset"? Or possibly as a child node.
> 
> Define nodes based on h/w blocks, not as containers of things you
> happen
> to want for some driver.

Yes - I think the idea of using syscons came from another reset driver,
but it probably makes more sense to just use IO ranges directly.
I will try that out.

> 
> > +                     gcb-syscon = <&gcb_ctrl>;
> >               };
> > 
> >               uart0: serial@600100000 {
> > --
> > 2.29.2
> > 

Thanks for your comments

BR
Steen



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Re: [PATCH v4 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver

[Steen Hegelund]

Hi Rob,

On Fri, 2021-02-05 at 16:35 -0600, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Wed, Jan 20, 2021 at 09:19:21AM +0100, Steen Hegelund wrote:
> > This provides reset driver support for the Microchip Sparx5 PCB134
> > and
> > PCB135 reference boards.
> 
> This isn't a compatible change. You need an explanation why that's
> okay
> if that's intended.

I am not entirely sure that I get your point.

The change (adding the reset driver) is new, and it is optional (but
strongly recommended) for the  clients to use it, so will this be a
incompatible change?

I can certainly add a an explanation.  Would that be needed here in the
bindings, or where do you suggest?


> 
> > 
> > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
> > ---
> >  arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +++++++++++---
> >  1 file changed, 11 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > index 380281f312d8..4edbb9fcdce0 100644
> > --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > @@ -132,9 +132,17 @@ mux: mux-controller {
> >                       };
> >               };
> > 
> > -             reset@611010008 {
> > -                     compatible = "microchip,sparx5-chip-reset";
> > -                     reg = <0x6 0x11010008 0x4>;
> > +             gcb_ctrl: syscon@611010000 {
> > +                     compatible = "microchip,sparx5-gcb-syscon",
> > "syscon";
> > +                     reg = <0x6 0x11010000 0x10000>;
> > +             };
> > +
> > +             reset: reset-controller@0 {
> > +                     compatible = "microchip,sparx5-switch-reset";
> > +                     reg = <0x6 0x0 0x0>;
> 
> Your register length is 0?
> 
> > +                     #reset-cells = <1>;
> > +                     cpu-syscon = <&cpu_ctrl>;
> 
> Can't you accomplish the same thing adding these to
> "microchip,sparx5-chip-reset"? Or possibly as a child node.
> 
> Define nodes based on h/w blocks, not as containers of things you
> happen
> to want for some driver.
> 
> > +                     gcb-syscon = <&gcb_ctrl>;
> >               };
> > 
> >               uart0: serial@600100000 {
> > --
> > 2.29.2
> > 

Thanks for your comments

BR
Steen

Re: [PATCH v4 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver

[Steen Hegelund]

Hi Rob,

On Fri, 2021-02-05 at 16:35 -0600, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Wed, Jan 20, 2021 at 09:19:21AM +0100, Steen Hegelund wrote:
> > This provides reset driver support for the Microchip Sparx5 PCB134
> > and
> > PCB135 reference boards.
> 
> This isn't a compatible change. You need an explanation why that's
> okay
> if that's intended.

I am not entirely sure that I get your point.

The change (adding the reset driver) is new, and it is optional (but
strongly recommended) for the  clients to use it, so will this be a
incompatible change?

I can certainly add a an explanation.  Would that be needed here in the
bindings, or where do you suggest?


> 
> > 
> > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
> > ---
> >  arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +++++++++++---
> >  1 file changed, 11 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > index 380281f312d8..4edbb9fcdce0 100644
> > --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> > @@ -132,9 +132,17 @@ mux: mux-controller {
> >                       };
> >               };
> > 
> > -             reset@611010008 {
> > -                     compatible = "microchip,sparx5-chip-reset";
> > -                     reg = <0x6 0x11010008 0x4>;
> > +             gcb_ctrl: syscon@611010000 {
> > +                     compatible = "microchip,sparx5-gcb-syscon",
> > "syscon";
> > +                     reg = <0x6 0x11010000 0x10000>;
> > +             };
> > +
> > +             reset: reset-controller@0 {
> > +                     compatible = "microchip,sparx5-switch-reset";
> > +                     reg = <0x6 0x0 0x0>;
> 
> Your register length is 0?
> 
> > +                     #reset-cells = <1>;
> > +                     cpu-syscon = <&cpu_ctrl>;
> 
> Can't you accomplish the same thing adding these to
> "microchip,sparx5-chip-reset"? Or possibly as a child node.
> 
> Define nodes based on h/w blocks, not as containers of things you
> happen
> to want for some driver.
> 
> > +                     gcb-syscon = <&gcb_ctrl>;
> >               };
> > 
> >               uart0: serial@600100000 {
> > --
> > 2.29.2
> > 

Thanks for your comments

BR
Steen


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Re: [PATCH v4 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver

[Rob Herring]

On Mon, Feb 8, 2021 at 7:20 AM Steen Hegelund
<steen.hegelund@microchip.com> wrote:
>
> Hi Rob,
>
> On Fri, 2021-02-05 at 16:35 -0600, Rob Herring wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> > know the content is safe
> >
> > On Wed, Jan 20, 2021 at 09:19:21AM +0100, Steen Hegelund wrote:
> > > This provides reset driver support for the Microchip Sparx5 PCB134
> > > and
> > > PCB135 reference boards.
> >
> > This isn't a compatible change. You need an explanation why that's
> > okay
> > if that's intended.
>
> I am not entirely sure that I get your point.
>
> The change (adding the reset driver) is new, and it is optional (but
> strongly recommended) for the  clients to use it, so will this be a
> incompatible change?

I'm assuming something used "microchip,sparx5-chip-reset"?

> I can certainly add a an explanation.  Would that be needed here in the
> bindings, or where do you suggest?

Just need to spell out why dropping that is okay in the commit msg.
But I guess what this looks like will change anyways.

Rob

Re: [PATCH v4 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver

[Rob Herring]

On Mon, Feb 8, 2021 at 7:20 AM Steen Hegelund
<steen.hegelund@microchip.com> wrote:
>
> Hi Rob,
>
> On Fri, 2021-02-05 at 16:35 -0600, Rob Herring wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> > know the content is safe
> >
> > On Wed, Jan 20, 2021 at 09:19:21AM +0100, Steen Hegelund wrote:
> > > This provides reset driver support for the Microchip Sparx5 PCB134
> > > and
> > > PCB135 reference boards.
> >
> > This isn't a compatible change. You need an explanation why that's
> > okay
> > if that's intended.
>
> I am not entirely sure that I get your point.
>
> The change (adding the reset driver) is new, and it is optional (but
> strongly recommended) for the  clients to use it, so will this be a
> incompatible change?

I'm assuming something used "microchip,sparx5-chip-reset"?

> I can certainly add a an explanation.  Would that be needed here in the
> bindings, or where do you suggest?

Just need to spell out why dropping that is okay in the commit msg.
But I guess what this looks like will change anyways.

Rob

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