From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bin Meng Date: Thu, 21 Jan 2021 23:00:13 +0800 Subject: [PATCH 5/7] riscv: Change phys_addr_t and phys_size_t to 64-bit In-Reply-To: <20210121150015.25558-1-bmeng.cn@gmail.com> References: <20210121150015.25558-1-bmeng.cn@gmail.com> Message-ID: <20210121150015.25558-6-bmeng.cn@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Bin Meng phys_addr_t and phys_size_t are currently defined as `unsigned long`, but RV32 supports 34-bit physical address, hence both phys_addr_t and phys_size_t should be defined to 64-bit using `unsigned long long`. Signed-off-by: Bin Meng --- arch/riscv/include/asm/types.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index b800b2d221..49f7a5d6b3 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -35,8 +35,8 @@ typedef u64 dma_addr_t; typedef u32 dma_addr_t; #endif -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; #endif /* __KERNEL__ */ -- 2.25.1