From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBF09C433E0 for ; Thu, 21 Jan 2021 17:52:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 734FF23A5C for ; Thu, 21 Jan 2021 17:52:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389131AbhAURr5 (ORCPT ); Thu, 21 Jan 2021 12:47:57 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:51870 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389120AbhAURrm (ORCPT ); Thu, 21 Jan 2021 12:47:42 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 10LHkdW4043759; Thu, 21 Jan 2021 11:46:39 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1611251199; bh=LtCWC+zfplDvxwmdpuGPDRkT7qfes0Jn/RdPmeQXLiU=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=DDkIwG12oHc3YjxVXd1LhaxwzB79AzfjBjnJT02VUEeVIPVh0PDueP7EMLUq/5/QE j5ir/k0TEEPyXMNOKwCIcMSoJscxUY/X3dKOXmgOQADtbknPIbQe0qit/K9JsPZzbi bv7bQa/Sx/1L2WqTd5C6dqSzJRaP0JntOS7Pu2Oo= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 10LHkddc026988 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 21 Jan 2021 11:46:39 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 21 Jan 2021 11:46:39 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 21 Jan 2021 11:46:38 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 10LHkdwJ016319; Thu, 21 Jan 2021 11:46:39 -0600 Date: Thu, 21 Jan 2021 11:46:39 -0600 From: Nishanth Menon To: Suman Anna CC: Dave Gerlach , , , Rob Herring , Tony Lindgren , Vignesh Raghavendra , Sekhar Nori , Kishon Vijay Abraham , Lokesh Vutla , Aswath Govindraju Subject: Re: [PATCH v3 3/5] arm64: dts: ti: Add support for AM642 SoC Message-ID: <20210121174639.jqbvem6b4ozd3six@sterling> References: <20210120202532.9011-1-d-gerlach@ti.com> <20210120202532.9011-4-d-gerlach@ti.com> <197af185-d2ea-3c76-d0bf-714485f8f195@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <197af185-d2ea-3c76-d0bf-714485f8f195@ti.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11:25-20210121, Suman Anna wrote: > On 1/20/21 2:25 PM, Dave Gerlach wrote: > > The AM642 SoC belongs to the K3 Multicore SoC architecture platform, > > providing advanced system integration to enable applications such as > > Motor Drives, PLC, Remote IO and IoT Gateways. > > > > Some highlights of this SoC are: > > * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F > > MCUs, and a single Cortex-M4F. > > * Two Gigabit Industrial Communication Subsystems (ICSSG). > > * Integrated Ethernet switch supporting up to a total of two external > > ports. > > * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory > > controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other > > peripherals. > > * Centralized System Controller for Security, Power, and Resource > > Management (DMSC). > > > > See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) > > for further details: https://www.ti.com/lit/pdf/spruim2 > > > > Introduce basic support for the AM642 SoC to enable ramdisk or MMC > > boot. Introduce the sdhci, i2c, spi, and uart MAIN domain periperhals > > under cbass_main and the i2c, spi, and uart MCU domain periperhals > > under cbass_mcu. > > > > Signed-off-by: Faiz Abbas > > Signed-off-by: Aswath Govindraju > > Hmm, there are a few pieces contributed by me, so please do add > > Signed-off-by: Suman Anna Sure, thanks.. [...] > > + > > + sdhci0: mmc@fa10000 { > > + compatible = "ti,am64-sdhci-8bit"; > > Hmm, I tried booting this series on top of 5.11-rc1 + Nishanth's current > ti-k3-dts-next. So, boot of these patches using this baseline fails when using > MMC rootfs, but is ok when using initramfs. This particular compatible and the > corresponding driver change are only in linux-next coming through couple of > patches from the MMC subsystem. > > I am not sure why we would be including stuff that's dependent on some other > patches being merged from a different sub-system? Strangely, this ought to be > caught by dtbs_check, but it is not throwing any errors. > > IMHO, these should only be added if you have no other external dependencies > especially when you are applying on a 5.11-rc baseline. The MMC pull-requests > would not go through arm-soc either. > Yes, I am aware of this - this is no different from integration we have done in the past as well.. intent is to get bindings in via subsystem trees and dts changes via arm-soc. I always insist that basic ramdisk boot always in the basic introduction tree. mmc, nfs are add-ons that get added via subsystem tree and I host the dts changes - in this case every dts node binding is fine with subsystems already queued in linux-next. And this is no different from what I have noticed on other ARM SoC maintainer trees as well. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DE95C433DB for ; Thu, 21 Jan 2021 17:48:13 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A935D21973 for ; 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Thu, 21 Jan 2021 11:46:39 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 21 Jan 2021 11:46:39 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 21 Jan 2021 11:46:38 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 10LHkdwJ016319; Thu, 21 Jan 2021 11:46:39 -0600 Date: Thu, 21 Jan 2021 11:46:39 -0600 From: Nishanth Menon To: Suman Anna Subject: Re: [PATCH v3 3/5] arm64: dts: ti: Add support for AM642 SoC Message-ID: <20210121174639.jqbvem6b4ozd3six@sterling> References: <20210120202532.9011-1-d-gerlach@ti.com> <20210120202532.9011-4-d-gerlach@ti.com> <197af185-d2ea-3c76-d0bf-714485f8f195@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <197af185-d2ea-3c76-d0bf-714485f8f195@ti.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210121_124645_069371_22EB1F0B X-CRM114-Status: GOOD ( 24.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Vignesh Raghavendra , Dave Gerlach , Tony Lindgren , Sekhar Nori , Kishon Vijay Abraham , Lokesh Vutla , Rob Herring , Aswath Govindraju , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11:25-20210121, Suman Anna wrote: > On 1/20/21 2:25 PM, Dave Gerlach wrote: > > The AM642 SoC belongs to the K3 Multicore SoC architecture platform, > > providing advanced system integration to enable applications such as > > Motor Drives, PLC, Remote IO and IoT Gateways. > > > > Some highlights of this SoC are: > > * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F > > MCUs, and a single Cortex-M4F. > > * Two Gigabit Industrial Communication Subsystems (ICSSG). > > * Integrated Ethernet switch supporting up to a total of two external > > ports. > > * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory > > controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other > > peripherals. > > * Centralized System Controller for Security, Power, and Resource > > Management (DMSC). > > > > See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) > > for further details: https://www.ti.com/lit/pdf/spruim2 > > > > Introduce basic support for the AM642 SoC to enable ramdisk or MMC > > boot. Introduce the sdhci, i2c, spi, and uart MAIN domain periperhals > > under cbass_main and the i2c, spi, and uart MCU domain periperhals > > under cbass_mcu. > > > > Signed-off-by: Faiz Abbas > > Signed-off-by: Aswath Govindraju > > Hmm, there are a few pieces contributed by me, so please do add > > Signed-off-by: Suman Anna Sure, thanks.. [...] > > + > > + sdhci0: mmc@fa10000 { > > + compatible = "ti,am64-sdhci-8bit"; > > Hmm, I tried booting this series on top of 5.11-rc1 + Nishanth's current > ti-k3-dts-next. So, boot of these patches using this baseline fails when using > MMC rootfs, but is ok when using initramfs. This particular compatible and the > corresponding driver change are only in linux-next coming through couple of > patches from the MMC subsystem. > > I am not sure why we would be including stuff that's dependent on some other > patches being merged from a different sub-system? Strangely, this ought to be > caught by dtbs_check, but it is not throwing any errors. > > IMHO, these should only be added if you have no other external dependencies > especially when you are applying on a 5.11-rc baseline. The MMC pull-requests > would not go through arm-soc either. > Yes, I am aware of this - this is no different from integration we have done in the past as well.. intent is to get bindings in via subsystem trees and dts changes via arm-soc. I always insist that basic ramdisk boot always in the basic introduction tree. mmc, nfs are add-ons that get added via subsystem tree and I host the dts changes - in this case every dts node binding is fine with subsystems already queued in linux-next. And this is no different from what I have noticed on other ARM SoC maintainer trees as well. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel