From: Simon Glass <sjg@chromium.org>
To: u-boot@lists.denx.de
Subject: [PATCH 02/11] x86: coral: Support TPM and RTC in SPL
Date: Thu, 21 Jan 2021 13:57:07 -0700 [thread overview]
Message-ID: <20210121205716.964652-3-sjg@chromium.org> (raw)
In-Reply-To: <20210121205716.964652-1-sjg@chromium.org>
Update the devicetree so that the TPM and RTC can be used in SPL. Also
enable the pins used for getting the memory configuration settings while
we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/x86/dts/chromebook_coral.dts | 20 +++++++++++++++++++-
arch/x86/include/asm/arch-apollolake/iomap.h | 3 +++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index bfbdd517d1f..2ffe3b423c3 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/x86-gpio.h>
/include/ "skeleton.dtsi"
@@ -99,6 +100,7 @@
clk: clock {
compatible = "intel,apl-clk";
#clock-cells = <1>;
+ u-boot,dm-pre-reloc;
};
cpus {
@@ -139,6 +141,7 @@
};
acpi_gpe: general-purpose-events {
+ u-boot,dm-pre-reloc;
reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
compatible = "intel,acpi-gpe";
interrupt-controller;
@@ -417,8 +420,10 @@
};
i2c_2: i2c2 at 16,2 {
- compatible = "intel,apl-i2c";
+ compatible = "intel,apl-i2c", "snps,designware-i2c-pci";
reg = <0x0200b210 0 0 0 0>;
+ early-regs = <IOMAP_I2C2_BASE 0x1000>;
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
@@ -429,6 +434,7 @@
tpm: tpm at 50 {
reg = <0x50>;
compatible = "google,cr50";
+ u-boot,dm-pre-reloc;
u-boot,i2c-offset-len = <0>;
ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
interrupts-extended = <&acpi_gpe GPIO_28_IRQ
@@ -589,6 +595,7 @@
u-boot,dm-pre-reloc;
cros_ec: cros-ec {
u-boot,dm-pre-proper;
+ u-boot,dm-vpl;
compatible = "google,cros-ec-lpc";
reg = <0x204 1 0x200 1 0x880 0x80>;
@@ -664,6 +671,11 @@
PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
+
+ PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */
+ PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */
+ PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/
+ PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */
>;
};
@@ -1217,3 +1229,9 @@
PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */
>;
};
+
+&rtc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h
index 21c5f33021a..a4ea1507073 100644
--- a/arch/x86/include/asm/arch-apollolake/iomap.h
+++ b/arch/x86/include/asm/arch-apollolake/iomap.h
@@ -33,6 +33,9 @@
#define SRAM_SIZE_2 (4 * KiB)
#endif
+/* Early address for I2C port 2 */
+#define IOMAP_I2C2_BASE (0xfe020000 + 2 * 0x1000)
+
/*
* Use UART2. To use UART1 you need to set '2' to '1', change device tree serial
* node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE.
--
2.30.0.280.ga3ce27912f-goog
next prev parent reply other threads:[~2021-01-21 20:57 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-21 20:57 [PATCH 00/11] More minor clean-ups and improvements Simon Glass
2021-01-21 20:57 ` [PATCH 01/11] spl: Tidy up SPL/TPL malloc sizes Simon Glass
2021-01-21 20:57 ` Simon Glass [this message]
2021-01-21 20:57 ` [PATCH 03/11] i2c: desigware: Add an alias for Intel Apollo Lake Simon Glass
2021-01-26 5:17 ` Heiko Schocher
2021-01-30 21:27 ` Simon Glass
2021-01-21 20:57 ` [PATCH 04/11] sandbox: Disable I2C emulators in SPL Simon Glass
2021-01-26 5:19 ` Heiko Schocher
2021-01-30 21:27 ` Simon Glass
2021-01-21 20:57 ` [PATCH 05/11] dm: core: Don't inline dev_read...() calls with of-platdata Simon Glass
2021-01-21 20:57 ` [PATCH 06/11] clk: Add debugging for return values Simon Glass
2021-01-21 20:57 ` [PATCH 07/11] clk: x86: Correct the driver name Simon Glass
2021-01-21 20:57 ` [PATCH 08/11] dm: core: Add a comment about pinctrl_select_state() Simon Glass
2021-01-21 20:57 ` [PATCH 09/11] dm: core: Update ofnode_read_fmap_entry() to read hashes Simon Glass
2021-01-21 20:57 ` [PATCH 10/11] Add a symlink for ctype.h Simon Glass
2021-01-21 20:57 ` [PATCH 11/11] binman: Print a debug message when binman selects a node Simon Glass
2021-01-30 21:26 ` Simon Glass
2021-01-30 21:26 ` [PATCH 10/11] Add a symlink for ctype.h Simon Glass
2021-01-30 21:27 ` [PATCH 08/11] dm: core: Add a comment about pinctrl_select_state() Simon Glass
2021-01-30 21:27 ` [PATCH 07/11] clk: x86: Correct the driver name Simon Glass
2021-01-30 21:27 ` [PATCH 06/11] clk: Add debugging for return values Simon Glass
2021-01-30 21:27 ` [PATCH 05/11] dm: core: Don't inline dev_read...() calls with of-platdata Simon Glass
2021-01-30 21:27 ` [PATCH 02/11] x86: coral: Support TPM and RTC in SPL Simon Glass
2021-01-30 21:27 ` [PATCH 01/11] spl: Tidy up SPL/TPL malloc sizes Simon Glass
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