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Fri, 22 Jan 2021 03:56:26 -0800 (PST) From: Jean-Philippe Brucker To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Subject: [PATCH 0/3] iommu/arm-smmu-v3: TLB invalidation for SVA Date: Fri, 22 Jan 2021 12:52:55 +0100 Message-Id: <20210122115257.2502526-1-jean-philippe@linaro.org> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 Cc: Jean-Philippe Brucker , vivek.gautam@arm.com, iommu@lists.linux-foundation.org, zhangfei.gao@linaro.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" To support sharing page tables with the CPU, the SMMU can participate in Broadcast TLB Maintenance (BTM), where TLB invalidate instructions from the CPU are received by the SMMU. For platforms that do no implement BTM [1], it is still possible to use SVA, by sending all TLB invalidations through the command queue. Patch 2 implements this. This series also enables SVA for platforms that do support BTM, as an intermediate step because properly supporting BTM requires cooperating with KVM to allocate VMIDs [2]. With BTM enabled, the SMMU applies broadcast invalidations by VMID to any matching TLB entry, because there is no distinction between private and shared VMIDs like there is for ASIDs. Therefore a stage-2 domain will need a VMID that doesn't conflict with one allocated by KVM (or use the one from the corresponding VM, pinned). These patches, along with the IOPF series [3] and the quirks [4], enable SVA for the hisi accelerator that's already supported upstream. My quick performance comparison between BTM and !BTM on that platform were inconclusive. Doing invalidations via cmdq seemed to slightly reduce performance of some heavy compression jobs, but there was too much noise and not enough invalidations in my tests. This series does not depend on the IOPF one [3]. [1] https://lore.kernel.org/linux-iommu/BY5PR12MB37641E84D516054387FEE330B3CC0@BY5PR12MB3764.namprd12.prod.outlook.com/ [2] https://lore.kernel.org/linux-iommu/20200522101755.GA3453945@myrica/ [3] https://lore.kernel.org/linux-iommu/20210121123623.2060416-1-jean-philippe@linaro.org/ [4] https://lore.kernel.org/linux-pci/1610960316-28935-1-git-send-email-zhangfei.gao@linaro.org/ Jean-Philippe Brucker (3): iommu/arm-smmu-v3: Split arm_smmu_tlb_inv_range() iommu/arm-smmu-v3: Make BTM optional for SVA iommu/arm-smmu-v3: Add support for VHE drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 + .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 14 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 104 ++++++++++++------ 3 files changed, 89 insertions(+), 35 deletions(-) -- 2.30.0 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AFEBC433E0 for ; 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Fri, 22 Jan 2021 03:56:27 -0800 (PST) Received: from localhost.localdomain ([2001:1715:4e26:a7e0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id s25sm13293901wrs.49.2021.01.22.03.56.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jan 2021 03:56:26 -0800 (PST) From: Jean-Philippe Brucker To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Subject: [PATCH 0/3] iommu/arm-smmu-v3: TLB invalidation for SVA Date: Fri, 22 Jan 2021 12:52:55 +0100 Message-Id: <20210122115257.2502526-1-jean-philippe@linaro.org> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210122_065629_194003_778DB44B X-CRM114-Status: GOOD ( 12.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jean-Philippe Brucker , vivek.gautam@arm.com, eric.auger@redhat.com, iommu@lists.linux-foundation.org, Jonathan.Cameron@huawei.com, zhangfei.gao@linaro.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To support sharing page tables with the CPU, the SMMU can participate in Broadcast TLB Maintenance (BTM), where TLB invalidate instructions from the CPU are received by the SMMU. For platforms that do no implement BTM [1], it is still possible to use SVA, by sending all TLB invalidations through the command queue. Patch 2 implements this. This series also enables SVA for platforms that do support BTM, as an intermediate step because properly supporting BTM requires cooperating with KVM to allocate VMIDs [2]. With BTM enabled, the SMMU applies broadcast invalidations by VMID to any matching TLB entry, because there is no distinction between private and shared VMIDs like there is for ASIDs. Therefore a stage-2 domain will need a VMID that doesn't conflict with one allocated by KVM (or use the one from the corresponding VM, pinned). These patches, along with the IOPF series [3] and the quirks [4], enable SVA for the hisi accelerator that's already supported upstream. My quick performance comparison between BTM and !BTM on that platform were inconclusive. Doing invalidations via cmdq seemed to slightly reduce performance of some heavy compression jobs, but there was too much noise and not enough invalidations in my tests. This series does not depend on the IOPF one [3]. [1] https://lore.kernel.org/linux-iommu/BY5PR12MB37641E84D516054387FEE330B3CC0@BY5PR12MB3764.namprd12.prod.outlook.com/ [2] https://lore.kernel.org/linux-iommu/20200522101755.GA3453945@myrica/ [3] https://lore.kernel.org/linux-iommu/20210121123623.2060416-1-jean-philippe@linaro.org/ [4] https://lore.kernel.org/linux-pci/1610960316-28935-1-git-send-email-zhangfei.gao@linaro.org/ Jean-Philippe Brucker (3): iommu/arm-smmu-v3: Split arm_smmu_tlb_inv_range() iommu/arm-smmu-v3: Make BTM optional for SVA iommu/arm-smmu-v3: Add support for VHE drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 + .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 14 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 104 ++++++++++++------ 3 files changed, 89 insertions(+), 35 deletions(-) -- 2.30.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel