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From: Andre Przywara <andre.przywara@arm.com>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>
Cc: "Jernej Skrabec" <jernej.skrabec@siol.net>,
	"Samuel Holland" <samuel@sholland.org>,
	"Icenowy Zheng" <icenowy@aosc.io>,
	"Rob Herring" <robh@kernel.org>,
	"Clément Péron" <peron.clem@gmail.com>,
	"Shuosheng Huang" <huangshuosheng@allwinnertech.com>,
	"Yangtao Li" <tiny.windzz@gmail.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	linux-clk@vger.kernel.org,
	"Philipp Zabel" <p.zabel@pengutronix.de>
Subject: [PATCH v4 02/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
Date: Mon, 25 Jan 2021 15:17:52 +0000	[thread overview]
Message-ID: <20210125151811.11871-3-andre.przywara@arm.com> (raw)
In-Reply-To: <20210125151811.11871-1-andre.przywara@arm.com>

The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
---
 drivers/clk/sunxi-ng/Kconfig           |  2 +-
 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 48 ++++++++++++++++++++++++++
 2 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index ce5f5847d5d3..feeb8d2074ee 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -33,7 +33,7 @@ config SUN50I_H6_CCU
 	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 
 config SUN50I_H6_R_CCU
-	bool "Support for the Allwinner H6 PRCM CCU"
+	bool "Support for the Allwinner H6 and H616 PRCM CCU"
 	default ARM64 && ARCH_SUNXI
 	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 56e351b513f3..f8909a7ed553 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -139,6 +139,16 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
 	&w1_clk.common,
 };
 
+static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
+	&r_apb1_clk.common,
+	&r_apb2_clk.common,
+	&r_apb1_twd_clk.common,
+	&r_apb2_i2c_clk.common,
+	&r_apb2_rsb_clk.common,
+	&r_apb1_ir_clk.common,
+	&ir_clk.common,
+};
+
 static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
 	.hws	= {
 		[CLK_AR100]		= &ar100_clk.common.hw,
@@ -159,6 +169,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
 	.num	= CLK_NUMBER,
 };
 
+static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
+	.hws	= {
+		[CLK_R_AHB]		= &r_ahb_clk.hw,
+		[CLK_R_APB1]		= &r_apb1_clk.common.hw,
+		[CLK_R_APB2]		= &r_apb2_clk.common.hw,
+		[CLK_R_APB1_TWD]	= &r_apb1_twd_clk.common.hw,
+		[CLK_R_APB2_I2C]	= &r_apb2_i2c_clk.common.hw,
+		[CLK_R_APB2_RSB]	= &r_apb2_rsb_clk.common.hw,
+		[CLK_R_APB1_IR]		= &r_apb1_ir_clk.common.hw,
+		[CLK_IR]		= &ir_clk.common.hw,
+	},
+	.num	= CLK_NUMBER,
+};
+
 static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
 	[RST_R_APB1_TIMER]	=  { 0x11c, BIT(16) },
 	[RST_R_APB1_TWD]	=  { 0x12c, BIT(16) },
@@ -170,6 +194,13 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
 	[RST_R_APB1_W1]		=  { 0x1ec, BIT(16) },
 };
 
+static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
+	[RST_R_APB1_TWD]	=  { 0x12c, BIT(16) },
+	[RST_R_APB2_I2C]	=  { 0x19c, BIT(16) },
+	[RST_R_APB2_RSB]	=  { 0x1bc, BIT(16) },
+	[RST_R_APB1_IR]		=  { 0x1cc, BIT(16) },
+};
+
 static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
 	.ccu_clks	= sun50i_h6_r_ccu_clks,
 	.num_ccu_clks	= ARRAY_SIZE(sun50i_h6_r_ccu_clks),
@@ -180,6 +211,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
 	.num_resets	= ARRAY_SIZE(sun50i_h6_r_ccu_resets),
 };
 
+static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
+	.ccu_clks	= sun50i_h616_r_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun50i_h616_r_ccu_clks),
+
+	.hw_clks	= &sun50i_h616_r_hw_clks,
+
+	.resets		= sun50i_h616_r_ccu_resets,
+	.num_resets	= ARRAY_SIZE(sun50i_h616_r_ccu_resets),
+};
+
 static void __init sunxi_r_ccu_init(struct device_node *node,
 				    const struct sunxi_ccu_desc *desc)
 {
@@ -200,3 +241,10 @@ static void __init sun50i_h6_r_ccu_setup(struct device_node *node)
 }
 CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
 	       sun50i_h6_r_ccu_setup);
+
+static void __init sun50i_h616_r_ccu_setup(struct device_node *node)
+{
+	sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
+	       sun50i_h616_r_ccu_setup);
-- 
2.17.5


WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>
Cc: "Jernej Skrabec" <jernej.skrabec@siol.net>,
	"Samuel Holland" <samuel@sholland.org>,
	"Yangtao Li" <tiny.windzz@gmail.com>,
	"Michael Turquette" <mturquette@baylibre.com>,
	linux-kernel@vger.kernel.org, "Stephen Boyd" <sboyd@kernel.org>,
	linux-sunxi@googlegroups.com,
	"Clément Péron" <peron.clem@gmail.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Shuosheng Huang" <huangshuosheng@allwinnertech.com>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	"Icenowy Zheng" <icenowy@aosc.io>
Subject: [PATCH v4 02/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
Date: Mon, 25 Jan 2021 15:17:52 +0000	[thread overview]
Message-ID: <20210125151811.11871-3-andre.przywara@arm.com> (raw)
In-Reply-To: <20210125151811.11871-1-andre.przywara@arm.com>

The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
---
 drivers/clk/sunxi-ng/Kconfig           |  2 +-
 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 48 ++++++++++++++++++++++++++
 2 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index ce5f5847d5d3..feeb8d2074ee 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -33,7 +33,7 @@ config SUN50I_H6_CCU
 	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 
 config SUN50I_H6_R_CCU
-	bool "Support for the Allwinner H6 PRCM CCU"
+	bool "Support for the Allwinner H6 and H616 PRCM CCU"
 	default ARM64 && ARCH_SUNXI
 	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 56e351b513f3..f8909a7ed553 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -139,6 +139,16 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
 	&w1_clk.common,
 };
 
+static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
+	&r_apb1_clk.common,
+	&r_apb2_clk.common,
+	&r_apb1_twd_clk.common,
+	&r_apb2_i2c_clk.common,
+	&r_apb2_rsb_clk.common,
+	&r_apb1_ir_clk.common,
+	&ir_clk.common,
+};
+
 static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
 	.hws	= {
 		[CLK_AR100]		= &ar100_clk.common.hw,
@@ -159,6 +169,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
 	.num	= CLK_NUMBER,
 };
 
+static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
+	.hws	= {
+		[CLK_R_AHB]		= &r_ahb_clk.hw,
+		[CLK_R_APB1]		= &r_apb1_clk.common.hw,
+		[CLK_R_APB2]		= &r_apb2_clk.common.hw,
+		[CLK_R_APB1_TWD]	= &r_apb1_twd_clk.common.hw,
+		[CLK_R_APB2_I2C]	= &r_apb2_i2c_clk.common.hw,
+		[CLK_R_APB2_RSB]	= &r_apb2_rsb_clk.common.hw,
+		[CLK_R_APB1_IR]		= &r_apb1_ir_clk.common.hw,
+		[CLK_IR]		= &ir_clk.common.hw,
+	},
+	.num	= CLK_NUMBER,
+};
+
 static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
 	[RST_R_APB1_TIMER]	=  { 0x11c, BIT(16) },
 	[RST_R_APB1_TWD]	=  { 0x12c, BIT(16) },
@@ -170,6 +194,13 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
 	[RST_R_APB1_W1]		=  { 0x1ec, BIT(16) },
 };
 
+static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
+	[RST_R_APB1_TWD]	=  { 0x12c, BIT(16) },
+	[RST_R_APB2_I2C]	=  { 0x19c, BIT(16) },
+	[RST_R_APB2_RSB]	=  { 0x1bc, BIT(16) },
+	[RST_R_APB1_IR]		=  { 0x1cc, BIT(16) },
+};
+
 static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
 	.ccu_clks	= sun50i_h6_r_ccu_clks,
 	.num_ccu_clks	= ARRAY_SIZE(sun50i_h6_r_ccu_clks),
@@ -180,6 +211,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
 	.num_resets	= ARRAY_SIZE(sun50i_h6_r_ccu_resets),
 };
 
+static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
+	.ccu_clks	= sun50i_h616_r_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun50i_h616_r_ccu_clks),
+
+	.hw_clks	= &sun50i_h616_r_hw_clks,
+
+	.resets		= sun50i_h616_r_ccu_resets,
+	.num_resets	= ARRAY_SIZE(sun50i_h616_r_ccu_resets),
+};
+
 static void __init sunxi_r_ccu_init(struct device_node *node,
 				    const struct sunxi_ccu_desc *desc)
 {
@@ -200,3 +241,10 @@ static void __init sun50i_h6_r_ccu_setup(struct device_node *node)
 }
 CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
 	       sun50i_h6_r_ccu_setup);
+
+static void __init sun50i_h616_r_ccu_setup(struct device_node *node)
+{
+	sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
+	       sun50i_h616_r_ccu_setup);
-- 
2.17.5


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  parent reply	other threads:[~2021-01-25 15:39 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-25 15:17 [PATCH v4 00/21] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara
2021-01-25 15:17 ` Andre Przywara
2021-01-25 15:17 ` [PATCH v4 01/21] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 Andre Przywara
2021-01-25 15:17   ` Andre Przywara
2021-01-25 15:17 ` Andre Przywara [this message]
2021-01-25 15:17   ` [PATCH v4 02/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU Andre Przywara
2021-01-25 15:17 ` [PATCH v4 03/21] clk: sunxi-ng: Add support for the Allwinner H616 CCU Andre Przywara
2021-01-25 15:17   ` Andre Przywara
2021-01-25 15:17 ` [PATCH v4 04/21] dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ) Andre Przywara
2021-01-25 15:17   ` Andre Przywara
2021-01-25 15:17 ` [PATCH v4 05/21] Input: axp20x-pek: Bail out if AXP has no interrupt line connected Andre Przywara
2021-01-25 15:17   ` Andre Przywara
2021-01-25 15:17 ` [PATCH v4 06/21] mfd: axp20x: Allow AXP chips without interrupt lines Andre Przywara
2021-01-25 15:17   ` Andre Przywara
2021-01-25 15:17 ` [PATCH v4 07/21] dt-bindings: sram: sunxi-sram: Add H616 compatible string Andre Przywara
2021-01-25 15:17   ` Andre Przywara
2021-01-25 15:17 ` [PATCH v4 08/21] soc: sunxi: sram: Add support for more than one EMAC clock Andre Przywara
2021-01-25 15:17   ` Andre Przywara
2021-01-25 15:17 ` [PATCH v4 09/21] dt-bindings: watchdog: sun4i: Add H616 compatible string Andre Przywara
2021-01-25 15:17   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 10/21] dt-bindings: i2c: mv64xxx: " Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 11/21] dt-bindings: media: IR: Add H616 IR " Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 12/21] dt-bindings: rtc: sun6i: Add H616 " Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 22:51   ` Alexandre Belloni
2021-01-25 22:51     ` Alexandre Belloni
2021-01-26  0:14     ` Andre Przywara
2021-01-26  0:14       ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 13/21] dt-bindings: spi: sunxi: " Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 14/21] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 15/21] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 16/21] dt-bindings: usb: Add H616 compatible string Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 17/21] dt-bindings: usb: sunxi-musb: " Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 18/21] phy: sun4i-usb: Add support for the H616 USB PHY Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 20/21] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-25 15:18 ` [PATCH v4 21/21] arm64: dts: allwinner: Add OrangePi Zero 2 .dts Andre Przywara
2021-01-25 15:18   ` Andre Przywara
2021-01-26 12:07 ` [PATCH v4 00/21] arm64: sunxi: Initial Allwinner H616 SoC support Maxime Ripard
2021-01-26 12:07   ` Maxime Ripard
2021-01-27 17:15 ` (subset) " Mark Brown
2021-01-27 17:29   ` Andre Przywara
2021-01-27 17:29     ` Andre Przywara

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