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Date:   Mon, 25 Jan 2021 15:23:19 -0400
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     Shiraz Saleem <shiraz.saleem@intel.com>
CC:     <dledford@redhat.com>, <kuba@kernel.org>, <davem@davemloft.net>,
        <linux-rdma@vger.kernel.org>, <gregkh@linuxfoundation.org>,
        <netdev@vger.kernel.org>, <david.m.ertman@intel.com>,
        <anthony.l.nguyen@intel.com>,
        Mustafa Ismail <mustafa.ismail@intel.com>
Subject: Re: [PATCH 09/22] RDMA/irdma: Implement HW Admin Queue OPs
Message-ID: <20210125192319.GW4147@nvidia.com>
References: <20210122234827.1353-1-shiraz.saleem@intel.com>
 <20210122234827.1353-10-shiraz.saleem@intel.com>
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On Fri, Jan 22, 2021 at 05:48:14PM -0600, Shiraz Saleem wrote:
> +#define LS_64_1(val, bits)	((u64)(uintptr_t)(val) << (bits))
> +#define RS_64_1(val, bits)	((u64)(uintptr_t)(val) >> (bits))
> +#define LS_32_1(val, bits)	((u32)((val) << (bits)))
> +#define RS_32_1(val, bits)	((u32)((val) >> (bits)))
> +#define LS_64(val, field)	(((u64)(val) << field ## _S) & (field ## _M))
> +#define RS_64(val, field)	((u64)((val) & field ## _M) >> field ## _S)
> +#define LS_32(val, field)	(((val) << field ## _S) & (field ## _M))
> +#define RS_32(val, field)	(((val) & field ## _M) >> field ## _S)

Yikes, why can't this use the normal GENMASK/FIELD_PREP infrastructure
like the other new drivers are now doing?

EFA is not a perfect example, but EFA_GET/EFA_SET are the macros I
would expect to see, just without the _MASK thing.

IBA_GET/SET shows how to do that pattern

> +#define FLD_LS_64(dev, val, field)	\
> +	(((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
> +#define FLD_RS_64(dev, val, field)	\
> +	((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
> +#define FLD_LS_32(dev, val, field)	\
> +	(((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
> +#define FLD_RS_32(dev, val, field)	\
> +	((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])

Is it because the register access is programmable? That shouldn't be a
significant problem.

> +#define IRDMA_CQPSQ_QHASH_QS_HANDLE_S 0
> +#define IRDMA_CQPSQ_QHASH_QS_HANDLE_M ((u64)0x3ff << IRDMA_CQPSQ_QHASH_QS_HANDLE_S)

All of this is particularly painful

A bit of time with coccinelle would probably fix all of this

Jason