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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id p4sm3799500oib.24.2021.01.25.13.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jan 2021 13:37:59 -0800 (PST) Received: (nullmailer pid 1048034 invoked by uid 1000); Mon, 25 Jan 2021 21:37:58 -0000 Date: Mon, 25 Jan 2021 15:37:58 -0600 From: Rob Herring To: Muhammad Husaini Zulkifli Cc: ulf.hansson@linaro.org, broonie@kernel.org, lgirdwood@gmail.com, devicetree@vger.kernel.org, adrian.hunter@intel.com, michal.simek@xilinx.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, andriy.shevchenko@intel.com, Rashmi.A@intel.com, mahesh.r.vaidya@intel.com Subject: Re: [PATCH v1 9/9] mmc: sdhci-of-arasan: Add UHS-1 support for Keem Bay SOC Message-ID: <20210125213758.GA1026926@robh.at.kernel.org> References: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> <20210114152700.21916-10-muhammad.husaini.zulkifli@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210114152700.21916-10-muhammad.husaini.zulkifli@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 14, 2021 at 11:27:00PM +0800, Muhammad Husaini Zulkifli wrote: > Keem Bay SOC can support dual voltage operations for GPIO SD pins to > either 1.8V or 3.3V for bus IO line power. In order to operate the GPIOs > line for Clk, Cmd and Data on Keem Bay hardware, it is important to > configure the supplied voltage applied to their I/O Rail and the output > of the I²C expander pin. Final Voltage applied on the GPIOs line are > dependent by both supplied voltage rail and expander pin output as it is > been set after passing through the voltage sense resistor. > > Keem Bay hardware is somewhat unique in the way of how IO bus line > voltage are been controlled. > > Expander pin output is controlled by gpio-regulator. Voltage rail output > is controlled by Keem Bay SD regulator. Keem Bay SD regulator encapsulated > the Secure Monitor Calling Convention (SMCCC) to communicate with Trusted > Firmware during set voltage operation. > > Signed-off-by: Muhammad Husaini Zulkifli > Acked-by: Adrian Hunter > Acked-by: Andy Shevchenko > --- > drivers/mmc/host/sdhci-of-arasan.c | 263 +++++++++++++++++++++++++++++ > 1 file changed, 263 insertions(+) > + u32 otap_delay, sel_clk_buffer; > + > + phys = of_parse_phandle(dev->of_node, "phys", 0); Normally, you'd use the phy API here. Though not required from a DT perspective. > + if (!phys) { > + dev_err(dev, "Can't get phys for sd0\n"); > + return -ENODEV; > + } > + > + of_property_read_u32(phys, "intel,keembay-emmc-phy-otap-dly", &otap_delay); > + of_property_read_u32(phys, "intel,keembay-emmc-phy-sel-clkbuf", &sel_clk_buffer); Not doucmented? For property names, I'd leave out the SoC name. Might want to use it in the next chip. Rob