From: Bin Meng <bmeng.cn@gmail.com>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Jean-Christophe Dubois" <jcd@tribudubois.net>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH v9 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8
Date: Fri, 29 Jan 2021 21:23:21 +0800 [thread overview]
Message-ID: <20210129132323.30946-9-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
Current implementation of the imx spi controller expects the burst
length to be multiple of 8, which is the most common use case.
In case the burst length is not what we expect, log it to give user
a chance to notice it, and round it up to be multiple of 8.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Changes in v9:
- Do the LOG_UNIMP when the unsupported burst length value is written,
rather than where it is used.
- Squash the 2 LOG_UNIMP warnings down into one line
Changes in v5:
- round up the burst length to be multiple of 8
Changes in v4:
- s/normal/common/ in the commit message
- log the burst length value in the log message
Changes in v3:
- new patch: log unimplemented burst length
hw/ssi/imx_spi.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 2fb65498c3..41fe199c9f 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -128,7 +128,14 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s)
static uint32_t imx_spi_burst_length(IMXSPIState *s)
{
- return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+ uint32_t burst;
+
+ burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+ if (burst % 8) {
+ burst = ROUND_UP(burst, 8);
+ }
+
+ return burst;
}
static bool imx_spi_is_enabled(IMXSPIState *s)
@@ -328,6 +335,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
IMXSPIState *s = opaque;
uint32_t index = offset >> 2;
uint32_t change_mask;
+ uint32_t burst;
if (index >= ECSPI_MAX) {
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
@@ -380,6 +388,13 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
case ECSPI_CONREG:
s->regs[ECSPI_CONREG] = value;
+ burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+ if (burst % 8) {
+ qemu_log_mask(LOG_UNIMP,
+ "[%s]%s: burst length %d not supported: rounding up to next multiple of 8\n",
+ TYPE_IMX_SPI, __func__, burst);
+ }
+
if (!imx_spi_is_enabled(s)) {
/* device is disabled, so this is a soft reset */
imx_spi_soft_reset(s);
--
2.25.1
next prev parent reply other threads:[~2021-01-29 13:33 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-29 13:23 [PATCH v9 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-29 13:23 ` [PATCH v9 01/10] hw/ssi: imx_spi: Use a macro for number of chip selects supported Bin Meng
2021-01-29 13:23 ` [PATCH v9 02/10] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Bin Meng
2021-01-29 13:23 ` [PATCH v9 03/10] hw/ssi: imx_spi: Remove pointless variable initialization Bin Meng
2021-01-29 13:23 ` [PATCH v9 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Bin Meng
2021-01-29 14:00 ` Philippe Mathieu-Daudé
2021-01-29 13:23 ` [PATCH v9 05/10] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Bin Meng
2021-01-29 13:23 ` [PATCH v9 06/10] hw/ssi: imx_spi: Rework imx_spi_write() " Bin Meng
2021-01-29 13:23 ` [PATCH v9 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled Bin Meng
2021-01-29 13:23 ` Bin Meng [this message]
2021-01-29 13:23 ` [PATCH v9 09/10] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Bin Meng
2021-01-29 13:23 ` [PATCH v9 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness Bin Meng
2021-02-02 11:39 ` [PATCH v9 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Peter Maydell
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