From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60CD9C433E0 for ; Sat, 30 Jan 2021 09:58:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2BCFA64DCC for ; Sat, 30 Jan 2021 09:58:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232079AbhA3J6B (ORCPT ); Sat, 30 Jan 2021 04:58:01 -0500 Received: from mga12.intel.com ([192.55.52.136]:24253 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232683AbhA3DAb (ORCPT ); Fri, 29 Jan 2021 22:00:31 -0500 IronPort-SDR: rUMr80GEYNWdBdgKZQRWrVoh2G+jo7YUP5I9QkATxm0moDNnya3VdqXRpmrzb27gppWOm+45am VNDZUFWh/T6A== X-IronPort-AV: E=McAfee;i="6000,8403,9879"; a="159675267" X-IronPort-AV: E=Sophos;i="5.79,387,1602572400"; d="scan'208";a="159675267" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2021 18:21:29 -0800 IronPort-SDR: rMK9oS01LngBYi77Q3Ky5ty3MxIj74cIa8nhW1+pNBpc6PLOJ7fSo55A/b7uAFtUKDzZnc23PP GP6U+HbmnmlA== X-IronPort-AV: E=Sophos;i="5.79,387,1602572400"; d="scan'208";a="431263326" Received: from smtp.ostc.intel.com ([10.54.29.231]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2021 18:21:29 -0800 Received: from mtg-dev.jf.intel.com (mtg-dev.jf.intel.com [10.54.74.10]) by smtp.ostc.intel.com (Postfix) with ESMTP id 9C54E6371; Fri, 29 Jan 2021 18:21:29 -0800 (PST) Received: by mtg-dev.jf.intel.com (Postfix, from userid 1000) id 905A3363674; Fri, 29 Jan 2021 18:21:29 -0800 (PST) From: mgross@linux.intel.com To: markgross@kernel.org, mgross@linux.intel.com, arnd@arndb.de, bp@suse.de, damien.lemoal@wdc.com, dragan.cvetic@xilinx.com, gregkh@linuxfoundation.org, corbet@lwn.net, palmerdabbelt@google.com, paul.walmsley@sifive.com, peng.fan@nxp.com, robh+dt@kernel.org, shawnguo@kernel.org, jassisinghbrar@gmail.com Cc: linux-kernel@vger.kernel.org, Paul Murphy , devicetree@vger.kernel.org, Daniele Alessandrelli Subject: [PATCH v4 06/34] dt-bindings: Add bindings for Keem Bay VPU IPC driver Date: Fri, 29 Jan 2021 18:20:56 -0800 Message-Id: <20210130022124.65083-42-mgross@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210130022124.65083-1-mgross@linux.intel.com> References: <20210130022124.65083-1-mgross@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Paul Murphy Add DT bindings documentation for the Keem Bay VPU IPC driver. Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Mark Gross Co-developed-by: Daniele Alessandrelli Signed-off-by: Paul Murphy Signed-off-by: Daniele Alessandrelli Signed-off-by: Mark Gross --- .../soc/intel/intel,keembay-vpu-ipc.yaml | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml diff --git a/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml new file mode 100644 index 000000000000..9dae8ab4c723 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) Intel Corporation. All rights reserved. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-vpu-ipc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Keem Bay VPU IPC + +maintainers: + - Paul Murphy + - Daniele Alessandrelli + +description: + This binding provides support for the Vision Processing Unit (VPU) found on + the Intel Keem Bay SoC. + + The VPU is started and controlled by SoC CPU, which is in charge of loading + the VPU firmware. The SoC CPU can communicate with the VPU firmware using an + Inter-Processor Communication (IPC) mechanism. + +properties: + compatible: + oneOf: + - items: + - const: intel,keembay-vpu-ipc + + reg: + items: + - description: NCE WDT registers + - description: NCE TIM_GEN_CONFIG registers + - description: MSS WDT registers + - description: MSS TIM_GEN_CONFIG registers + + reg-names: + items: + - const: nce_wdt + - const: nce_tim_cfg + - const: mss_wdt + - const: mss_tim_cfg + + memory-region: + items: + - description: reference to the VPU reserved memory region + - description: reference to the X509 reserved memory region + - description: reference to the MSS IPC area + + clocks: + items: + - description: cpu clock + - description: pll 0 out 0 rate + - description: pll 0 out 1 rate + - description: pll 0 out 2 rate + - description: pll 0 out 3 rate + - description: pll 1 out 0 rate + - description: pll 1 out 1 rate + - description: pll 1 out 2 rate + - description: pll 1 out 3 rate + - description: pll 2 out 0 rate + - description: pll 2 out 1 rate + - description: pll 2 out 2 rate + - description: pll 2 out 3 rate + + clock-names: + items: + - const: cpu_clock + - const: pll_0_out_0 + - const: pll_0_out_1 + - const: pll_0_out_2 + - const: pll_0_out_3 + - const: pll_1_out_0 + - const: pll_1_out_1 + - const: pll_1_out_2 + - const: pll_1_out_3 + - const: pll_2_out_0 + - const: pll_2_out_1 + - const: pll_2_out_2 + - const: pll_2_out_3 + + interrupts: + items: + - description: number of NCE sub-system WDT timeout IRQ + - description: number of MSS sub-system WDT timeout IRQ + + interrupt-names: + items: + - const: nce_wdt + - const: mss_wdt + + intel,keembay-vpu-ipc-imr: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: + Isolated Memory Region (IMR) number that the runtime service must use to + protect the VPU memory region before authentication. + + intel,keembay-vpu-ipc-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: The VPU ID to be passed to the VPU firmware. + +additionalProperties: False + +examples: + - | + #include + vpu-ipc@3f00209c { + compatible = "intel,keembay-vpu-ipc"; + reg = <0x3f00209c 0x10>, + <0x3f003008 0x4>, + <0x2082009c 0x10>, + <0x20821008 0x4>; + reg-names = "nce_wdt", + "nce_tim_cfg", + "mss_wdt", + "mss_tim_cfg"; + memory-region = <&vpu_reserved>, + <&vpu_x509_reserved>, + <&mss_ipc_reserved>; + clocks = <&scmi_clk 0>, + <&scmi_clk 0>, + <&scmi_clk 1>, + <&scmi_clk 2>, + <&scmi_clk 3>, + <&scmi_clk 4>, + <&scmi_clk 5>, + <&scmi_clk 6>, + <&scmi_clk 7>, + <&scmi_clk 8>, + <&scmi_clk 9>, + <&scmi_clk 10>, + <&scmi_clk 11>; + clock-names = "cpu_clock", + "pll_0_out_0", "pll_0_out_1", + "pll_0_out_2", "pll_0_out_3", + "pll_1_out_0", "pll_1_out_1", + "pll_1_out_2", "pll_1_out_3", + "pll_2_out_0", "pll_2_out_1", + "pll_2_out_2", "pll_2_out_3"; + interrupts = , + ; + interrupt-names = "nce_wdt", "mss_wdt"; + intel,keembay-vpu-ipc-imr = <9>; + intel,keembay-vpu-ipc-id = <0>; + }; -- 2.17.1