From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6E6DC433E6 for ; Mon, 1 Feb 2021 12:32:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7809464EA1 for ; Mon, 1 Feb 2021 12:32:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7809464EA1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=TJC2IIP2sxC+2lS+eT3kvG2GHCIatpL95I/wkQL7jAs=; b=FTS+FZI68pRgGqrOgek1OIq5Gg vUaWupaqNRMSV378HMnOVVcN7ea0Znr6SHlxFiZx9eRWG++uyN53XRdUYaGpmVfo6rRx+AHUu9hI7 J70sm7Iy1QRwv5cmO+o155v4oL79INeJMsj1BMQThaXg6qcknxuGzqQgTiKVqL1sbm/3KAw7Dyccr ghkEeM7nVd4jBVpxJbL999pQEf2MV6JQvIWZBV3MCkqRSqAzveHD91Zp7XDsZq2L+4OKtB4g/iCKI Cj2VQLhDGTpCrvbYRFmorBerp39SPUox/xCeRCbM4cUJ6+hxLyabuiIRiTULyPzU1DiGiQBFI+44o 8BfSXEOw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6YLn-0002po-GC; Mon, 01 Feb 2021 12:30:39 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6YLj-0002p8-Sm for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 12:30:37 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id AF7EF64E99; Mon, 1 Feb 2021 12:30:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612182634; bh=azBBPeRQssv810znDNb2yjuYSDWxu5BHHarYvFQm0Ws=; h=From:To:Cc:Subject:Date:From; b=gAAHVHaqIOuXCHexWDgK/hYqEaRDLvmGs6D4odIhD9YDbvVHd9g23+GBt4M98E039 OC0giFZY+jyhVkRVHGLq0cFf5C2WlWIDGf53VY4rEV1BKYqNgMyFafBlK40a8LH/Tm p0X+YafM+Be5piWwY57R5JVqQFq9yHGLbVq3MRfTKLTXpqHocYsOG/rDld4Rqym5/6 JonpxUnXgs4OiMriaAo4D53UAlbg+ucRqJQXJpJ1w/PEgIW+Q+pYo2J2R+OBOX+6uf PN3BQSHDqgPJLlm+EcJ3Vwl3KonSaDOegjm2Mh/rXIV6Bk8C6NqiaLlv4VHF2472hd 5Dee0Rpb7FSZQ== From: Mark Brown To: Catalin Marinas , Will Deacon Subject: [PATCH v7 0/2] arm64/sve: Improve performance when handling SVE access traps Date: Mon, 1 Feb 2021 12:28:59 +0000 Message-Id: <20210201122901.11331-1-broonie@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_073036_356647_D6087AD9 X-CRM114-Status: GOOD ( 22.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Julien Grall , Zhang Lei , Mark Brown , Dave Martin , linux-arm-kernel@lists.infradead.org, Daniel Kiss Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch series aims to improve the performance of handling SVE access traps, earlier versions were originally written by Julien Gral but based on discussions on previous versions the patches have been substantially reworked to use a different approach. The patches are now different enough that I set myself as the author, hopefully that's OK for Julien. I've marked this as RFC since it's not quite ready yet but I'd really like feedback on the overall approach, it's a big change in implementation. It needs at least one more pass for polish and while it's holding up in my testing thus far I've not done as much as I'd like yet. Per the syscall ABI, SVE registers will be unknown after a syscall. In practice, the kernel will disable SVE and the registers will be zeroed (except the first 128 bits of each vector) on the next SVE instruction. Currently we do this by saving the FPSIMD state to memory, converting to the matching SVE state and then reloading the registers on return to userspace. This requires a lot of memory accesses that we shouldn't need, improve this by reworking the SVE state tracking so we track if we should trap on executing SVE instructions separately to if we need to save the full register state. This allows us to avoid tracking the full SVE state until we need to return to userspace and to convert directly in registers in the common case where the FPSIMD state is still in registers then. As with current mainline we disable SVE on every syscall. This may not be ideal for applications that mix SVE and syscall usage, strategies such as SH's fpu_counter may perform better but we need to assess the performance on a wider range of systems than are currently available before implementing anything. It is also possible to optimize the case when the SVE vector length is 128-bit (ie the same size as the FPSIMD vectors). This could be explored in the future, it becomes a lot easier to do with this implementation. v7: - A few minor cosmetic updates and one bugfix for fpsimd_update_current_state(). v6: - Substantially rework the patch so that TIF_SVE is now replaced by two flags TIF_SVE_EXEC and TIF_SVE_FULL_REGS. - Return to disabling SVE after every syscall as for current mainine rather than leaving it enabled unless reset via ptrace. v5: - Rebase onto v5.10-rc2. - Explicitly support the case where TIF_SVE and TIF_SVE_NEEDS_FLUSH are set simultaneously, though this is not currently expected to happen. - Extensively revised the documentation for TIF_SVE and TIF_SVE_NEEDS_FLUSH to hopefully make things more clear together with the above, I hope this addresses the comments on the prior version but it really needs fresh eyes to tell if that's actually the case. - Make comments in ptrace.c more precise. - Remove some redundant checks for system_has_sve(). v4: - Rebase onto v5.9-rc2 - Address review comments from Dave Martin, mostly documentation but also some refactorings to ensure we don't check capabilities multiple times and the addition of some WARN_ONs to make sure assumptions we are making about what TIF_ flags can be set when are true. v3: - Rebased to current kernels. - Addressed review comments from v2, mostly around tweaks in the documentation. Mark Brown (2): arm64/sve: Split TIF_SVE into separate execute and register state flags arm64/sve: Rework SVE trap access to minimise memory access arch/arm64/include/asm/fpsimd.h | 2 + arch/arm64/include/asm/thread_info.h | 3 +- arch/arm64/kernel/entry-fpsimd.S | 5 + arch/arm64/kernel/fpsimd.c | 203 +++++++++++++++++++-------- arch/arm64/kernel/process.c | 7 +- arch/arm64/kernel/ptrace.c | 8 +- arch/arm64/kernel/signal.c | 15 +- arch/arm64/kernel/syscall.c | 3 +- arch/arm64/kvm/fpsimd.c | 6 +- 9 files changed, 179 insertions(+), 73 deletions(-) base-commit: 7c53f6b671f4aba70ff15e1b05148b10d58c2837 -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel