From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1112C433DB for ; Mon, 1 Feb 2021 15:37:39 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 67E9364DAE for ; Mon, 1 Feb 2021 15:37:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 67E9364DAE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2g9OFI5chXLd9ZEn05ZHs80XiVB6wXrPDuKDcfl0gjU=; b=WuiSzJ/HPbZsDJntYvkSrrNR1 zkRKGdIk2GQBLA0k8b36oGjh2ndmVtE1sqwQUbcJgtFB5sTeSG3/8uJyoCJeBQvimj4liaM1ZmbvV /6qYbY3S0R7F1Im0j9YI8lpvlmKa9corXPVudjlBjNhq236hEvy5Y4WdcT3TP4ObYZkVYGrgwWZC3 zmVItPCEZNN8j5IMRy5wSAoZORtOSfcCRiZkNnbcGqcLQK+c0sump2q+KGjO4pH4oTkxF9xs5hRdQ iSMqtzDHa4GjdOCDOGumLOnfdCjNWa/8ufr0G9/yjzPVDMO8B8iM3glIvrnUNfWh+p3mTtFlJqHGw y29BrjpUg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6bFX-0005A0-Gq; Mon, 01 Feb 2021 15:36:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6bFU-00059a-F4 for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 15:36:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A2215101E; Mon, 1 Feb 2021 07:36:13 -0800 (PST) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 85E3A3F71A; Mon, 1 Feb 2021 07:36:12 -0800 (PST) Date: Mon, 1 Feb 2021 15:35:53 +0000 From: Dave Martin To: Mark Brown Subject: Re: [PATCH v7 1/2] arm64/sve: Split TIF_SVE into separate execute and register state flags Message-ID: <20210201153550.GE13952@arm.com> References: <20210201122901.11331-1-broonie@kernel.org> <20210201122901.11331-2-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210201122901.11331-2-broonie@kernel.org> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_103620_575354_E4C33EE6 X-CRM114-Status: GOOD ( 19.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Julien Grall , Catalin Marinas , Zhang Lei , Will Deacon , linux-arm-kernel@lists.infradead.org, Daniel Kiss Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Feb 01, 2021 at 12:29:00PM +0000, Mark Brown wrote: > Currently we have a single flag TIF_SVE which says that a task is > allowed to execute SVE instructions without trapping and also that full > SVE register state is stored for the task. This results in us doing > extra work storing and restoring the full SVE register state even in > those cases where the ABI is that only the first 128 bits of the Z0-V31 > registers which are shared with the FPSIMD V0-V31 are valid. > > In order to allow us to avoid these overheads split TIF_SVE up so that > we have two separate flags, TIF_SVE_EXEC which allows execution of SVE > instructions without trapping and TIF_SVE_FULL_REGS which indicates that > the full SVE register state is stored. If both are set the behaviour is > as currently, if TIF_SVE_EXEC is set without TIF_SVE_FULL_REGS then we > save and restore only the FPSIMD registers until we return to userspace > with TIF_SVE_EXEC enabled at which point we convert the FPSIMD registers > to SVE. It is not meaningful to have TIF_SVE_FULL_REGS set without > TIF_SVE_EXEC. > > This patch is intended only to split the flags, it does not take > avantage of the ability to set the flags independently and the new > state with TIF_SVE_EXEC only should not be observed. > > This is based on earlier work by Julien Gral implementing a slightly > different approach. > > Signed-off-by: Mark Brown While I'm trying to get my head around this, can you sketch out the mapping between the old flag combinations (including Julien's TIF_SVE_NEEDS_FLUSH) and yours? [...] Cheers ---Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel