From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0662C433E0 for ; Tue, 2 Feb 2021 12:25:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E9AB64F05 for ; Tue, 2 Feb 2021 12:25:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229913AbhBBMZZ convert rfc822-to-8bit (ORCPT ); Tue, 2 Feb 2021 07:25:25 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]:2476 "EHLO frasgout.his.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229511AbhBBMZV (ORCPT ); Tue, 2 Feb 2021 07:25:21 -0500 Received: from fraeml706-chm.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4DVP3k1LV8z67jvS; Tue, 2 Feb 2021 20:18:26 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml706-chm.china.huawei.com (10.206.15.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2106.2; Tue, 2 Feb 2021 13:24:36 +0100 Received: from localhost (10.47.79.68) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 2 Feb 2021 12:24:35 +0000 Date: Tue, 2 Feb 2021 12:23:50 +0000 From: Jonathan Cameron To: Ben Widawsky CC: , , Chris Browy , Dan Williams , "David Hildenbrand" , Igor Mammedov , "Ira Weiny" , Marcel Apfelbaum , Markus Armbruster , Philippe =?ISO-8859-1?Q?Mathieu-Da?= =?ISO-8859-1?Q?ud=E9?= , Vishal Verma , "John Groves (jgroves)" , "Michael S. Tsirkin" Subject: Re: [RFC PATCH v3 04/31] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Message-ID: <20210202122350.000047f3@Huawei.com> In-Reply-To: <20210202005948.241655-5-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> <20210202005948.241655-5-ben.widawsky@intel.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Originating-IP: [10.47.79.68] X-ClientProxiedBy: lhreml745-chm.china.huawei.com (10.201.108.195) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org On Mon, 1 Feb 2021 16:59:21 -0800 Ben Widawsky wrote: > This implements all device MMIO up to the first capability. That > includes the CXL Device Capabilities Array Register, as well as all of > the CXL Device Capability Header Registers. The latter are filled in as > they are implemented in the following patches. > > Endianness and alignment are managed by softmmu memory core. > > Signed-off-by: Ben Widawsky A few trivials > --- > hw/cxl/cxl-device-utils.c | 105 ++++++++++++++++++++++++++++++++++++ > hw/cxl/meson.build | 1 + > include/hw/cxl/cxl_device.h | 27 +++++++++- > 3 files changed, 132 insertions(+), 1 deletion(-) > create mode 100644 hw/cxl/cxl-device-utils.c > > diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c > new file mode 100644 > index 0000000000..bb15ad9a0f > --- /dev/null > +++ b/hw/cxl/cxl-device-utils.c > @@ -0,0 +1,105 @@ > +/* > + * CXL Utility library for devices > + * > + * Copyright(C) 2020 Intel Corporation. > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See the > + * COPYING file in the top-level directory. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "hw/cxl/cxl.h" > + > +/* > + * Device registers have no restrictions per the spec, and so fall back to the > + * default memory mapped register rules in 8.2: > + * Software shall use CXL.io Memory Read and Write to access memory mapped > + * register defined in this section. Unless otherwise specified, software > + * shall restrict the accesses width based on the following: > + * • A 32 bit register shall be accessed as a 1 Byte, 2 Bytes or 4 Bytes odd spacing > + * quantity. > + * • A 64 bit register shall be accessed as a 1 Byte, 2 Bytes, 4 Bytes or 8 > + * Bytes > + * • The address shall be a multiple of the access width, e.g. when > + * accessing a register as a 4 Byte quantity, the address shall be > + * multiple of 4. > + * • The accesses shall map to contiguous bytes.If these rules are not > + * followed, the behavior is undefined > + */ > + > +static uint64_t caps_reg_read(void *opaque, hwaddr offset, unsigned size) > +{ > + CXLDeviceState *cxl_dstate = opaque; > + > + return cxl_dstate->caps_reg_state32[offset / 4]; > +} > + > +static uint64_t dev_reg_read(void *opaque, hwaddr offset, unsigned size) > +{ > + return 0; > +} > + > +static const MemoryRegionOps dev_ops = { > + .read = dev_reg_read, > + .write = NULL, /* status register is read only */ > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 1, > + .max_access_size = 8, > + .unaligned = false, > + }, > + .impl = { > + .min_access_size = 1, > + .max_access_size = 8, > + }, > +}; > + > +static const MemoryRegionOps caps_ops = { > + .read = caps_reg_read, > + .write = NULL, /* caps registers are read only */ > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 1, > + .max_access_size = 8, > + .unaligned = false, > + }, > + .impl = { > + .min_access_size = 4, > + .max_access_size = 4, > + }, > +}; > + > +void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstate) > +{ > + /* This will be a BAR, so needs to be rounded up to pow2 for PCI spec */ > + memory_region_init(&cxl_dstate->device_registers, obj, "device-registers", > + pow2ceil(CXL_MMIO_SIZE)); > + > + memory_region_init_io(&cxl_dstate->caps, obj, &caps_ops, cxl_dstate, > + "cap-array", CXL_DEVICE_REGISTERS_OFFSET - 0); Specifying a size in terms of the offset of another region isn't exactly intuitive so perhaps a comment on why or better yet actually use a size parameter covering what is there rather than simply the region below the CXL_DEVICE_REGISTERS_OFFSET. > + memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate, > + "device-status", CXL_DEVICE_REGISTERS_LENGTH); > + > + memory_region_add_subregion(&cxl_dstate->device_registers, 0, > + &cxl_dstate->caps); > + memory_region_add_subregion(&cxl_dstate->device_registers, > + CXL_DEVICE_REGISTERS_OFFSET, > + &cxl_dstate->device); > +} > + > +static void device_reg_init_common(CXLDeviceState *cxl_dstate) { } > + > +void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) > +{ > + uint32_t *cap_hdrs = cxl_dstate->caps_reg_state32; > + const int cap_count = 1; > + > + /* CXL Device Capabilities Array Register */ > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0); > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1); > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY2, CAP_COUNT, cap_count); > + > + cxl_device_cap_init(cxl_dstate, DEVICE, 1); > + device_reg_init_common(cxl_dstate); > +} > diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build > index 00c3876a0f..47154d6850 100644 > --- a/hw/cxl/meson.build > +++ b/hw/cxl/meson.build > @@ -1,3 +1,4 @@ > softmmu_ss.add(when: 'CONFIG_CXL', if_true: files( > 'cxl-component-utils.c', > + 'cxl-device-utils.c', > )) > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h > index a85f250503..f3bcf19410 100644 > --- a/include/hw/cxl/cxl_device.h > +++ b/include/hw/cxl/cxl_device.h > @@ -58,6 +58,8 @@ > #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ > #define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ > #define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ > +#define CXL_CAPS_SIZE \ > + (CXL_DEVICE_CAP_REG_SIZE * CXL_DEVICE_CAPS_MAX + 1) /* +1 for header */ > > #define CXL_DEVICE_REGISTERS_OFFSET 0x80 /* Read comment above */ > #define CXL_DEVICE_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ > @@ -70,11 +72,18 @@ > #define CXL_MAILBOX_REGISTERS_LENGTH \ > (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) > > +#define CXL_MMIO_SIZE \ > + CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \ > + CXL_MAILBOX_REGISTERS_LENGTH > + > typedef struct cxl_device_state { > MemoryRegion device_registers; > > /* mmio for device capabilities array - 8.2.8.2 */ > - MemoryRegion caps; > + struct { > + MemoryRegion caps; > + uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; > + }; With this unnamed,w hat is the benefit of having these two in a struct? The naming makes it clear they are related anyway. > > /* mmio for the device status registers 8.2.8.3 */ > MemoryRegion device; > @@ -126,6 +135,22 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET) > CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ > CXL_DEVICE_CAP_REG_SIZE) > > +#define cxl_device_cap_init(dstate, reg, cap_id) \ > + do { \ > + uint32_t *cap_hdrs = dstate->caps_reg_state32; \ > + int which = R_CXL_DEV_##reg##_CAP_HDR0; \ > + cap_hdrs[which] = \ > + FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_ID, cap_id); \ > + cap_hdrs[which] = FIELD_DP32( \ > + cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1); \ > + cap_hdrs[which + 1] = \ > + FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \ > + CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \ > + cap_hdrs[which + 2] = \ > + FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \ > + CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \ > + } while (0) > + > REG32(CXL_DEV_MAILBOX_CAP, 0) > FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) > FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1) From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87E3EC433E9 for ; Tue, 2 Feb 2021 12:29:19 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB28064F4E for ; Tue, 2 Feb 2021 12:29:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DB28064F4E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=Huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:34592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6uo1-0003VK-Q1 for qemu-devel@archiver.kernel.org; Tue, 02 Feb 2021 07:29:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6ujd-0007dZ-1Q for qemu-devel@nongnu.org; Tue, 02 Feb 2021 07:24:45 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]:2093) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6ujZ-00079e-W4 for qemu-devel@nongnu.org; Tue, 02 Feb 2021 07:24:44 -0500 Received: from fraeml706-chm.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4DVP3k1LV8z67jvS; Tue, 2 Feb 2021 20:18:26 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml706-chm.china.huawei.com (10.206.15.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2106.2; Tue, 2 Feb 2021 13:24:36 +0100 Received: from localhost (10.47.79.68) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 2 Feb 2021 12:24:35 +0000 Date: Tue, 2 Feb 2021 12:23:50 +0000 From: Jonathan Cameron To: Ben Widawsky Subject: Re: [RFC PATCH v3 04/31] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Message-ID: <20210202122350.000047f3@Huawei.com> In-Reply-To: <20210202005948.241655-5-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> <20210202005948.241655-5-ben.widawsky@intel.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.47.79.68] X-ClientProxiedBy: lhreml745-chm.china.huawei.com (10.201.108.195) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, Markus Armbruster , "Michael S. Tsirkin" , Igor Mammedov , Dan Williams , Ira Weiny , Philippe =?ISO-8859-1?Q?Mathieu-Da?= =?ISO-8859-1?Q?ud=E9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, 1 Feb 2021 16:59:21 -0800 Ben Widawsky wrote: > This implements all device MMIO up to the first capability. That > includes the CXL Device Capabilities Array Register, as well as all of > the CXL Device Capability Header Registers. The latter are filled in as > they are implemented in the following patches. >=20 > Endianness and alignment are managed by softmmu memory core. >=20 > Signed-off-by: Ben Widawsky A few trivials > --- > hw/cxl/cxl-device-utils.c | 105 ++++++++++++++++++++++++++++++++++++ > hw/cxl/meson.build | 1 + > include/hw/cxl/cxl_device.h | 27 +++++++++- > 3 files changed, 132 insertions(+), 1 deletion(-) > create mode 100644 hw/cxl/cxl-device-utils.c >=20 > diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c > new file mode 100644 > index 0000000000..bb15ad9a0f > --- /dev/null > +++ b/hw/cxl/cxl-device-utils.c > @@ -0,0 +1,105 @@ > +/* > + * CXL Utility library for devices > + * > + * Copyright(C) 2020 Intel Corporation. > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See = the > + * COPYING file in the top-level directory. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "hw/cxl/cxl.h" > + > +/* > + * Device registers have no restrictions per the spec, and so fall back = to the > + * default memory mapped register rules in 8.2: > + * Software shall use CXL.io Memory Read and Write to access memory ma= pped > + * register defined in this section. Unless otherwise specified, softw= are > + * shall restrict the accesses width based on the following: > + * =E2=80=A2 A 32 bit register shall be accessed as a 1 Byte, 2 Byte= s or 4 Bytes odd spacing > + * quantity. > + * =E2=80=A2 A 64 bit register shall be accessed as a 1 Byte, 2 Bytes,= 4 Bytes or 8 > + * Bytes > + * =E2=80=A2 The address shall be a multiple of the access width, e.g.= when > + * accessing a register as a 4 Byte quantity, the address shall be > + * multiple of 4. > + * =E2=80=A2 The accesses shall map to contiguous bytes.If these rules= are not > + * followed, the behavior is undefined > + */ > + > +static uint64_t caps_reg_read(void *opaque, hwaddr offset, unsigned size) > +{ > + CXLDeviceState *cxl_dstate =3D opaque; > + > + return cxl_dstate->caps_reg_state32[offset / 4]; > +} > + > +static uint64_t dev_reg_read(void *opaque, hwaddr offset, unsigned size) > +{ > + return 0; > +} > + > +static const MemoryRegionOps dev_ops =3D { > + .read =3D dev_reg_read, > + .write =3D NULL, /* status register is read only */ > + .endianness =3D DEVICE_LITTLE_ENDIAN, > + .valid =3D { > + .min_access_size =3D 1, > + .max_access_size =3D 8, > + .unaligned =3D false, > + }, > + .impl =3D { > + .min_access_size =3D 1, > + .max_access_size =3D 8, > + }, > +}; > + > +static const MemoryRegionOps caps_ops =3D { > + .read =3D caps_reg_read, > + .write =3D NULL, /* caps registers are read only */ > + .endianness =3D DEVICE_LITTLE_ENDIAN, > + .valid =3D { > + .min_access_size =3D 1, > + .max_access_size =3D 8, > + .unaligned =3D false, > + }, > + .impl =3D { > + .min_access_size =3D 4, > + .max_access_size =3D 4, > + }, > +}; > + > +void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dst= ate) > +{ > + /* This will be a BAR, so needs to be rounded up to pow2 for PCI spe= c */ > + memory_region_init(&cxl_dstate->device_registers, obj, "device-regis= ters", > + pow2ceil(CXL_MMIO_SIZE)); > + > + memory_region_init_io(&cxl_dstate->caps, obj, &caps_ops, cxl_dstate, > + "cap-array", CXL_DEVICE_REGISTERS_OFFSET - 0); Specifying a size in terms of the offset of another region isn't exactly=20 intuitive so perhaps a comment on why or better yet actually use a size parameter covering what is there rather than simply the region below the CXL_DEVICE_REGISTERS_OFFSET. > + memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate, > + "device-status", CXL_DEVICE_REGISTERS_LENGTH); > + > + memory_region_add_subregion(&cxl_dstate->device_registers, 0, > + &cxl_dstate->caps); > + memory_region_add_subregion(&cxl_dstate->device_registers, > + CXL_DEVICE_REGISTERS_OFFSET, > + &cxl_dstate->device); > +} > + > +static void device_reg_init_common(CXLDeviceState *cxl_dstate) { } > + > +void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) > +{ > + uint32_t *cap_hdrs =3D cxl_dstate->caps_reg_state32; > + const int cap_count =3D 1; > + > + /* CXL Device Capabilities Array Register */ > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0); > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1); > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY2, CAP_COUNT, cap_count); > + > + cxl_device_cap_init(cxl_dstate, DEVICE, 1); > + device_reg_init_common(cxl_dstate); > +} > diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build > index 00c3876a0f..47154d6850 100644 > --- a/hw/cxl/meson.build > +++ b/hw/cxl/meson.build > @@ -1,3 +1,4 @@ > softmmu_ss.add(when: 'CONFIG_CXL', if_true: files( > 'cxl-component-utils.c', > + 'cxl-device-utils.c', > )) > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h > index a85f250503..f3bcf19410 100644 > --- a/include/hw/cxl/cxl_device.h > +++ b/include/hw/cxl/cxl_device.h > @@ -58,6 +58,8 @@ > #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ > #define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ > #define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ > +#define CXL_CAPS_SIZE \ > + (CXL_DEVICE_CAP_REG_SIZE * CXL_DEVICE_CAPS_MAX + 1) /* +1 for header= */ > =20 > #define CXL_DEVICE_REGISTERS_OFFSET 0x80 /* Read comment above */ > #define CXL_DEVICE_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ > @@ -70,11 +72,18 @@ > #define CXL_MAILBOX_REGISTERS_LENGTH \ > (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) > =20 > +#define CXL_MMIO_SIZE \ > + CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \ > + CXL_MAILBOX_REGISTERS_LENGTH > + > typedef struct cxl_device_state { > MemoryRegion device_registers; > =20 > /* mmio for device capabilities array - 8.2.8.2 */ > - MemoryRegion caps; > + struct { > + MemoryRegion caps; > + uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; > + }; With this unnamed,w hat is the benefit of having these two in a struct? The naming makes it clear they are related anyway. > =20 > /* mmio for the device status registers 8.2.8.3 */ > MemoryRegion device; > @@ -126,6 +135,22 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DE= VICE_CAP_HDR1_OFFSET) > CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSE= T + \ > CXL_DEVICE_CAP_REG_SIZE) > =20 > +#define cxl_device_cap_init(dstate, reg, cap_id) = \ > + do { = \ > + uint32_t *cap_hdrs =3D dstate->caps_reg_state32; = \ > + int which =3D R_CXL_DEV_##reg##_CAP_HDR0; = \ > + cap_hdrs[which] =3D = \ > + FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_ID= , cap_id); \ > + cap_hdrs[which] =3D FIELD_DP32( = \ > + cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1); = \ > + cap_hdrs[which + 1] =3D = \ > + FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, = \ > + CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); = \ > + cap_hdrs[which + 2] =3D = \ > + FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, = \ > + CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); = \ > + } while (0) > + > REG32(CXL_DEV_MAILBOX_CAP, 0) > FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) > FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1)