From: Jonathan Cameron <Jonathan.Cameron@Huawei.com> To: Ben Widawsky <ben.widawsky@intel.com> Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, "Chris Browy" <cbrowy@avery-design.com>, "Dan Williams" <dan.j.williams@intel.com>, "David Hildenbrand" <david@redhat.com>, "Igor Mammedov" <imammedo@redhat.com>, "Ira Weiny" <ira.weiny@intel.com>, "Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>, "Markus Armbruster" <armbru@redhat.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Vishal Verma" <vishal.l.verma@intel.com>, "John Groves (jgroves)" <jgroves@micron.com>, "Michael S. Tsirkin" <mst@redhat.com> Subject: Re: [RFC PATCH v3 17/31] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Date: Tue, 2 Feb 2021 19:21:35 +0000 [thread overview] Message-ID: <20210202192135.000035e9@Huawei.com> (raw) In-Reply-To: <20210202005948.241655-18-ben.widawsky@intel.com> On Mon, 1 Feb 2021 16:59:34 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > CXL host bridges themselves may have MMIO. Since host bridges don't have > a BAR they are treated as special for MMIO. > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > -- > > It's arbitrarily chosen here to pick 0xD0000000 as the base for the host > bridge MMIO. I'm not sure what the right way to find free space for > platform hardcoded things like this is. Seems like this needs to come from the machine definition. This is fairly easy for arm/virt, where there is a clearly laid out memory map. For hw/i386 I'm less sure on how to do it. Having said that, for this particular magic device, we do have a PCI EP associated with it. How about putting all the host bridge MMIO into a BAR of that rather than having it separate. That has the added advantage of making it discoverable from firmware. Any normal system is going to have this is impdef for discovery anyway. That would then let you drop the separate definition of CXLHost structure though it needs a bit of figuring out what to do with the memory window setup etc. I tried hacking it together, but not gotten it working yet. > --- > hw/pci-bridge/pci_expander_bridge.c | 53 ++++++++++++++++++++++++++++- > include/hw/cxl/cxl.h | 2 ++ > 2 files changed, 54 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c > index 5021b60435..226a8a5fff 100644 > --- a/hw/pci-bridge/pci_expander_bridge.c > +++ b/hw/pci-bridge/pci_expander_bridge.c > @@ -17,6 +17,7 @@ > #include "hw/pci/pci_host.h" > #include "hw/qdev-properties.h" > #include "hw/pci/pci_bridge.h" > +#include "hw/cxl/cxl.h" > #include "qemu/range.h" > #include "qemu/error-report.h" > #include "qemu/module.h" > @@ -70,6 +71,12 @@ struct PXBDev { > int32_t uid; > }; > > +typedef struct CXLHost { > + PCIHostState parent_obj; > + > + CXLComponentState cxl_cstate; > +} CXLHost; > + > static PXBDev *convert_to_pxb(PCIDevice *dev) > { > /* A CXL PXB's parent bus is PCIe, so the normal check won't work */ > @@ -85,6 +92,9 @@ static GList *pxb_dev_list; > > #define TYPE_PXB_HOST "pxb-host" > > +#define TYPE_PXB_CXL_HOST "pxb-cxl-host" > +#define PXB_CXL_HOST(obj) OBJECT_CHECK(CXLHost, (obj), TYPE_PXB_CXL_HOST) > + > static int pxb_bus_num(PCIBus *bus) > { > PXBDev *pxb = convert_to_pxb(bus->parent_dev); > @@ -198,6 +208,46 @@ static const TypeInfo pxb_host_info = { > .class_init = pxb_host_class_init, > }; > > +static void pxb_cxl_realize(DeviceState *dev, Error **errp) > +{ > + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); > + PCIHostState *phb = PCI_HOST_BRIDGE(dev); > + CXLHost *cxl = PXB_CXL_HOST(dev); > + CXLComponentState *cxl_cstate = &cxl->cxl_cstate; > + struct MemoryRegion *mr = &cxl_cstate->crb.component_registers; > + > + cxl_component_register_block_init(OBJECT(dev), cxl_cstate, > + TYPE_PXB_CXL_HOST); > + sysbus_init_mmio(sbd, mr); > + > + /* FIXME: support multiple host bridges. */ > + sysbus_mmio_map(sbd, 0, CXL_HOST_BASE + > + memory_region_size(mr) * pci_bus_uid(phb->bus)); > +} > + > +static void pxb_cxl_host_class_init(ObjectClass *class, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(class); > + PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class); > + > + hc->root_bus_path = pxb_host_root_bus_path; > + dc->fw_name = "cxl"; > + dc->realize = pxb_cxl_realize; > + /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */ > + dc->user_creatable = false; > +} > + > +/* > + * This is a device to handle the MMIO for a CXL host bridge. It does nothing > + * else. > + */ > +static const TypeInfo cxl_host_info = { > + .name = TYPE_PXB_CXL_HOST, > + .parent = TYPE_PCI_HOST_BRIDGE, > + .instance_size = sizeof(CXLHost), > + .class_init = pxb_cxl_host_class_init, > +}; > + > /* > * Registers the PXB bus as a child of pci host root bus. > */ > @@ -272,7 +322,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum BusType type, > dev_name = dev->qdev.id; > } > > - ds = qdev_new(TYPE_PXB_HOST); > + ds = qdev_new(type == CXL ? TYPE_PXB_CXL_HOST : TYPE_PXB_HOST); > if (type == PCIE) { > bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS); > } else if (type == CXL) { > @@ -466,6 +516,7 @@ static void pxb_register_types(void) > type_register_static(&pxb_pcie_bus_info); > type_register_static(&pxb_cxl_bus_info); > type_register_static(&pxb_host_info); > + type_register_static(&cxl_host_info); > type_register_static(&pxb_dev_info); > type_register_static(&pxb_pcie_dev_info); > type_register_static(&pxb_cxl_dev_info); > diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h > index 362cda40de..6bc344f205 100644 > --- a/include/hw/cxl/cxl.h > +++ b/include/hw/cxl/cxl.h > @@ -17,5 +17,7 @@ > #define COMPONENT_REG_BAR_IDX 0 > #define DEVICE_REG_BAR_IDX 2 > > +#define CXL_HOST_BASE 0xD0000000 > + > #endif >
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com> To: Ben Widawsky <ben.widawsky@intel.com> Cc: "David Hildenbrand" <david@redhat.com>, "Vishal Verma" <vishal.l.verma@intel.com>, "John Groves (jgroves)" <jgroves@micron.com>, "Chris Browy" <cbrowy@avery-design.com>, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, "Markus Armbruster" <armbru@redhat.com>, "Michael S. Tsirkin" <mst@redhat.com>, "Igor Mammedov" <imammedo@redhat.com>, "Dan Williams" <dan.j.williams@intel.com>, "Ira Weiny" <ira.weiny@intel.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org> Subject: Re: [RFC PATCH v3 17/31] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Date: Tue, 2 Feb 2021 19:21:35 +0000 [thread overview] Message-ID: <20210202192135.000035e9@Huawei.com> (raw) In-Reply-To: <20210202005948.241655-18-ben.widawsky@intel.com> On Mon, 1 Feb 2021 16:59:34 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > CXL host bridges themselves may have MMIO. Since host bridges don't have > a BAR they are treated as special for MMIO. > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > -- > > It's arbitrarily chosen here to pick 0xD0000000 as the base for the host > bridge MMIO. I'm not sure what the right way to find free space for > platform hardcoded things like this is. Seems like this needs to come from the machine definition. This is fairly easy for arm/virt, where there is a clearly laid out memory map. For hw/i386 I'm less sure on how to do it. Having said that, for this particular magic device, we do have a PCI EP associated with it. How about putting all the host bridge MMIO into a BAR of that rather than having it separate. That has the added advantage of making it discoverable from firmware. Any normal system is going to have this is impdef for discovery anyway. That would then let you drop the separate definition of CXLHost structure though it needs a bit of figuring out what to do with the memory window setup etc. I tried hacking it together, but not gotten it working yet. > --- > hw/pci-bridge/pci_expander_bridge.c | 53 ++++++++++++++++++++++++++++- > include/hw/cxl/cxl.h | 2 ++ > 2 files changed, 54 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c > index 5021b60435..226a8a5fff 100644 > --- a/hw/pci-bridge/pci_expander_bridge.c > +++ b/hw/pci-bridge/pci_expander_bridge.c > @@ -17,6 +17,7 @@ > #include "hw/pci/pci_host.h" > #include "hw/qdev-properties.h" > #include "hw/pci/pci_bridge.h" > +#include "hw/cxl/cxl.h" > #include "qemu/range.h" > #include "qemu/error-report.h" > #include "qemu/module.h" > @@ -70,6 +71,12 @@ struct PXBDev { > int32_t uid; > }; > > +typedef struct CXLHost { > + PCIHostState parent_obj; > + > + CXLComponentState cxl_cstate; > +} CXLHost; > + > static PXBDev *convert_to_pxb(PCIDevice *dev) > { > /* A CXL PXB's parent bus is PCIe, so the normal check won't work */ > @@ -85,6 +92,9 @@ static GList *pxb_dev_list; > > #define TYPE_PXB_HOST "pxb-host" > > +#define TYPE_PXB_CXL_HOST "pxb-cxl-host" > +#define PXB_CXL_HOST(obj) OBJECT_CHECK(CXLHost, (obj), TYPE_PXB_CXL_HOST) > + > static int pxb_bus_num(PCIBus *bus) > { > PXBDev *pxb = convert_to_pxb(bus->parent_dev); > @@ -198,6 +208,46 @@ static const TypeInfo pxb_host_info = { > .class_init = pxb_host_class_init, > }; > > +static void pxb_cxl_realize(DeviceState *dev, Error **errp) > +{ > + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); > + PCIHostState *phb = PCI_HOST_BRIDGE(dev); > + CXLHost *cxl = PXB_CXL_HOST(dev); > + CXLComponentState *cxl_cstate = &cxl->cxl_cstate; > + struct MemoryRegion *mr = &cxl_cstate->crb.component_registers; > + > + cxl_component_register_block_init(OBJECT(dev), cxl_cstate, > + TYPE_PXB_CXL_HOST); > + sysbus_init_mmio(sbd, mr); > + > + /* FIXME: support multiple host bridges. */ > + sysbus_mmio_map(sbd, 0, CXL_HOST_BASE + > + memory_region_size(mr) * pci_bus_uid(phb->bus)); > +} > + > +static void pxb_cxl_host_class_init(ObjectClass *class, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(class); > + PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class); > + > + hc->root_bus_path = pxb_host_root_bus_path; > + dc->fw_name = "cxl"; > + dc->realize = pxb_cxl_realize; > + /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */ > + dc->user_creatable = false; > +} > + > +/* > + * This is a device to handle the MMIO for a CXL host bridge. It does nothing > + * else. > + */ > +static const TypeInfo cxl_host_info = { > + .name = TYPE_PXB_CXL_HOST, > + .parent = TYPE_PCI_HOST_BRIDGE, > + .instance_size = sizeof(CXLHost), > + .class_init = pxb_cxl_host_class_init, > +}; > + > /* > * Registers the PXB bus as a child of pci host root bus. > */ > @@ -272,7 +322,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum BusType type, > dev_name = dev->qdev.id; > } > > - ds = qdev_new(TYPE_PXB_HOST); > + ds = qdev_new(type == CXL ? TYPE_PXB_CXL_HOST : TYPE_PXB_HOST); > if (type == PCIE) { > bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS); > } else if (type == CXL) { > @@ -466,6 +516,7 @@ static void pxb_register_types(void) > type_register_static(&pxb_pcie_bus_info); > type_register_static(&pxb_cxl_bus_info); > type_register_static(&pxb_host_info); > + type_register_static(&cxl_host_info); > type_register_static(&pxb_dev_info); > type_register_static(&pxb_pcie_dev_info); > type_register_static(&pxb_cxl_dev_info); > diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h > index 362cda40de..6bc344f205 100644 > --- a/include/hw/cxl/cxl.h > +++ b/include/hw/cxl/cxl.h > @@ -17,5 +17,7 @@ > #define COMPONENT_REG_BAR_IDX 0 > #define DEVICE_REG_BAR_IDX 2 > > +#define CXL_HOST_BASE 0xD0000000 > + > #endif >
next prev parent reply other threads:[~2021-02-02 19:25 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-02 0:59 [RFC PATCH v3 00/31] CXL 2.0 Support Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 01/31] hw/pci/cxl: Add a CXL component type (interface) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 02/31] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 11:48 ` Jonathan Cameron 2021-02-02 11:48 ` Jonathan Cameron 2021-02-17 18:36 ` Ben Widawsky 2021-02-11 17:08 ` Jonathan Cameron 2021-02-11 17:08 ` Jonathan Cameron 2021-02-17 16:40 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 03/31] hw/cxl/device: Introduce a CXL device (8.2.8) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 12:03 ` Jonathan Cameron 2021-02-02 12:03 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 04/31] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 12:23 ` Jonathan Cameron 2021-02-02 12:23 ` Jonathan Cameron 2021-02-17 22:15 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 05/31] hw/cxl/device: Implement basic mailbox (8.2.8.4) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 14:58 ` Jonathan Cameron 2021-02-02 14:58 ` Jonathan Cameron 2021-02-11 17:46 ` Jonathan Cameron 2021-02-18 0:55 ` Ben Widawsky 2021-02-18 16:50 ` Jonathan Cameron 2021-02-11 18:09 ` Jonathan Cameron 2021-02-11 18:09 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 06/31] hw/cxl/device: Add memory device utilities Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 07/31] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 13:44 ` Jonathan Cameron 2021-02-02 13:44 ` Jonathan Cameron 2021-02-11 17:59 ` Jonathan Cameron 2021-02-11 17:59 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 08/31] hw/cxl/device: Timestamp implementation (8.2.9.3) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 09/31] hw/cxl/device: Add log commands (8.2.9.4) + CEL Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 10/31] hw/pxb: Use a type for realizing expanders Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 13:50 ` Jonathan Cameron 2021-02-02 13:50 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 11/31] hw/pci/cxl: Create a CXL bus type Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 12/31] hw/pxb: Allow creation of a CXL PXB (host bridge) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 13/31] qtest: allow DSDT acpi table changes Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 14/31] acpi/pci: Consolidate host bridge setup Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 13:56 ` Jonathan Cameron 2021-02-02 13:56 ` Jonathan Cameron 2021-12-02 10:32 ` Jonathan Cameron 2021-12-02 10:32 ` Jonathan Cameron via 2021-02-02 0:59 ` [RFC PATCH v3 15/31] tests/acpi: remove stale allowed tables Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 16/31] hw/pci: Plumb _UID through host bridges Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 15:00 ` Jonathan Cameron 2021-02-02 15:00 ` Jonathan Cameron 2021-02-02 15:24 ` Michael S. Tsirkin 2021-02-02 15:24 ` Michael S. Tsirkin 2021-02-02 15:42 ` Ben Widawsky 2021-02-02 15:42 ` Ben Widawsky 2021-02-02 15:51 ` Michael S. Tsirkin 2021-02-02 15:51 ` Michael S. Tsirkin 2021-02-02 16:20 ` Ben Widawsky 2021-02-02 16:20 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 17/31] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 19:21 ` Jonathan Cameron [this message] 2021-02-02 19:21 ` Jonathan Cameron 2021-02-02 19:45 ` Ben Widawsky 2021-02-02 20:43 ` Jonathan Cameron 2021-02-02 21:03 ` Ben Widawsky 2021-02-02 22:06 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 18/31] acpi/pxb/cxl: Reserve host bridge MMIO Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 19/31] hw/pxb/cxl: Add "windows" for host bridges Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 20/31] hw/cxl/rp: Add a root port Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 21/31] hw/cxl/device: Add a memory device (8.2.8.5) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 14:26 ` Eric Blake 2021-02-02 15:06 ` Ben Widawsky 2021-02-02 15:06 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 22/31] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 23/31] acpi/cxl: Add _OSC implementation (9.14.2) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 24/31] tests/acpi: allow CEDT table addition Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 25/31] acpi/cxl: Create the CEDT (9.14.1) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 26/31] tests/acpi: Add new CEDT files Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 27/31] hw/cxl/device: Add some trivial commands Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 28/31] hw/cxl/device: Plumb real LSA sizing Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 29/31] hw/cxl/device: Implement get/set LSA Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 30/31] qtest/cxl: Add very basic sanity tests Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 31/31] WIP: i386/cxl: Initialize a host bridge Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 1:33 ` [RFC PATCH v3 00/31] CXL 2.0 Support no-reply 2021-02-02 1:33 ` no-reply 2021-02-03 17:42 ` Ben Widawsky 2021-02-11 18:51 ` Jonathan Cameron 2021-02-11 18:51 ` Jonathan Cameron 2021-03-11 23:27 ` [RFC PATCH] hw/mem/cxl_type3: Go back to subregions Ben Widawsky
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