* [Intel-gfx] [CI 1/3] drm/i915/gt: Move engine setup out of set_default_submission
@ 2021-02-03 6:53 Chris Wilson
2021-02-03 6:53 ` [Intel-gfx] [CI 2/3] drm/i915/gt: Move submission_method into intel_gt Chris Wilson
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Chris Wilson @ 2021-02-03 6:53 UTC (permalink / raw)
To: intel-gfx
Now that we no longer switch back and forth between guc and execlists,
we no longer need to restore the backend's vfunc and can leave them set
after initialisation. The only catch is that we lose the submission on
wedging and still need to reset the submit_request vfunc on unwedging.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
.../drm/i915/gt/intel_execlists_submission.c | 46 ++++++++---------
.../gpu/drm/i915/gt/intel_ring_submission.c | 4 --
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 50 ++++++++-----------
3 files changed, 44 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b8bd3d48b345..c98fdeb94dba 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3069,29 +3069,6 @@ static void execlists_set_default_submission(struct intel_engine_cs *engine)
engine->submit_request = execlists_submit_request;
engine->schedule = i915_schedule;
engine->execlists.tasklet.callback = execlists_submission_tasklet;
-
- engine->reset.prepare = execlists_reset_prepare;
- engine->reset.rewind = execlists_reset_rewind;
- engine->reset.cancel = execlists_reset_cancel;
- engine->reset.finish = execlists_reset_finish;
-
- engine->park = execlists_park;
- engine->unpark = NULL;
-
- engine->flags |= I915_ENGINE_SUPPORTS_STATS;
- if (!intel_vgpu_active(engine->i915)) {
- engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- if (can_preempt(engine)) {
- engine->flags |= I915_ENGINE_HAS_PREEMPTION;
- if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
- engine->flags |= I915_ENGINE_HAS_TIMESLICES;
- }
- }
-
- if (intel_engine_has_preemption(engine))
- engine->emit_bb_start = gen8_emit_bb_start;
- else
- engine->emit_bb_start = gen8_emit_bb_start_noarb;
}
static void execlists_shutdown(struct intel_engine_cs *engine)
@@ -3122,6 +3099,14 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->cops = &execlists_context_ops;
engine->request_alloc = execlists_request_alloc;
+ engine->reset.prepare = execlists_reset_prepare;
+ engine->reset.rewind = execlists_reset_rewind;
+ engine->reset.cancel = execlists_reset_cancel;
+ engine->reset.finish = execlists_reset_finish;
+
+ engine->park = execlists_park;
+ engine->unpark = NULL;
+
engine->emit_flush = gen8_emit_flush_xcs;
engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
@@ -3142,6 +3127,21 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
* until a more refined solution exists.
*/
}
+
+ engine->flags |= I915_ENGINE_SUPPORTS_STATS;
+ if (!intel_vgpu_active(engine->i915)) {
+ engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
+ if (can_preempt(engine)) {
+ engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+ if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
+ engine->flags |= I915_ENGINE_HAS_TIMESLICES;
+ }
+ }
+
+ if (intel_engine_has_preemption(engine))
+ engine->emit_bb_start = gen8_emit_bb_start;
+ else
+ engine->emit_bb_start = gen8_emit_bb_start_noarb;
}
static void logical_ring_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 9c2c605d7a92..3cb2ce503544 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -969,14 +969,10 @@ static void gen6_bsd_submit_request(struct i915_request *request)
static void i9xx_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = i9xx_submit_request;
-
- engine->park = NULL;
- engine->unpark = NULL;
}
static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
{
- i9xx_set_default_submission(engine);
engine->submit_request = gen6_bsd_submit_request;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 92688a9b6717..f72faa0b8339 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -608,35 +608,6 @@ static int guc_resume(struct intel_engine_cs *engine)
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = guc_submit_request;
- engine->schedule = i915_schedule;
- engine->execlists.tasklet.callback = guc_submission_tasklet;
-
- engine->reset.prepare = guc_reset_prepare;
- engine->reset.rewind = guc_reset_rewind;
- engine->reset.cancel = guc_reset_cancel;
- engine->reset.finish = guc_reset_finish;
-
- engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
- engine->flags |= I915_ENGINE_HAS_PREEMPTION;
-
- /*
- * TODO: GuC supports timeslicing and semaphores as well, but they're
- * handled by the firmware so some minor tweaks are required before
- * enabling.
- *
- * engine->flags |= I915_ENGINE_HAS_TIMESLICES;
- * engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- */
-
- engine->emit_bb_start = gen8_emit_bb_start;
-
- /*
- * For the breadcrumb irq to work we need the interrupts to stay
- * enabled. However, on all platforms on which we'll have support for
- * GuC submission we don't allow disabling the interrupts at runtime, so
- * we're always safe with the current flow.
- */
- GEM_BUG_ON(engine->irq_enable || engine->irq_disable);
}
static void guc_release(struct intel_engine_cs *engine)
@@ -658,6 +629,13 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
engine->cops = &guc_context_ops;
engine->request_alloc = guc_request_alloc;
+ engine->schedule = i915_schedule;
+
+ engine->reset.prepare = guc_reset_prepare;
+ engine->reset.rewind = guc_reset_rewind;
+ engine->reset.cancel = guc_reset_cancel;
+ engine->reset.finish = guc_reset_finish;
+
engine->emit_flush = gen8_emit_flush_xcs;
engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
@@ -666,6 +644,20 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
engine->emit_flush = gen12_emit_flush_xcs;
}
engine->set_default_submission = guc_set_default_submission;
+
+ engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
+ engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+
+ /*
+ * TODO: GuC supports timeslicing and semaphores as well, but they're
+ * handled by the firmware so some minor tweaks are required before
+ * enabling.
+ *
+ * engine->flags |= I915_ENGINE_HAS_TIMESLICES;
+ * engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
+ */
+
+ engine->emit_bb_start = gen8_emit_bb_start;
}
static void rcs_submission_override(struct intel_engine_cs *engine)
--
2.20.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [Intel-gfx] [CI 2/3] drm/i915/gt: Move submission_method into intel_gt 2021-02-03 6:53 [Intel-gfx] [CI 1/3] drm/i915/gt: Move engine setup out of set_default_submission Chris Wilson @ 2021-02-03 6:53 ` Chris Wilson 2021-02-03 6:53 ` [Intel-gfx] [CI 3/3] drm/i915/gt: Move CS interrupt handler to the backend Chris Wilson ` (3 subsequent siblings) 4 siblings, 0 replies; 7+ messages in thread From: Chris Wilson @ 2021-02-03 6:53 UTC (permalink / raw) To: intel-gfx Since we setup the submission method for the engines once, it is easy to assign an enum and use that instead of probing into the backends. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 8 +++++++- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 ++++++++---- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 8 -------- drivers/gpu/drm/i915/gt/intel_execlists_submission.h | 3 --- drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +++++++ drivers/gpu/drm/i915/gt/intel_reset.c | 7 +++---- drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +- drivers/gpu/drm/i915/gt/selftest_ring_submission.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 5 ----- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h | 1 - drivers/gpu/drm/i915/i915_perf.c | 10 +++++----- 11 files changed, 32 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 47ee8578e511..8d9184920c51 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -13,8 +13,9 @@ #include "i915_reg.h" #include "i915_request.h" #include "i915_selftest.h" -#include "gt/intel_timeline.h" #include "intel_engine_types.h" +#include "intel_gt_types.h" +#include "intel_timeline.h" #include "intel_workarounds.h" struct drm_printer; @@ -262,6 +263,11 @@ void intel_engine_init_active(struct intel_engine_cs *engine, #define ENGINE_MOCK 1 #define ENGINE_VIRTUAL 2 +static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine) +{ + return engine->gt->submission_method >= INTEL_SUBMISSION_GUC; +} + static inline bool intel_engine_has_preempt_reset(const struct intel_engine_cs *engine) { diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 56fb9cece71b..dab8d734e272 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -891,12 +891,16 @@ int intel_engines_init(struct intel_gt *gt) enum intel_engine_id id; int err; - if (intel_uc_uses_guc_submission(>->uc)) + if (intel_uc_uses_guc_submission(>->uc)) { + gt->submission_method = INTEL_SUBMISSION_GUC; setup = intel_guc_submission_setup; - else if (HAS_EXECLISTS(gt->i915)) + } else if (HAS_EXECLISTS(gt->i915)) { + gt->submission_method = INTEL_SUBMISSION_ELSP; setup = intel_execlists_submission_setup; - else + } else { + gt->submission_method = INTEL_SUBMISSION_RING; setup = intel_ring_submission_setup; + } for_each_engine(engine, gt, id) { err = engine_setup_common(engine); @@ -1467,7 +1471,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); } - if (intel_engine_in_guc_submission_mode(engine)) { + if (intel_engine_uses_guc(engine)) { /* nothing to print yet */ } else if (HAS_EXECLISTS(dev_priv)) { struct i915_request * const *port, *rq; diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index c98fdeb94dba..8dc52cc43f27 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1757,7 +1757,6 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive) */ GEM_BUG_ON(!tasklet_is_locked(&execlists->tasklet) && !reset_in_progress(execlists)); - GEM_BUG_ON(!intel_engine_in_execlists_submission_mode(engine)); /* * Note that csb_write, csb_status may be either in HWSP or mmio. @@ -3877,13 +3876,6 @@ void intel_execlists_show_requests(struct intel_engine_cs *engine, spin_unlock_irqrestore(&engine->active.lock, flags); } -bool -intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine) -{ - return engine->set_default_submission == - execlists_set_default_submission; -} - #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftest_execlists.c" #endif diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.h b/drivers/gpu/drm/i915/gt/intel_execlists_submission.h index a8fd7adefd82..f7bd3fccfee8 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.h +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.h @@ -41,7 +41,4 @@ int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine, const struct intel_engine_cs *master, const struct intel_engine_cs *sibling); -bool -intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine); - #endif /* __INTEL_EXECLISTS_SUBMISSION_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 91d20daca536..626af37c7790 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -29,6 +29,12 @@ struct i915_ggtt; struct intel_engine_cs; struct intel_uncore; +enum intel_submission_method { + INTEL_SUBMISSION_RING, + INTEL_SUBMISSION_ELSP, + INTEL_SUBMISSION_GUC, +}; + struct intel_gt { struct drm_i915_private *i915; struct intel_uncore *uncore; @@ -108,6 +114,7 @@ struct intel_gt { struct intel_engine_cs *engine[I915_NUM_ENGINES]; struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] [MAX_ENGINE_INSTANCE + 1]; + enum intel_submission_method submission_method; /* * Default address space (either GGTT or ppGTT depending on arch). diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 7638fb2a45f4..bf5b9f303a68 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -1113,7 +1113,6 @@ static int intel_gt_reset_engine(struct intel_engine_cs *engine) int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg) { struct intel_gt *gt = engine->gt; - bool uses_guc = intel_engine_in_guc_submission_mode(engine); int ret; ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags); @@ -1129,10 +1128,10 @@ int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg) "Resetting %s for %s\n", engine->name, msg); atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]); - if (!uses_guc) - ret = intel_gt_reset_engine(engine); - else + if (intel_engine_uses_guc(engine)) ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine); + else + ret = intel_gt_reset_engine(engine); if (ret) { /* If we fail here, we expect to fallback to a global reset */ ENGINE_TRACE(engine, "Failed to reset, err: %d\n", ret); diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c index 5d7fac383add..9304a35384aa 100644 --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c @@ -4715,7 +4715,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) SUBTEST(live_virtual_reset), }; - if (!HAS_EXECLISTS(i915)) + if (i915->gt.submission_method != INTEL_SUBMISSION_ELSP) return 0; if (intel_gt_is_wedged(&i915->gt)) diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c index 3350e7c995bc..6cd9f6bc240c 100644 --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c @@ -291,7 +291,7 @@ int intel_ring_submission_live_selftests(struct drm_i915_private *i915) SUBTEST(live_ctx_switch_wa), }; - if (HAS_EXECLISTS(i915)) + if (i915->gt.submission_method > INTEL_SUBMISSION_RING) return 0; return intel_gt_live_subtests(tests, &i915->gt); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index f72faa0b8339..17b551a0c89f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -745,8 +745,3 @@ void intel_guc_submission_init_early(struct intel_guc *guc) { guc->submission_selected = __guc_submission_selected(guc); } - -bool intel_engine_in_guc_submission_mode(const struct intel_engine_cs *engine) -{ - return engine->set_default_submission == guc_set_default_submission; -} diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h index 5f7b9e6347d0..3f7005018939 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h @@ -20,7 +20,6 @@ void intel_guc_submission_fini(struct intel_guc *guc); int intel_guc_preempt_work_create(struct intel_guc *guc); void intel_guc_preempt_work_destroy(struct intel_guc *guc); int intel_guc_submission_setup(struct intel_engine_cs *engine); -bool intel_engine_in_guc_submission_mode(const struct intel_engine_cs *engine); static inline bool intel_guc_submission_is_supported(struct intel_guc *guc) { diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 112ba5f2ce90..89665e14ab01 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1273,11 +1273,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream) case 8: case 9: case 10: - if (intel_engine_in_execlists_submission_mode(ce->engine)) { - stream->specific_ctx_id_mask = - (1U << GEN8_CTX_ID_WIDTH) - 1; - stream->specific_ctx_id = stream->specific_ctx_id_mask; - } else { + if (intel_engine_uses_guc(ce->engine)) { /* * When using GuC, the context descriptor we write in * i915 is read by GuC and rewritten before it's @@ -1296,6 +1292,10 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream) */ stream->specific_ctx_id_mask = (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1; + } else { + stream->specific_ctx_id_mask = + (1U << GEN8_CTX_ID_WIDTH) - 1; + stream->specific_ctx_id = stream->specific_ctx_id_mask; } break; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] [CI 3/3] drm/i915/gt: Move CS interrupt handler to the backend 2021-02-03 6:53 [Intel-gfx] [CI 1/3] drm/i915/gt: Move engine setup out of set_default_submission Chris Wilson 2021-02-03 6:53 ` [Intel-gfx] [CI 2/3] drm/i915/gt: Move submission_method into intel_gt Chris Wilson @ 2021-02-03 6:53 ` Chris Wilson 2021-02-03 8:11 ` [Intel-gfx] [PATCH] " Chris Wilson 2021-02-03 8:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission Patchwork ` (2 subsequent siblings) 4 siblings, 1 reply; 7+ messages in thread From: Chris Wilson @ 2021-02-03 6:53 UTC (permalink / raw) To: intel-gfx The different submission backends each have their own preferred behaviour and interrupt setup. Let each handle their own interrupts. This becomes more useful later as we to extract the use of auxiliary state in the interrupt handler that is backend specific. v2: An overabundance of caution is always justified; put a barrier on updating the irq handler so that we know that the next interrupt will be redirected towards ourselves. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++ drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +--- .../drm/i915/gt/intel_execlists_submission.c | 41 ++++++++++ drivers/gpu/drm/i915/gt/intel_gt_irq.c | 82 ++++++------------- drivers/gpu/drm/i915/gt/intel_gt_irq.h | 23 ++++++ .../gpu/drm/i915/gt/intel_ring_submission.c | 8 ++ drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 ++- drivers/gpu/drm/i915/i915_irq.c | 8 +- 9 files changed, 122 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index dab8d734e272..13ef5725ef51 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) intel_engine_set_hwsp_writemask(engine, ~0u); } +static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) +{ + GEM_DEBUG_WARN_ON(iir); +} + static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) { const struct engine_info *info = &intel_engines[id]; @@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) engine->hw_id = info->hw_id; engine->guc_id = MAKE_GUC_ID(info->class, info->instance); + engine->irq_handler = nop_irq_handler; + engine->class = info->class; engine->instance = info->instance; __sprint_engine_name(engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 9d59de5c559a..c9974de2dd00 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -402,6 +402,7 @@ struct intel_engine_cs { u32 irq_enable_mask; /* bitmask to enable ring interrupt */ void (*irq_enable)(struct intel_engine_cs *engine); void (*irq_disable)(struct intel_engine_cs *engine); + void (*irq_handler)(struct intel_engine_cs *engine, u16 iir); void (*sanitize)(struct intel_engine_cs *engine); int (*resume)(struct intel_engine_cs *engine); @@ -481,10 +482,9 @@ struct intel_engine_cs { #define I915_ENGINE_HAS_PREEMPTION BIT(2) #define I915_ENGINE_HAS_SEMAPHORES BIT(3) #define I915_ENGINE_HAS_TIMESLICES BIT(4) -#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5) -#define I915_ENGINE_IS_VIRTUAL BIT(6) -#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7) -#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8) +#define I915_ENGINE_IS_VIRTUAL BIT(5) +#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6) +#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7) unsigned int flags; /* @@ -588,12 +588,6 @@ intel_engine_has_timeslices(const struct intel_engine_cs *engine) return engine->flags & I915_ENGINE_HAS_TIMESLICES; } -static inline bool -intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine) -{ - return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; -} - static inline bool intel_engine_is_virtual(const struct intel_engine_cs *engine) { diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 8dc52cc43f27..554eaaa268a7 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -118,6 +118,7 @@ #include "intel_engine_stats.h" #include "intel_execlists_submission.h" #include "intel_gt.h" +#include "intel_gt_irq.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" #include "intel_lrc.h" @@ -2394,6 +2395,45 @@ static void execlists_submission_tasklet(struct tasklet_struct *t) rcu_read_unlock(); } +static void execlists_irq_handler(struct intel_engine_cs *engine, u16 iir) +{ + bool tasklet = false; + + if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) { + u32 eir; + + /* Upper 16b are the enabling mask, rsvd for internal errors */ + eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0); + ENGINE_TRACE(engine, "CS error: %x\n", eir); + + /* Disable the error interrupt until after the reset */ + if (likely(eir)) { + ENGINE_WRITE(engine, RING_EMR, ~0u); + ENGINE_WRITE(engine, RING_EIR, eir); + WRITE_ONCE(engine->execlists.error_interrupt, eir); + tasklet = true; + } + } + + if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) { + WRITE_ONCE(engine->execlists.yield, + ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI)); + ENGINE_TRACE(engine, "semaphore yield: %08x\n", + engine->execlists.yield); + if (del_timer(&engine->execlists.timer)) + tasklet = true; + } + + if (iir & GT_CONTEXT_SWITCH_INTERRUPT) + tasklet = true; + + if (iir & GT_RENDER_USER_INTERRUPT) + intel_engine_signal_breadcrumbs(engine); + + if (tasklet) + tasklet_hi_schedule(&engine->execlists.tasklet); +} + static void __execlists_kick(struct intel_engine_execlists *execlists) { /* Kick the tasklet for some interrupt coalescing and reset handling */ @@ -3126,6 +3166,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) * until a more refined solution exists. */ } + intel_engine_set_irq_handler(engine, execlists_irq_handler); engine->flags |= I915_ENGINE_SUPPORTS_STATS; if (!intel_vgpu_active(engine->i915)) { diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 9fc6c912a4e5..f5aa31ae8f6c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -20,48 +20,6 @@ static void guc_irq_handler(struct intel_guc *guc, u16 iir) intel_guc_to_host_event_handler(guc); } -static void -cs_irq_handler(struct intel_engine_cs *engine, u32 iir) -{ - bool tasklet = false; - - if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) { - u32 eir; - - /* Upper 16b are the enabling mask, rsvd for internal errors */ - eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0); - ENGINE_TRACE(engine, "CS error: %x\n", eir); - - /* Disable the error interrupt until after the reset */ - if (likely(eir)) { - ENGINE_WRITE(engine, RING_EMR, ~0u); - ENGINE_WRITE(engine, RING_EIR, eir); - WRITE_ONCE(engine->execlists.error_interrupt, eir); - tasklet = true; - } - } - - if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) { - WRITE_ONCE(engine->execlists.yield, - ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI)); - ENGINE_TRACE(engine, "semaphore yield: %08x\n", - engine->execlists.yield); - if (del_timer(&engine->execlists.timer)) - tasklet = true; - } - - if (iir & GT_CONTEXT_SWITCH_INTERRUPT) - tasklet = true; - - if (iir & GT_RENDER_USER_INTERRUPT) { - intel_engine_signal_breadcrumbs(engine); - tasklet |= intel_engine_needs_breadcrumb_tasklet(engine); - } - - if (tasklet) - tasklet_hi_schedule(&engine->execlists.tasklet); -} - static u32 gen11_gt_engine_identity(struct intel_gt *gt, const unsigned int bank, const unsigned int bit) @@ -122,7 +80,7 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class, engine = NULL; if (likely(engine)) - return cs_irq_handler(engine, iir); + return intel_engine_cs_irq(engine, iir); WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n", class, instance); @@ -275,9 +233,12 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) { if (gt_iir & GT_RENDER_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); + intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], + gt_iir); + if (gt_iir & ILK_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], + gt_iir); } static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) @@ -301,11 +262,16 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) { if (gt_iir & GT_RENDER_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); + intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], + gt_iir); + if (gt_iir & GT_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], + gt_iir); + if (gt_iir & GT_BLT_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[COPY_ENGINE_CLASS][0]); + intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], + gt_iir); if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | GT_BSD_CS_ERROR_INTERRUPT | @@ -324,10 +290,10 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { iir = raw_reg_read(regs, GEN8_GT_IIR(0)); if (likely(iir)) { - cs_irq_handler(gt->engine_class[RENDER_CLASS][0], - iir >> GEN8_RCS_IRQ_SHIFT); - cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0], - iir >> GEN8_BCS_IRQ_SHIFT); + intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], + iir >> GEN8_RCS_IRQ_SHIFT); + intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], + iir >> GEN8_BCS_IRQ_SHIFT); raw_reg_write(regs, GEN8_GT_IIR(0), iir); } } @@ -335,10 +301,10 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) { iir = raw_reg_read(regs, GEN8_GT_IIR(1)); if (likely(iir)) { - cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0], - iir >> GEN8_VCS0_IRQ_SHIFT); - cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1], - iir >> GEN8_VCS1_IRQ_SHIFT); + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], + iir >> GEN8_VCS0_IRQ_SHIFT); + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1], + iir >> GEN8_VCS1_IRQ_SHIFT); raw_reg_write(regs, GEN8_GT_IIR(1), iir); } } @@ -346,8 +312,8 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) if (master_ctl & GEN8_GT_VECS_IRQ) { iir = raw_reg_read(regs, GEN8_GT_IIR(3)); if (likely(iir)) { - cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0], - iir >> GEN8_VECS_IRQ_SHIFT); + intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0], + iir >> GEN8_VECS_IRQ_SHIFT); raw_reg_write(regs, GEN8_GT_IIR(3), iir); } } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h index f667e976fb2b..50610596a365 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h @@ -8,6 +8,8 @@ #include <linux/types.h> +#include "intel_engine_types.h" + struct intel_gt; #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \ @@ -39,4 +41,25 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl); void gen8_gt_irq_reset(struct intel_gt *gt); void gen8_gt_irq_postinstall(struct intel_gt *gt); +static inline void intel_engine_cs_irq(struct intel_engine_cs *engine, u16 iir) +{ + if (likely(iir)) + engine->irq_handler(engine, iir); +} + +static inline void +intel_engine_set_irq_handler(struct intel_engine_cs *engine, + void (*fn)(struct intel_engine_cs *engine, + u16 iir)) +{ + /* + * As the interrupt is live as allocate and setup the engines, + * err on the side of caution and apply barriers to updating + * the irq handler callback. This assures that when we do use + * the engine, we will receive interrupts only to ourselves, + * and not lose any. + */ + smp_store_mb(engine->irq_handler, fn); +} + #endif /* INTEL_GT_IRQ_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 3cb2ce503544..aa9cfb4dcbca 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -12,6 +12,7 @@ #include "intel_breadcrumbs.h" #include "intel_context.h" #include "intel_gt.h" +#include "intel_gt_irq.h" #include "intel_reset.h" #include "intel_ring.h" #include "shmem_utils.h" @@ -997,10 +998,17 @@ static void ring_release(struct intel_engine_cs *engine) intel_timeline_put(engine->legacy.timeline); } +static void irq_handler(struct intel_engine_cs *engine, u16 iir) +{ + intel_engine_signal_breadcrumbs(engine); +} + static void setup_irq(struct intel_engine_cs *engine) { struct drm_i915_private *i915 = engine->i915; + intel_engine_set_irq_handler(engine, irq_handler); + if (INTEL_GEN(i915) >= 6) { engine->irq_enable = gen6_irq_enable; engine->irq_disable = gen6_irq_disable; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 405d814e9040..4ba6a33f65cf 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1774,7 +1774,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) return; if (pm_iir & PM_VEBOX_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine[VECS0]); + intel_engine_cs_irq(gt->engine[VECS0], pm_iir); if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 17b551a0c89f..335719f17490 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -11,6 +11,7 @@ #include "gt/intel_context.h" #include "gt/intel_engine_pm.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_irq.h" #include "gt/intel_gt_pm.h" #include "gt/intel_lrc.h" #include "gt/intel_mocs.h" @@ -264,6 +265,14 @@ static void guc_submission_tasklet(struct tasklet_struct *t) spin_unlock_irqrestore(&engine->active.lock, flags); } +static void cs_irq_handler(struct intel_engine_cs *engine, u16 iir) +{ + if (iir & GT_RENDER_USER_INTERRUPT) { + intel_engine_signal_breadcrumbs(engine); + tasklet_hi_schedule(&engine->execlists.tasklet); + } +} + static void guc_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; @@ -645,7 +654,6 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine) } engine->set_default_submission = guc_set_default_submission; - engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; engine->flags |= I915_ENGINE_HAS_PREEMPTION; /* @@ -681,6 +689,7 @@ static void rcs_submission_override(struct intel_engine_cs *engine) static inline void guc_default_irqs(struct intel_engine_cs *engine) { engine->irq_keep_mask = GT_RENDER_USER_INTERRUPT; + intel_engine_set_irq_handler(engine, cs_irq_handler); } int intel_guc_submission_setup(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9d47da8ec86d..37a48402adc1 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3954,7 +3954,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); if (iir & I915_MASTER_ERROR_INTERRUPT) i8xx_error_irq_handler(dev_priv, eir, eir_stuck); @@ -4062,7 +4062,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); if (iir & I915_MASTER_ERROR_INTERRUPT) i9xx_error_irq_handler(dev_priv, eir, eir_stuck); @@ -4207,10 +4207,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); if (iir & I915_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]); + intel_engine_cs_irq(dev_priv->gt.engine[VCS0], iir); if (iir & I915_MASTER_ERROR_INTERRUPT) i9xx_error_irq_handler(dev_priv, eir, eir_stuck); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/gt: Move CS interrupt handler to the backend 2021-02-03 6:53 ` [Intel-gfx] [CI 3/3] drm/i915/gt: Move CS interrupt handler to the backend Chris Wilson @ 2021-02-03 8:11 ` Chris Wilson 0 siblings, 0 replies; 7+ messages in thread From: Chris Wilson @ 2021-02-03 8:11 UTC (permalink / raw) To: intel-gfx; +Cc: Chris Wilson The different submission backends each have their own preferred behaviour and interrupt setup. Let each handle their own interrupts. This becomes more useful later as we to extract the use of auxiliary state in the interrupt handler that is backend specific. v2: An overabundance of caution is always justified; put a barrier on updating the irq handler so that we know that the next interrupt will be redirected towards ourselves. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++ drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +--- .../drm/i915/gt/intel_execlists_submission.c | 41 ++++++++++ drivers/gpu/drm/i915/gt/intel_gt_irq.c | 82 ++++++------------- drivers/gpu/drm/i915/gt/intel_gt_irq.h | 23 ++++++ .../gpu/drm/i915/gt/intel_ring_submission.c | 8 ++ drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 ++- drivers/gpu/drm/i915/i915_irq.c | 10 ++- 9 files changed, 124 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index dab8d734e272..13ef5725ef51 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) intel_engine_set_hwsp_writemask(engine, ~0u); } +static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) +{ + GEM_DEBUG_WARN_ON(iir); +} + static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) { const struct engine_info *info = &intel_engines[id]; @@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) engine->hw_id = info->hw_id; engine->guc_id = MAKE_GUC_ID(info->class, info->instance); + engine->irq_handler = nop_irq_handler; + engine->class = info->class; engine->instance = info->instance; __sprint_engine_name(engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 9d59de5c559a..c9974de2dd00 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -402,6 +402,7 @@ struct intel_engine_cs { u32 irq_enable_mask; /* bitmask to enable ring interrupt */ void (*irq_enable)(struct intel_engine_cs *engine); void (*irq_disable)(struct intel_engine_cs *engine); + void (*irq_handler)(struct intel_engine_cs *engine, u16 iir); void (*sanitize)(struct intel_engine_cs *engine); int (*resume)(struct intel_engine_cs *engine); @@ -481,10 +482,9 @@ struct intel_engine_cs { #define I915_ENGINE_HAS_PREEMPTION BIT(2) #define I915_ENGINE_HAS_SEMAPHORES BIT(3) #define I915_ENGINE_HAS_TIMESLICES BIT(4) -#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5) -#define I915_ENGINE_IS_VIRTUAL BIT(6) -#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7) -#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8) +#define I915_ENGINE_IS_VIRTUAL BIT(5) +#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6) +#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7) unsigned int flags; /* @@ -588,12 +588,6 @@ intel_engine_has_timeslices(const struct intel_engine_cs *engine) return engine->flags & I915_ENGINE_HAS_TIMESLICES; } -static inline bool -intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine) -{ - return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; -} - static inline bool intel_engine_is_virtual(const struct intel_engine_cs *engine) { diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 8dc52cc43f27..554eaaa268a7 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -118,6 +118,7 @@ #include "intel_engine_stats.h" #include "intel_execlists_submission.h" #include "intel_gt.h" +#include "intel_gt_irq.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" #include "intel_lrc.h" @@ -2394,6 +2395,45 @@ static void execlists_submission_tasklet(struct tasklet_struct *t) rcu_read_unlock(); } +static void execlists_irq_handler(struct intel_engine_cs *engine, u16 iir) +{ + bool tasklet = false; + + if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) { + u32 eir; + + /* Upper 16b are the enabling mask, rsvd for internal errors */ + eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0); + ENGINE_TRACE(engine, "CS error: %x\n", eir); + + /* Disable the error interrupt until after the reset */ + if (likely(eir)) { + ENGINE_WRITE(engine, RING_EMR, ~0u); + ENGINE_WRITE(engine, RING_EIR, eir); + WRITE_ONCE(engine->execlists.error_interrupt, eir); + tasklet = true; + } + } + + if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) { + WRITE_ONCE(engine->execlists.yield, + ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI)); + ENGINE_TRACE(engine, "semaphore yield: %08x\n", + engine->execlists.yield); + if (del_timer(&engine->execlists.timer)) + tasklet = true; + } + + if (iir & GT_CONTEXT_SWITCH_INTERRUPT) + tasklet = true; + + if (iir & GT_RENDER_USER_INTERRUPT) + intel_engine_signal_breadcrumbs(engine); + + if (tasklet) + tasklet_hi_schedule(&engine->execlists.tasklet); +} + static void __execlists_kick(struct intel_engine_execlists *execlists) { /* Kick the tasklet for some interrupt coalescing and reset handling */ @@ -3126,6 +3166,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) * until a more refined solution exists. */ } + intel_engine_set_irq_handler(engine, execlists_irq_handler); engine->flags |= I915_ENGINE_SUPPORTS_STATS; if (!intel_vgpu_active(engine->i915)) { diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 9fc6c912a4e5..d29126c458ba 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -20,48 +20,6 @@ static void guc_irq_handler(struct intel_guc *guc, u16 iir) intel_guc_to_host_event_handler(guc); } -static void -cs_irq_handler(struct intel_engine_cs *engine, u32 iir) -{ - bool tasklet = false; - - if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) { - u32 eir; - - /* Upper 16b are the enabling mask, rsvd for internal errors */ - eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0); - ENGINE_TRACE(engine, "CS error: %x\n", eir); - - /* Disable the error interrupt until after the reset */ - if (likely(eir)) { - ENGINE_WRITE(engine, RING_EMR, ~0u); - ENGINE_WRITE(engine, RING_EIR, eir); - WRITE_ONCE(engine->execlists.error_interrupt, eir); - tasklet = true; - } - } - - if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) { - WRITE_ONCE(engine->execlists.yield, - ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI)); - ENGINE_TRACE(engine, "semaphore yield: %08x\n", - engine->execlists.yield); - if (del_timer(&engine->execlists.timer)) - tasklet = true; - } - - if (iir & GT_CONTEXT_SWITCH_INTERRUPT) - tasklet = true; - - if (iir & GT_RENDER_USER_INTERRUPT) { - intel_engine_signal_breadcrumbs(engine); - tasklet |= intel_engine_needs_breadcrumb_tasklet(engine); - } - - if (tasklet) - tasklet_hi_schedule(&engine->execlists.tasklet); -} - static u32 gen11_gt_engine_identity(struct intel_gt *gt, const unsigned int bank, const unsigned int bit) @@ -122,7 +80,7 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class, engine = NULL; if (likely(engine)) - return cs_irq_handler(engine, iir); + return intel_engine_cs_irq(engine, iir); WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n", class, instance); @@ -275,9 +233,12 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) { if (gt_iir & GT_RENDER_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); + intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], + gt_iir); + if (gt_iir & ILK_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], + gt_iir); } static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) @@ -301,11 +262,16 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) { if (gt_iir & GT_RENDER_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); + intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], + gt_iir); + if (gt_iir & GT_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], + gt_iir >> 12); + if (gt_iir & GT_BLT_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[COPY_ENGINE_CLASS][0]); + intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], + gt_iir >> 22); if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | GT_BSD_CS_ERROR_INTERRUPT | @@ -324,10 +290,10 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { iir = raw_reg_read(regs, GEN8_GT_IIR(0)); if (likely(iir)) { - cs_irq_handler(gt->engine_class[RENDER_CLASS][0], - iir >> GEN8_RCS_IRQ_SHIFT); - cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0], - iir >> GEN8_BCS_IRQ_SHIFT); + intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], + iir >> GEN8_RCS_IRQ_SHIFT); + intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], + iir >> GEN8_BCS_IRQ_SHIFT); raw_reg_write(regs, GEN8_GT_IIR(0), iir); } } @@ -335,10 +301,10 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) { iir = raw_reg_read(regs, GEN8_GT_IIR(1)); if (likely(iir)) { - cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0], - iir >> GEN8_VCS0_IRQ_SHIFT); - cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1], - iir >> GEN8_VCS1_IRQ_SHIFT); + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], + iir >> GEN8_VCS0_IRQ_SHIFT); + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1], + iir >> GEN8_VCS1_IRQ_SHIFT); raw_reg_write(regs, GEN8_GT_IIR(1), iir); } } @@ -346,8 +312,8 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) if (master_ctl & GEN8_GT_VECS_IRQ) { iir = raw_reg_read(regs, GEN8_GT_IIR(3)); if (likely(iir)) { - cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0], - iir >> GEN8_VECS_IRQ_SHIFT); + intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0], + iir >> GEN8_VECS_IRQ_SHIFT); raw_reg_write(regs, GEN8_GT_IIR(3), iir); } } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h index f667e976fb2b..41cad38668c5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h @@ -8,6 +8,8 @@ #include <linux/types.h> +#include "intel_engine_types.h" + struct intel_gt; #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \ @@ -39,4 +41,25 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl); void gen8_gt_irq_reset(struct intel_gt *gt); void gen8_gt_irq_postinstall(struct intel_gt *gt); +static inline void intel_engine_cs_irq(struct intel_engine_cs *engine, u16 iir) +{ + if (iir) + engine->irq_handler(engine, iir); +} + +static inline void +intel_engine_set_irq_handler(struct intel_engine_cs *engine, + void (*fn)(struct intel_engine_cs *engine, + u16 iir)) +{ + /* + * As the interrupt is live as allocate and setup the engines, + * err on the side of caution and apply barriers to updating + * the irq handler callback. This assures that when we do use + * the engine, we will receive interrupts only to ourselves, + * and not lose any. + */ + smp_store_mb(engine->irq_handler, fn); +} + #endif /* INTEL_GT_IRQ_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 3cb2ce503544..aa9cfb4dcbca 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -12,6 +12,7 @@ #include "intel_breadcrumbs.h" #include "intel_context.h" #include "intel_gt.h" +#include "intel_gt_irq.h" #include "intel_reset.h" #include "intel_ring.h" #include "shmem_utils.h" @@ -997,10 +998,17 @@ static void ring_release(struct intel_engine_cs *engine) intel_timeline_put(engine->legacy.timeline); } +static void irq_handler(struct intel_engine_cs *engine, u16 iir) +{ + intel_engine_signal_breadcrumbs(engine); +} + static void setup_irq(struct intel_engine_cs *engine) { struct drm_i915_private *i915 = engine->i915; + intel_engine_set_irq_handler(engine, irq_handler); + if (INTEL_GEN(i915) >= 6) { engine->irq_enable = gen6_irq_enable; engine->irq_disable = gen6_irq_disable; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 405d814e9040..97cab1b99871 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1774,7 +1774,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) return; if (pm_iir & PM_VEBOX_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine[VECS0]); + intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10); if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 17b551a0c89f..335719f17490 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -11,6 +11,7 @@ #include "gt/intel_context.h" #include "gt/intel_engine_pm.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_irq.h" #include "gt/intel_gt_pm.h" #include "gt/intel_lrc.h" #include "gt/intel_mocs.h" @@ -264,6 +265,14 @@ static void guc_submission_tasklet(struct tasklet_struct *t) spin_unlock_irqrestore(&engine->active.lock, flags); } +static void cs_irq_handler(struct intel_engine_cs *engine, u16 iir) +{ + if (iir & GT_RENDER_USER_INTERRUPT) { + intel_engine_signal_breadcrumbs(engine); + tasklet_hi_schedule(&engine->execlists.tasklet); + } +} + static void guc_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; @@ -645,7 +654,6 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine) } engine->set_default_submission = guc_set_default_submission; - engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; engine->flags |= I915_ENGINE_HAS_PREEMPTION; /* @@ -681,6 +689,7 @@ static void rcs_submission_override(struct intel_engine_cs *engine) static inline void guc_default_irqs(struct intel_engine_cs *engine) { engine->irq_keep_mask = GT_RENDER_USER_INTERRUPT; + intel_engine_set_irq_handler(engine, cs_irq_handler); } int intel_guc_submission_setup(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9d47da8ec86d..0ff3f64c4bb5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3954,7 +3954,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); if (iir & I915_MASTER_ERROR_INTERRUPT) i8xx_error_irq_handler(dev_priv, eir, eir_stuck); @@ -4062,7 +4062,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); if (iir & I915_MASTER_ERROR_INTERRUPT) i9xx_error_irq_handler(dev_priv, eir, eir_stuck); @@ -4207,10 +4207,12 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + intel_engine_cs_irq(dev_priv->gt.engine[RCS0], + iir); if (iir & I915_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]); + intel_engine_cs_irq(dev_priv->gt.engine[VCS0], + iir >> 25); if (iir & I915_MASTER_ERROR_INTERRUPT) i9xx_error_irq_handler(dev_priv, eir, eir_stuck); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission 2021-02-03 6:53 [Intel-gfx] [CI 1/3] drm/i915/gt: Move engine setup out of set_default_submission Chris Wilson 2021-02-03 6:53 ` [Intel-gfx] [CI 2/3] drm/i915/gt: Move submission_method into intel_gt Chris Wilson 2021-02-03 6:53 ` [Intel-gfx] [CI 3/3] drm/i915/gt: Move CS interrupt handler to the backend Chris Wilson @ 2021-02-03 8:04 ` Patchwork 2021-02-03 9:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission (rev2) Patchwork 2021-02-03 11:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2021-02-03 8:04 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 5851 bytes --] == Series Details == Series: series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission URL : https://patchwork.freedesktop.org/series/86603/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9720 -> Patchwork_19567 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_19567 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19567, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_19567: ### IGT changes ### #### Possible regressions #### * igt@gem_exec_parallel@engines@contexts: - fi-byt-j1900: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9720/fi-byt-j1900/igt@gem_exec_parallel@engines@contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/fi-byt-j1900/igt@gem_exec_parallel@engines@contexts.html - fi-ivb-3770: [PASS][3] -> [FAIL][4] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9720/fi-ivb-3770/igt@gem_exec_parallel@engines@contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/fi-ivb-3770/igt@gem_exec_parallel@engines@contexts.html Known issues ------------ Here are the changes found in Patchwork_19567 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@coherency: - fi-hsw-4770: [PASS][5] -> [INCOMPLETE][6] ([i915#1729]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9720/fi-hsw-4770/igt@i915_selftest@live@coherency.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/fi-hsw-4770/igt@i915_selftest@live@coherency.html - fi-ivb-3770: [PASS][7] -> [INCOMPLETE][8] ([i915#1729]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9720/fi-ivb-3770/igt@i915_selftest@live@coherency.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/fi-ivb-3770/igt@i915_selftest@live@coherency.html * igt@i915_selftest@live@hangcheck: - fi-icl-y: [PASS][9] -> [INCOMPLETE][10] ([i915#2782] / [i915#926]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9720/fi-icl-y/igt@i915_selftest@live@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/fi-icl-y/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-n3050: [PASS][11] -> [DMESG-FAIL][12] ([i915#2927]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9720/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9720/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html * igt@runner@aborted: - fi-icl-y: NOTRUN -> [FAIL][15] ([i915#2295] / [i915#2724]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/fi-icl-y/igt@runner@aborted.html - fi-bsw-n3050: NOTRUN -> [FAIL][16] ([i915#1436]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/fi-bsw-n3050/igt@runner@aborted.html #### Possible fixes #### * igt@prime_vgem@basic-gtt: - fi-tgl-y: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9720/fi-tgl-y/igt@prime_vgem@basic-gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/fi-tgl-y/igt@prime_vgem@basic-gtt.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1729]: https://gitlab.freedesktop.org/drm/intel/issues/1729 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#926]: https://gitlab.freedesktop.org/drm/intel/issues/926 [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379 Participating hosts (42 -> 39) ------------------------------ Missing (3): fi-jsl-1 fi-bsw-cyan fi-bdw-samus Build changes ------------- * Linux: CI_DRM_9720 -> Patchwork_19567 CI-20190529: 20190529 CI_DRM_9720: 23c0f4460024782c5043dabab4b2966831e4c887 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5988: 4581082c706498cc3afe20e89fc4836a3fc69105 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19567: 56f65e0f085863cd80136de398314be08c37fdc5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 56f65e0f0858 drm/i915/gt: Move CS interrupt handler to the backend e6dae7cfb111 drm/i915/gt: Move submission_method into intel_gt 28ff2ac4ae49 drm/i915/gt: Move engine setup out of set_default_submission == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19567/index.html [-- Attachment #1.2: Type: text/html, Size: 6712 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission (rev2) 2021-02-03 6:53 [Intel-gfx] [CI 1/3] drm/i915/gt: Move engine setup out of set_default_submission Chris Wilson ` (2 preceding siblings ...) 2021-02-03 8:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission Patchwork @ 2021-02-03 9:40 ` Patchwork 2021-02-03 11:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2021-02-03 9:40 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3511 bytes --] == Series Details == Series: series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission (rev2) URL : https://patchwork.freedesktop.org/series/86603/ State : success == Summary == CI Bug Log - changes from CI_DRM_9721 -> Patchwork_19568 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/index.html Known issues ------------ Here are the changes found in Patchwork_19568 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#142] / [i915#2405]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html * igt@prime_vgem@basic-userptr: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/fi-tgl-y/igt@prime_vgem@basic-userptr.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/fi-tgl-y/igt@prime_vgem@basic-userptr.html * igt@runner@aborted: - fi-byt-j1900: NOTRUN -> [FAIL][5] ([i915#1814] / [i915#2505]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/fi-byt-j1900/igt@runner@aborted.html #### Possible fixes #### * igt@gem_mmap_gtt@basic: - fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7] +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/fi-tgl-y/igt@gem_mmap_gtt@basic.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/fi-tgl-y/igt@gem_mmap_gtt@basic.html #### Warnings #### * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][8] ([i915#579]) -> [SKIP][9] ([fdo#109271]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405 [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 Participating hosts (42 -> 39) ------------------------------ Missing (3): fi-jsl-1 fi-bsw-cyan fi-bdw-samus Build changes ------------- * Linux: CI_DRM_9721 -> Patchwork_19568 CI-20190529: 20190529 CI_DRM_9721: 2bd88ea627421f4c9179740592f21c2789e1afda @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5988: 4581082c706498cc3afe20e89fc4836a3fc69105 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19568: c9c271b4630aa3a04aa4e1e9fb42ce499dac1612 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c9c271b4630a drm/i915/gt: Move CS interrupt handler to the backend 2857d50bc7e3 drm/i915/gt: Move submission_method into intel_gt 1a1e64e24b3b drm/i915/gt: Move engine setup out of set_default_submission == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/index.html [-- Attachment #1.2: Type: text/html, Size: 4293 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission (rev2) 2021-02-03 6:53 [Intel-gfx] [CI 1/3] drm/i915/gt: Move engine setup out of set_default_submission Chris Wilson ` (3 preceding siblings ...) 2021-02-03 9:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission (rev2) Patchwork @ 2021-02-03 11:20 ` Patchwork 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2021-02-03 11:20 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30320 bytes --] == Series Details == Series: series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission (rev2) URL : https://patchwork.freedesktop.org/series/86603/ State : success == Summary == CI Bug Log - changes from CI_DRM_9721_full -> Patchwork_19568_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_19568_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_balancer@hang: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([i915#1895] / [i915#2295] / [i915#3031]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb5/igt@gem_exec_balancer@hang.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb4/igt@gem_exec_balancer@hang.html * igt@gem_exec_capture@pi@vcs0: - shard-skl: NOTRUN -> [INCOMPLETE][3] ([i915#2295]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl3/igt@gem_exec_capture@pi@vcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-apl: [PASS][4] -> [SKIP][5] ([fdo#109271]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl8/igt@gem_exec_fair@basic-none-share@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl2/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb3/igt@gem_exec_fair@basic-pace@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb6/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_schedule@u-fairslice@vcs0: - shard-skl: NOTRUN -> [DMESG-WARN][11] ([i915#1610] / [i915#2803]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl10/igt@gem_exec_schedule@u-fairslice@vcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl7/igt@gem_huc_copy@huc-copy.html - shard-kbl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2190]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl7/igt@gem_huc_copy@huc-copy.html * igt@gem_partial_pwrite_pread@reads-uncached: - shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#118] / [i915#95]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-glk7/igt@gem_partial_pwrite_pread@reads-uncached.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-glk8/igt@gem_partial_pwrite_pread@reads-uncached.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2692]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-tglb6/igt@i915_pm_rc6_residency@rc6-idle.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-tglb2/igt@i915_pm_rc6_residency@rc6-idle.html - shard-iclb: [PASS][18] -> [WARN][19] ([i915#1804] / [i915#2684]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][20] -> [FAIL][21] ([i915#2597]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-tglb6/igt@kms_async_flips@test-time-stamp.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-tglb1/igt@kms_async_flips@test-time-stamp.html * igt@kms_big_joiner@basic: - shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#2705]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl3/igt@kms_big_joiner@basic.html * igt@kms_chamelium@vga-hpd-for-each-pipe: - shard-skl: NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl2/igt@kms_chamelium@vga-hpd-for-each-pipe.html * igt@kms_color@pipe-d-ctm-0-25: - shard-hsw: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#533]) +5 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-hsw4/igt@kms_color@pipe-d-ctm-0-25.html * igt@kms_color@pipe-d-ctm-max: - shard-skl: NOTRUN -> [SKIP][25] ([fdo#109271]) +52 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl9/igt@kms_color@pipe-d-ctm-max.html * igt@kms_color_chamelium@pipe-a-ctm-green-to-red: - shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +5 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl4/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-a-degamma: - shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +9 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl2/igt@kms_color_chamelium@pipe-a-degamma.html * igt@kms_color_chamelium@pipe-b-ctm-negative: - shard-hsw: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-hsw4/igt@kms_color_chamelium@pipe-b-ctm-negative.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#54]) +4 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen: - shard-skl: NOTRUN -> [FAIL][31] ([i915#54]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-kbl: [PASS][32] -> [INCOMPLETE][33] ([i915#155] / [i915#180] / [i915#636]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-tglb: [PASS][34] -> [FAIL][35] ([i915#2598]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1: - shard-apl: [PASS][36] -> [DMESG-WARN][37] ([i915#180]) +1 similar issue [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html * igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1: - shard-hsw: [PASS][38] -> [INCOMPLETE][39] ([i915#2295]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw8/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-hsw4/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1: - shard-skl: [PASS][40] -> [FAIL][41] ([i915#2122]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile: - shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#2642]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html - shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#2642]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc: - shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271]) +67 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu: - shard-hsw: NOTRUN -> [SKIP][45] ([fdo#109271]) +24 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-hsw4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt: - shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271]) +22 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: NOTRUN -> [FAIL][47] ([i915#1188]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_hdr@static-toggle-dpms: - shard-iclb: NOTRUN -> [SKIP][48] ([i915#1187]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb8/igt@kms_hdr@static-toggle-dpms.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#533]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][50] -> [DMESG-WARN][51] ([i915#180]) +2 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-skl: NOTRUN -> [FAIL][52] ([fdo#108145] / [i915#265]) +1 similar issue [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html - shard-kbl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-apl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl4/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1: - shard-kbl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#658]) +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html * igt@kms_psr2_su@page_flip: - shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658]) +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl7/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][57] -> [SKIP][58] ([fdo#109441]) +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][59] -> [DMESG-WARN][60] ([i915#180] / [i915#295]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@perf@blocking: - shard-skl: [PASS][61] -> [FAIL][62] ([i915#1542]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl2/igt@perf@blocking.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl8/igt@perf@blocking.html #### Possible fixes #### * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [FAIL][63] ([i915#2842]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-glk: [FAIL][65] ([i915#2842]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-glk8/igt@gem_exec_fair@basic-pace@rcs0.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-glk3/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-apl: [FAIL][67] ([i915#2389]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl3/igt@gem_exec_reloc@basic-many-active@rcs0.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl4/igt@gem_exec_reloc@basic-many-active@rcs0.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-iclb: [DMESG-WARN][69] ([i915#2803]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb2/igt@gem_exec_schedule@u-fairslice@rcs0.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb8/igt@gem_exec_schedule@u-fairslice@rcs0.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-hsw: [FAIL][71] ([i915#1860]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw1/igt@i915_pm_rc6_residency@rc6-idle.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-hsw7/igt@i915_pm_rc6_residency@rc6-idle.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: [DMESG-WARN][73] ([i915#180]) -> [PASS][74] +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl1/igt@i915_suspend@fence-restore-untiled.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl4/igt@i915_suspend@fence-restore-untiled.html * igt@kms_color@pipe-a-ctm-max: - shard-hsw: [DMESG-WARN][75] ([i915#44]) -> [PASS][76] +1 similar issue [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw5/igt@kms_color@pipe-a-ctm-max.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-hsw6/igt@kms_color@pipe-a-ctm-max.html * igt@kms_color@pipe-a-legacy-gamma: - shard-hsw: [DMESG-FAIL][77] ([i915#44]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw5/igt@kms_color@pipe-a-legacy-gamma.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-hsw6/igt@kms_color@pipe-a-legacy-gamma.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-skl: [FAIL][79] ([i915#54]) -> [PASS][80] +6 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][81] ([i915#180]) -> [PASS][82] +2 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html - shard-skl: [INCOMPLETE][83] ([i915#2295] / [i915#300]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen: - shard-hsw: [FAIL][85] -> [PASS][86] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw5/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-hsw6/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [FAIL][87] ([i915#96]) -> [PASS][88] [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic: - shard-skl: [FAIL][89] ([i915#2346]) -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [FAIL][91] ([i915#79]) -> [PASS][92] [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][93] ([i915#1188]) -> [PASS][94] +1 similar issue [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][95] ([fdo#108145] / [i915#265]) -> [PASS][96] +1 similar issue [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_suspend: - shard-iclb: [SKIP][97] ([fdo#109441]) -> [PASS][98] +2 similar issues [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb7/igt@kms_psr@psr2_suspend.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb2/igt@kms_psr@psr2_suspend.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: [INCOMPLETE][99] ([i915#198]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl3/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * {igt@sysfs_clients@recycle}: - shard-hsw: [FAIL][101] ([i915#3028]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw6/igt@sysfs_clients@recycle.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-hsw8/igt@sysfs_clients@recycle.html - shard-apl: [FAIL][103] ([i915#3028]) -> [PASS][104] [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl1/igt@sysfs_clients@recycle.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-apl1/igt@sysfs_clients@recycle.html * {igt@sysfs_clients@recycle-many}: - shard-iclb: [FAIL][105] -> [PASS][106] [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb3/igt@sysfs_clients@recycle-many.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb6/igt@sysfs_clients@recycle-many.html - shard-glk: [FAIL][107] -> [PASS][108] [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-glk8/igt@sysfs_clients@recycle-many.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-glk4/igt@sysfs_clients@recycle-many.html - shard-tglb: [FAIL][109] -> [PASS][110] [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-tglb2/igt@sysfs_clients@recycle-many.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-tglb5/igt@sysfs_clients@recycle-many.html #### Warnings #### * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][111] ([i915#1804] / [i915#2684]) -> [WARN][112] ([i915#2684]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-0: - shard-iclb: [SKIP][113] ([i915#658]) -> [SKIP][114] ([i915#2920]) +1 similar issue [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb7/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-3: - shard-iclb: [SKIP][115] ([i915#2920]) -> [SKIP][116] ([i915#658]) +1 similar issue [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb4/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html * igt@runner@aborted: - shard-kbl: ([FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128]) ([i915#1436] / [i915#1814] / [i915#2295] / [i915#3002] / [i915#602]) -> ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141]) ([i915#1436] / [i915#1814] / [i915#2292] / [i915#2295] / [i915#2505] / [i915#3002] / [i915#602] / [i915#92]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@runner@aborted.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@runner@aborted.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl4/igt@runner@aborted.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@runner@aborted.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl4/igt@runner@aborted.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@runner@aborted.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl7/igt@runner@aborted.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@runner@aborted.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@runner@aborted.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@runner@aborted.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl4/igt@runner@aborted.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@runner@aborted.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl1/igt@runner@aborted.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl1/igt@runner@aborted.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl4/igt@runner@aborted.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl1/igt@runner@aborted.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl2/igt@runner@aborted.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl2/igt@runner@aborted.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl2/igt@runner@aborted.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl4/igt@runner@aborted.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl6/igt@runner@aborted.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl1/igt@runner@aborted.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl1/igt@runner@aborted.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl2/igt@runner@aborted.html [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-kbl4/igt@runner@aborted.html - shard-iclb: ([FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145]) ([i915#2295] / [i915#2426] / [i915#2724] / [i915#3002]) -> ([FAIL][146], [FAIL][147], [FAIL][148]) ([i915#2295] / [i915#2724] / [i915#3002]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb7/igt@runner@aborted.html [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb5/igt@runner@aborted.html [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb2/igt@runner@aborted.html [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb1/igt@runner@aborted.html [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb7/igt@runner@aborted.html [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb7/igt@runner@aborted.html [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-iclb2/igt@runner@aborted.html - shard-snb: ([FAIL][149], [FAIL][150]) ([i915#3002] / [i915#698]) -> ([FAIL][151], [FAIL][152], [FAIL][153]) ([i915#2426] / [i915#3002] / [i915#698]) [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-snb5/igt@runner@aborted.html [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-snb2/igt@runner@aborted.html [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-snb5/igt@runner@aborted.html [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-snb7/igt@runner@aborted.html [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-snb4/igt@runner@aborted.html - shard-skl: ([FAIL][154], [FAIL][155], [FAIL][156]) ([i915#2295] / [i915#3002]) -> ([FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160]) ([i915#2295] / [i915#2426] / [i915#3002]) [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl1/igt@runner@aborted.html [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl7/igt@runner@aborted.html [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl8/igt@runner@aborted.html [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl6/igt@runner@aborted.html [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl8/igt@runner@aborted.html [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl10/igt@runner@aborted.html [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/shard-skl3/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1187]: https://gitlab.freedesktop.org/drm/intel/issues/1187 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#1860]: https://gitlab.freedesktop.org/drm/intel/issues/1860 [i915#1895]: https://gitlab.freedesktop.org/drm/intel/issues/1895 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2389]: https://gitlab.freedesktop.org/drm/inte == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19568/index.html [-- Attachment #1.2: Type: text/html, Size: 35947 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-02-03 11:20 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-02-03 6:53 [Intel-gfx] [CI 1/3] drm/i915/gt: Move engine setup out of set_default_submission Chris Wilson 2021-02-03 6:53 ` [Intel-gfx] [CI 2/3] drm/i915/gt: Move submission_method into intel_gt Chris Wilson 2021-02-03 6:53 ` [Intel-gfx] [CI 3/3] drm/i915/gt: Move CS interrupt handler to the backend Chris Wilson 2021-02-03 8:11 ` [Intel-gfx] [PATCH] " Chris Wilson 2021-02-03 8:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission Patchwork 2021-02-03 9:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/gt: Move engine setup out of set_default_submission (rev2) Patchwork 2021-02-03 11:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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