From mboxrd@z Thu Jan 1 00:00:00 1970 From: Patrick Delaunay Date: Fri, 5 Feb 2021 13:53:33 +0100 Subject: [PATCH 2/8] stm32mp: update the mmu configuration for SPL and prereloc In-Reply-To: <20210205125339.24721-1-patrick.delaunay@foss.st.com> References: <20210205125339.24721-1-patrick.delaunay@foss.st.com> Message-ID: <20210205135332.2.I89418f0518a81f98643b36c248b006e596950c25@changeid> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Overidde the weak function dram_bank_mmu_setup() to set the DDR (preloc case) or the SYSRAM (in SPL case) executable before to enable the MMU and configure DACR. This weak function is called in dcache_enable/mmu_setup. This patchs avoids a permission access issue when the DDR is marked executable (by calling mmu_set_region_dcache_behaviour with DCACHE_DEFAULT_OPTION) after MMU setup and domain access permission activation with DACR in dcache_enable. Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/cpu.c | 40 +++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 717f80e9ff..030066dc7c 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -210,6 +210,35 @@ u32 get_bootmode(void) TAMP_BOOT_MODE_SHIFT; } +/* + * weak function overidde: set the DDR/SYSRAM executable before to enable the + * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc) + */ +void dram_bank_mmu_setup(int bank) +{ + struct bd_info *bd = gd->bd; + int i; + phys_addr_t start; + phys_size_t size; + + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); + size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); + } else if (gd->flags & GD_FLG_RELOC) { + /* bd->bi_dram is available only after relocation */ + start = bd->bi_dram[bank].start; + size = bd->bi_dram[bank].size; + } else { + /* mark cacheable and executable the beggining of the DDR */ + start = STM32_DDR_BASE; + size = CONFIG_DDR_CACHEABLE_SIZE; + } + + for (i = start >> MMU_SECTION_SHIFT; + i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); +} /* * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage * MMU/TLB is updated in enable_caches() for U-Boot after relocation @@ -225,17 +254,8 @@ static void early_enable_caches(void) gd->arch.tlb_size = PGTABLE_SIZE; gd->arch.tlb_addr = (unsigned long)&early_tlb; + /* enable MMU (default configuration) */ dcache_enable(); - - if (IS_ENABLED(CONFIG_SPL_BUILD)) - mmu_set_region_dcache_behaviour( - ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), - ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), - DCACHE_DEFAULT_OPTION); - else - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, - CONFIG_DDR_CACHEABLE_SIZE, - DCACHE_DEFAULT_OPTION); } /* -- 2.17.1