From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C944C433E0 for ; Mon, 8 Feb 2021 22:51:29 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5BA764DA1 for ; Mon, 8 Feb 2021 22:51:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D5BA764DA1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=VHANomjTgL8mCi4ggBMgbolOirweHrUZxHfRjPPWSQs=; b=HTEW7Cqzhe59PPu8mMzmo3JMIt HTdE8Hh0nO/zNvu3Iq0u3UPGCcobzeFdR5dKygtCwnp89wu4ZtKyz3mWqm/Ov1nuXgPob08ODSeNn bYpdG0YjPH+g/PXyaJpXfRmSQA9VJ8OvvHx0qfCdowHe3OSxlNi8u3P3pN3+lEZQmg1I9l+zKL++d VaH3RybbOMtznqBZz+YhtoGK9a4jfsEoeLuiFHeWm/WCZIQBrP0P8w2xfwhgJ4XuxvEB7ZqR7jJSJ yqI57fTN/u9z3V4crj8froSKbwnL/LpP1+TginriTCzGyTsrJTlPU85OypS2OlQFSsJk1Q11501ea t74iarZQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9FMD-00079u-EA; Mon, 08 Feb 2021 22:50:13 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9FMB-00079V-54 for linux-arm-kernel@lists.infradead.org; Mon, 08 Feb 2021 22:50:11 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7D75B64D99; Mon, 8 Feb 2021 22:50:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612824610; bh=8cCPdMEcXYsZ9vvq5qoNjiPAyZ9UgnzJXfAUh/uGVnU=; h=From:To:Cc:Subject:Date:From; b=AuMbr75HxZ8QSkoOQGJBh0wqhAEgw3UOjp7xRy6gNSjSkkDCkZmxBAiHe78jrR89M SQ/uR+4M7LToUcFN9BperCOXUF1JCHtgxTHwHojh2YwIqPrHaJUYOmxFo9Dy/iWMUz 36SG4w3iHlrd+sL3H7IkIKxhW6XUk/ExnfXzdUDL5UVtVRBMYsIAxkOXAtUPtqwcVv DYf+0MniOt34c/oqv/zddaHwRvAMc7oGFOxdWkRUNNBpEqeEo2ljeqgqd5m1M1d57C bobsZDc2azEndH3xuWtG18uF/dbRXAiTXAGizq9i+PzptenE3aW0tWBRu+U2dMaenO oXlFcTV5jaLKg== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/3] ARM: v7: get rid of boot time mini stack Date: Mon, 8 Feb 2021 23:49:56 +0100 Message-Id: <20210208224959.13683-1-ardb@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210208_175011_310330_59BB6CD8 X-CRM114-Status: GOOD ( 13.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicolas Pitre , Marc Zyngier , Linus Walleij , Russell King , kernel-team@android.com, Ard Biesheuvel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The v7 boot code uses a small chunk of BSS to preserve some register contents across a call to v7_invalidate_l1 that occurs with the MMU and caches disabled. Memory accesses in such cases are tricky on v7+, given that the architecture permits some unintuitive behaviors (it is implementation defined whether accesses done with the MMU and caches off may hit in the caches, and on SoCs that incorporate off-core system caches, this behavior appears to be different even between cache levels). Also, cache invalidation is not safe under virtualization if the intent is to retain stores issued directly to DRAM, given that the hypervisor may upgrade invalidate operations to clean+invalidate, resulting in DRAM contents to be overwritte by the dirty cachelines that we were trying to evict in the first place. So let's address this issue, by removing the need for this stack to exist in the first place: v7_invalidate_l1 can be rewritten to use fewer registers, which means fewer registers need to be preserved, and we have enough spare registers available. Patch #1 adds a missing ISB. This patch is included separately so it can be backported if desired. Patch #2 rewrites v7_invalidate_l1 so it only uses 5 registers (not counting lr which it must preserve as well) Patch #3 updates the callers to use spare registers instead of the mini stack to stash the values that need to be preserved across the calls to v7_invalidate_l1. Cc: Marc Zyngier Cc: Russell King Cc: Linus Walleij Cc: Nicolas Pitre Ard Biesheuvel (3): ARM: cache-v7: add missing ISB after cache level selection ARM: cache-v7: refactor v7_invalidate_l1 to avoid clobbering r5/r6 ARM: cache-v7: get rid of mini-stack arch/arm/include/asm/memory.h | 15 ----- arch/arm/mm/cache-v7.S | 58 ++++++++++---------- arch/arm/mm/proc-v7.S | 40 ++++++-------- 3 files changed, 47 insertions(+), 66 deletions(-) -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel