From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andre Przywara <andre.przywara@arm.com>
Date: Tue, 9 Feb 2021 01:33:24 +0000
Subject: [PATCH 2/6] clk: sunxi: h6: Add XHCI clocks
In-Reply-To: <20210208055724.58673-3-samuel@sholland.org>
References: <20210208055724.58673-1-samuel@sholland.org>
 <20210208055724.58673-3-samuel@sholland.org>
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On Sun,  7 Feb 2021 23:57:20 -0600
Samuel Holland <samuel@sholland.org> wrote:

> The XHCI controller has its own clock and reset. Add them.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Checked against the manual:
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>  drivers/clk/sunxi/clk_h6.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
> index ac8656fe895..df93d96b3b0 100644
> --- a/drivers/clk/sunxi/clk_h6.c
> +++ b/drivers/clk/sunxi/clk_h6.c
> @@ -43,6 +43,7 @@ static struct ccu_clk_gate h6_gates[] = {
>  	[CLK_BUS_OHCI0]		= GATE(0xa8c, BIT(0)),
>  	[CLK_BUS_OHCI3]		= GATE(0xa8c, BIT(3)),
>  	[CLK_BUS_EHCI0]		= GATE(0xa8c, BIT(4)),
> +	[CLK_BUS_XHCI]		= GATE(0xa8c, BIT(5)),
>  	[CLK_BUS_EHCI3]		= GATE(0xa8c, BIT(7)),
>  	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
>  };
> @@ -71,6 +72,7 @@ static struct ccu_reset h6_resets[] = {
>  	[RST_BUS_OHCI0]		= RESET(0xa8c, BIT(16)),
>  	[RST_BUS_OHCI3]		= RESET(0xa8c, BIT(19)),
>  	[RST_BUS_EHCI0]		= RESET(0xa8c, BIT(20)),
> +	[RST_BUS_XHCI]		= RESET(0xa8c, BIT(21)),
>  	[RST_BUS_EHCI3]		= RESET(0xa8c, BIT(23)),
>  	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
>  };