[PATCH 11/25] arm: Remove apf27 board

[Tom Rini <trini@konsulko.com>]

This board has not been converted to CONFIG_DM_MMC by the deadline of
v2019.04, which is almost two years ago.  In addition there are other DM
migrations it is also missing.  Remove it.

Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/arm/Kconfig                     |   6 -
 board/armadeus/apf27/Kconfig         |  15 -
 board/armadeus/apf27/MAINTAINERS     |   7 -
 board/armadeus/apf27/Makefile        |  12 -
 board/armadeus/apf27/apf27.c         | 258 --------------
 board/armadeus/apf27/apf27.h         | 488 ---------------------------
 board/armadeus/apf27/fpga.c          | 226 -------------
 board/armadeus/apf27/fpga.h          |  24 --
 board/armadeus/apf27/lowlevel_init.S | 166 ---------
 configs/apf27_defconfig              |  59 ----
 drivers/serial/Kconfig               |   2 +-
 include/configs/apf27.h              | 266 ---------------
 12 files changed, 1 insertion(+), 1528 deletions(-)
 delete mode 100644 board/armadeus/apf27/Kconfig
 delete mode 100644 board/armadeus/apf27/MAINTAINERS
 delete mode 100644 board/armadeus/apf27/Makefile
 delete mode 100644 board/armadeus/apf27/apf27.c
 delete mode 100644 board/armadeus/apf27/apf27.h
 delete mode 100644 board/armadeus/apf27/fpga.c
 delete mode 100644 board/armadeus/apf27/fpga.h
 delete mode 100644 board/armadeus/apf27/lowlevel_init.S
 delete mode 100644 configs/apf27_defconfig
 delete mode 100644 include/configs/apf27.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9969da161e9c..acffdc6a1ed8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,11 +561,6 @@ config ARCH_MVEBU
 	select SPI
 	imply CMD_DM
 
-config TARGET_APF27
-	bool "Support apf27"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-
 config ARCH_ORION5X
 	bool "Marvell Orion"
 	select CPU_ARM926EJS
@@ -1969,7 +1964,6 @@ source "board/Marvell/aspenite/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
 source "board/Marvell/octeontx/Kconfig"
 source "board/Marvell/octeontx2/Kconfig"
-source "board/armadeus/apf27/Kconfig"
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/cortina/presidio-asic/Kconfig"
diff --git a/board/armadeus/apf27/Kconfig b/board/armadeus/apf27/Kconfig
deleted file mode 100644
index 65544a844834..000000000000
--- a/board/armadeus/apf27/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_APF27
-
-config SYS_BOARD
-	default "apf27"
-
-config SYS_VENDOR
-	default "armadeus"
-
-config SYS_SOC
-	default "mx27"
-
-config SYS_CONFIG_NAME
-	default "apf27"
-
-endif
diff --git a/board/armadeus/apf27/MAINTAINERS b/board/armadeus/apf27/MAINTAINERS
deleted file mode 100644
index 09f0525c51b9..000000000000
--- a/board/armadeus/apf27/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-APF27 BOARD
-M:	Philippe Reynes <tremyfr@yahoo.fr>
-M:	Eric Jarrige <eric.jarrige@armadeus.org>
-S:	Maintained
-F:	board/armadeus/apf27/
-F:	include/configs/apf27.h
-F:	configs/apf27_defconfig
diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
deleted file mode 100644
index 57129718d5c5..000000000000
--- a/board/armadeus/apf27/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-# (C) Copyright 2012-2013
-# Eric Jarrige <eric.jarrige@armadeus.org>
-#
-# SPDX-License-Identifier:    GPL-2.0+
-#
-
-obj-y	:= apf27.o
-obj-y	+= lowlevel_init.o
-obj-$(CONFIG_FPGA)	+= fpga.o
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
deleted file mode 100644
index 29e0bf388d07..000000000000
--- a/board/armadeus/apf27/apf27.c
+++ /dev/null
@@ -1,258 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
- *
- * based on the files by
- * Sascha Hauer, Pengutronix
- */
-
-#include <common.h>
-#include <hang.h>
-#include <init.h>
-#include <jffs2/jffs2.h>
-#include <nand.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/gpio.h>
-#include <asm/gpio.h>
-#include <linux/errno.h>
-#include <u-boot/crc.h>
-#include "apf27.h"
-#include "fpga.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Fuse bank 1 row 8 is "reserved for future use" and therefore available for
- * customer use. The APF27 board uses this fuse to store the board revision:
- * 0: initial board revision
- * 1: first revision - Presence of the second RAM chip on the board is blown in
- *     fuse bank 1 row 9  bit 0 - No hardware change
- * N: to be defined
- */
-static u32 get_board_rev(void)
-{
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-
-	return readl(&iim->bank[1].fuse_regs[8]);
-}
-
-/*
- * Fuse bank 1 row 9 is "reserved for future use" and therefore available for
- * customer use. The APF27 board revision 1 uses the bit 0 to permanently store
- * the presence of the second RAM chip
- * 0: AFP27 with 1 RAM of 64 MiB
- * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
- */
-static int get_num_ram_bank(void)
-{
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	int nr_dram_banks = 1;
-
-	if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
-		nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
-	else
-		nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
-
-	return nr_dram_banks;
-}
-
-static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2,
-			    u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2,
-			    u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr,
-			    u32 puen, u32 gius)
-{
-	struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
-
-	writel(gpio_dr,   &regs->port[port].gpio_dr);
-	writel(ocr1,      &regs->port[port].ocr1);
-	writel(ocr2,      &regs->port[port].ocr2);
-	writel(iconfa1,   &regs->port[port].iconfa1);
-	writel(iconfa2,   &regs->port[port].iconfa2);
-	writel(iconfb1,   &regs->port[port].iconfb1);
-	writel(iconfb2,   &regs->port[port].iconfb2);
-	writel(icr1,      &regs->port[port].icr1);
-	writel(icr2,      &regs->port[port].icr2);
-	writel(imr,       &regs->port[port].imr);
-	writel(gpio_dir,  &regs->port[port].gpio_dir);
-	writel(gpr,       &regs->port[port].gpr);
-	writel(puen,      &regs->port[port].puen);
-	writel(gius,      &regs->port[port].gius);
-}
-
-#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL,	  \
-	ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL,	  \
-	ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \
-	ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL,	  \
-	ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL,	  \
-	ACFG_GIUS_##n##_VAL)
-
-static void apf27_iomux_init(void)
-{
-	APF27_PORT_INIT(A);
-	APF27_PORT_INIT(B);
-	APF27_PORT_INIT(C);
-	APF27_PORT_INIT(D);
-	APF27_PORT_INIT(E);
-	APF27_PORT_INIT(F);
-}
-
-static int apf27_devices_init(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PC5_PF_I2C2_DATA,
-		PC6_PF_I2C2_CLK,
-		PD17_PF_I2C_DATA,
-		PD18_PF_I2C_CLK,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-#ifdef CONFIG_MXC_UART
-	mx27_uart1_init_pins();
-#endif
-
-#ifdef CONFIG_FEC_MXC
-	mx27_fec_init_pins();
-#endif
-
-#ifdef CONFIG_MMC_MXC
-	mx27_sd2_init_pins();
-	imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
-	gpio_request(PC_PWRON, "pc_pwron");
-	gpio_set_value(PC_PWRON, 1);
-#endif
-	return 0;
-}
-
-static void apf27_setup_csx(void)
-{
-	struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE;
-
-	writel(ACFG_CS0U_VAL, &weim->cs0u);
-	writel(ACFG_CS0L_VAL, &weim->cs0l);
-	writel(ACFG_CS0A_VAL, &weim->cs0a);
-
-	writel(ACFG_CS1U_VAL, &weim->cs1u);
-	writel(ACFG_CS1L_VAL, &weim->cs1l);
-	writel(ACFG_CS1A_VAL, &weim->cs1a);
-
-	writel(ACFG_CS2U_VAL, &weim->cs2u);
-	writel(ACFG_CS2L_VAL, &weim->cs2l);
-	writel(ACFG_CS2A_VAL, &weim->cs2a);
-
-	writel(ACFG_CS3U_VAL, &weim->cs3u);
-	writel(ACFG_CS3L_VAL, &weim->cs3l);
-	writel(ACFG_CS3A_VAL, &weim->cs3a);
-
-	writel(ACFG_CS4U_VAL, &weim->cs4u);
-	writel(ACFG_CS4L_VAL, &weim->cs4l);
-	writel(ACFG_CS4A_VAL, &weim->cs4a);
-
-	writel(ACFG_CS5U_VAL, &weim->cs5u);
-	writel(ACFG_CS5L_VAL, &weim->cs5l);
-	writel(ACFG_CS5A_VAL, &weim->cs5a);
-
-	writel(ACFG_EIM_VAL, &weim->eim);
-}
-
-static void apf27_setup_port(void)
-{
-	struct system_control_regs *system =
-		(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
-
-	writel(ACFG_FMCR_VAL, &system->fmcr);
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	apf27_setup_csx();
-	apf27_setup_port();
-	apf27_iomux_init();
-	apf27_devices_init();
-#if defined(CONFIG_FPGA)
-	APF27_init_fpga();
-#endif
-
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-	if (get_num_ram_bank() > 1)
-		gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
-					     PHYS_SDRAM_2_SIZE);
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = get_ram_size((void *)PHYS_SDRAM_1,
-						PHYS_SDRAM_1_SIZE);
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	if (get_num_ram_bank() > 1)
-		gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
-					     PHYS_SDRAM_2_SIZE);
-	else
-		gd->bd->bi_dram[1].size = 0;
-
-	return 0;
-}
-
-ulong board_get_usable_ram_top(ulong total_size)
-{
-	ulong ramtop;
-
-	if (get_num_ram_bank() > 1)
-		ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2,
-						     PHYS_SDRAM_2_SIZE);
-	else
-		ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1,
-						     PHYS_SDRAM_1_SIZE);
-
-	return ramtop;
-}
-
-int checkboard(void)
-{
-	printf("Board: Armadeus APF27 revision %d\n", get_board_rev());
-	return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-inline void hang(void)
-{
-	for (;;)
-		;
-}
-
-void board_init_f(ulong bootflag)
-{
-	/*
-	 * copy ourselves from where we are running to where we were
-	 * linked at. Use ulong pointers as all addresses involved
-	 * are 4-byte-aligned.
-	 */
-	ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
-	asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
-	asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
-	asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
-	asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
-	for (dst = start_ptr; dst < end_ptr; dst++)
-		*dst = *(dst+(run_ptr-link_ptr));
-
-	/*
-	 * branch to nand_boot's link-time address.
-	 */
-	asm volatile("ldr pc, =nand_boot");
-}
-#endif /* CONFIG_SPL_BUILD */
diff --git a/board/armadeus/apf27/apf27.h b/board/armadeus/apf27/apf27.h
deleted file mode 100644
index 9c3cfd3cf4bd..000000000000
--- a/board/armadeus/apf27/apf27.h
+++ /dev/null
@@ -1,488 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
- */
-
-#ifndef __APF27_H
-#define __APF27_H
-
-/* FPGA program pin configuration */
-#define ACFG_FPGA_PWR	(GPIO_PORTF | 19)	/* FPGA prog pin  */
-#define ACFG_FPGA_PRG	(GPIO_PORTF | 11)	/* FPGA prog pin  */
-#define ACFG_FPGA_CLK	(GPIO_PORTF | 15)	/* FPGA clk pin   */
-#define ACFG_FPGA_RDATA	0xD6000000		/* FPGA data addr */
-#define ACFG_FPGA_WDATA	0xD6000000		/* FPGA data addr */
-#define ACFG_FPGA_INIT	(GPIO_PORTF | 12)	/* FPGA init pin  */
-#define ACFG_FPGA_DONE	(GPIO_PORTF | 9)	/* FPGA done pin  */
-#define ACFG_FPGA_RW	(GPIO_PORTF | 21)	/* FPGA done pin  */
-#define ACFG_FPGA_CS	(GPIO_PORTF | 22)	/* FPGA done pin  */
-#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10)	/* FPGA done pin  */
-#define ACFG_FPGA_RESET	(GPIO_PORTF | 7)	/* FPGA done pin  */
-
-/* MMC pin */
-#define PC_PWRON	(GPIO_PORTF | 16)
-
-/*
- * MPU CLOCK source before PLL
- * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
- */
-#define ACFG_MPCTL0_VAL		0x01EF15D5	/* 399.000 MHz */
-#define ACFG_MPCTL1_VAL		0
-#define CONFIG_MPLL_FREQ	399
-
-#define ACFG_CLK_FREQ	(CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
-
-/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/
-#define ACFG_SPCTL0_VAL		0x0475206F	/* 299.99937 MHz */
-#define ACFG_SPCTL1_VAL		0
-#define CONFIG_SPLL_FREQ	300		/* MHz */
-
-/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
-#define CONFIG_ARM_FREQ		399	/* up to 400 MHz */
-
-/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */
-#define CONFIG_HCLK_FREQ	133	/* (ACFG_CLK_FREQ/2) */
-
-#define CONFIG_PERIF1_FREQ	16	/* 16.625 MHz UART, GPT, PWM */
-#define CONFIG_PERIF2_FREQ	33	/* 33.25 MHz CSPI and SDHC */
-#define CONFIG_PERIF3_FREQ	33	/* 33.25 MHz LCD */
-#define CONFIG_PERIF4_FREQ	33	/* 33.25 MHz CSI */
-#define CONFIG_SSI1_FREQ	66	/* 66.50 MHz SSI1 */
-#define CONFIG_SSI2_FREQ	66	/* 66.50 MHz SSI2 */
-#define CONFIG_MSHC_FREQ	66	/* 66.50 MHz MSHC */
-#define CONFIG_H264_FREQ	66	/* 66.50 MHz H264 */
-#define CONFIG_CLK0_DIV		3	/* Divide CLK0 by 4 */
-#define CONFIG_CLK0_EN		1	/* CLK0 enabled */
-
-/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */
-#define CONFIG_NFC_FREQ		44	/* NFC Clock up to 44 MHz wh 133MHz */
-
-/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */
-#define CONFIG_USB_FREQ		60	/* 60 MHz */
-
-/*
- * SDRAM
- */
-#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
-/* micron 64MB */
-#define ACFG_SDRAM_NUM_COL		9  /* 8, 9, 10 or 11
-					    * column address bits
-					    */
-#define ACFG_SDRAM_NUM_ROW		13 /* 11, 12 or 13
-					    * row address bits
-					    */
-#define ACFG_SDRAM_REFRESH		3  /* 0=OFF 1=2048
-					    * 2=4096 3=8192 refresh
-					    */
-#define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
-					    * down delay
-					    */
-#define ACFG_SDRAM_W2R_DELAY		1  /* write to read
-					    * cycle delay > 0
-					    */
-#define ACFG_SDRAM_ROW_PRECHARGE_DELAY	18 /* ns */
-#define ACFG_SDRAM_TMRD_DELAY		2  /* Load mode register
-					    * cycle delay 1..4
-					    */
-#define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck
-					    * SDRAM: 0=1ck 1=2ck
-					    */
-#define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE delay */
-#define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE delay */
-#define ACFG_SDRAM_RCD_DELAY		18 /* ns Row to Column delay */
-#define ACFG_SDRAM_RC_DELAY		70 /* ns Row cycle delay (tRFC
-					    * refresh to command)
-					    */
-#define ACFG_SDRAM_CLOCK_CYCLE_CL_1	0 /* ns clock cycle time
-					   * estimated fo CL=1
-					   * 0=force 3 for lpddr
-					   */
-#define ACFG_SDRAM_PARTIAL_ARRAY_SR	0  /* 0=full 1=half 2=quater
-					    * 3=Eighth 4=Sixteenth
-					    */
-#define ACFG_SDRAM_DRIVE_STRENGH	0  /* 0=Full-strength 1=half
-					    * 2=quater 3=Eighth
-					    */
-#define ACFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
-#define ACFG_SDRAM_SINGLE_ACCESS	0  /* 1= single access
-					    * 0 = Burst mode
-					    */
-#endif
-
-#if (ACFG_SDRAM_MBYTE_SYZE == 128)
-/* micron 128MB */
-#define ACFG_SDRAM_NUM_COL		9  /* 8, 9, 10 or 11
-					    * column address bits
-					    */
-#define ACFG_SDRAM_NUM_ROW		14 /* 11, 12 or 13
-					    * row address bits
-					    */
-#define ACFG_SDRAM_REFRESH		3  /* 0=OFF 1=2048
-					    * 2=4096 3=8192 refresh
-					    */
-#define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
-					    * down delay
-					    */
-#define ACFG_SDRAM_W2R_DELAY		1  /* write to read
-					    * cycle delay > 0
-					    */
-#define ACFG_SDRAM_ROW_PRECHARGE_DELAY	18 /* ns */
-#define ACFG_SDRAM_TMRD_DELAY		2  /* Load mode register
-					    * cycle delay 1..4
-					    */
-#define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck
-					    * SDRAM: 0=1ck 1=2ck
-					    */
-#define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE delay */
-#define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE delay */
-#define ACFG_SDRAM_RCD_DELAY		18 /* ns Row to Column delay */
-#define ACFG_SDRAM_RC_DELAY		70 /* ns Row cycle delay (tRFC
-					    * refresh to command)
-					    */
-#define ACFG_SDRAM_CLOCK_CYCLE_CL_1	0 /* ns clock cycle time
-					   * estimated fo CL=1
-					   * 0=force 3 for lpddr
-					   */
-#define ACFG_SDRAM_PARTIAL_ARRAY_SR	0  /* 0=full 1=half 2=quater
-					    * 3=Eighth 4=Sixteenth
-					    */
-#define ACFG_SDRAM_DRIVE_STRENGH	0  /* 0=Full-strength 1=half
-					    * 2=quater 3=Eighth
-					    */
-#define ACFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
-#define ACFG_SDRAM_SINGLE_ACCESS	0  /* 1= single access
-					    * 0 = Burst mode
-					    */
-#endif
-
-#if (ACFG_SDRAM_MBYTE_SYZE == 256)
-/* micron 256MB */
-#define ACFG_SDRAM_NUM_COL		10  /* 8, 9, 10 or 11
-					     * column address bits
-					     */
-#define ACFG_SDRAM_NUM_ROW		14 /* 11, 12 or 13
-					    * row address bits
-					    */
-#define ACFG_SDRAM_REFRESH		3  /* 0=OFF 1=2048
-					    * 2=4096 3=8192 refresh
-					    */
-#define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
-					    * down delay
-					    */
-#define ACFG_SDRAM_W2R_DELAY		1  /* write to read cycle
-					    * delay > 0
-					    */
-#define ACFG_SDRAM_ROW_PRECHARGE_DELAY	18 /* ns */
-#define ACFG_SDRAM_TMRD_DELAY		2  /* Load mode register
-					    * cycle delay 1..4
-					    */
-#define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck
-					    * SDRAM: 0=1ck 1=2ck
-					    */
-#define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE delay */
-#define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE delay */
-#define ACFG_SDRAM_RCD_DELAY		18 /* ns Row to Column delay */
-#define ACFG_SDRAM_RC_DELAY		70 /* ns Row cycle delay (tRFC
-					    * refresh to command)
-					    */
-#define ACFG_SDRAM_CLOCK_CYCLE_CL_1	0 /* ns clock cycle time
-					   * estimated fo CL=1
-					   * 0=force 3 for lpddr
-					   */
-#define ACFG_SDRAM_PARTIAL_ARRAY_SR	0  /* 0=full 1=half 2=quater
-					    * 3=Eighth 4=Sixteenth
-					    */
-#define ACFG_SDRAM_DRIVE_STRENGH	0  /* 0=Full-strength
-					    * 1=half
-					    * 2=quater
-					    * 3=Eighth
-					    */
-#define ACFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
-#define ACFG_SDRAM_SINGLE_ACCESS	0  /* 1= single access
-					    * 0 = Burst mode
-					    */
-#endif
-
-/*
- * External interface
- */
-/*
- * CSCRxU_VAL:
- * 31| x | x | x x |x x x x| x x | x | x  |x x x x|16
- *   |SP |WP | BCD |  BCS  | PSZ |PME|SYNC|  DOL  |
- *
- * 15| x x  | x x x x x x | x | x x x x | x x x x |0
- *   | CNC  |     WSC     |EW |   WWS   |   EDC   |
- *
- * CSCRxL_VAL:
- * 31|  x x x x  | x x x x  | x x x x  | x x x x  |16
- *   |    OEA    |   OEN    |   EBWA   |   EBWN   |
- * 15|x x x x| x |x x x |x x x x| x | x | x  | x  | 0
- *   |  CSA  |EBC| DSZ  |  CSN  |PSR|CRE|WRAP|CSEN|
- *
- * CSCRxA_VAL:
- * 31|  x x x x  | x x x x  | x x x x  | x x x x  |16
- *   |   EBRA    |   EBRN   |   RWA    |   RWN    |
- * 15| x | x x |x x x|x x|x x|x x| x | x | x  | x | 0
- *   |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE|
- */
-
-/* CS0 configuration for 16 bit nor flash */
-#define ACFG_CS0U_VAL	0x0000CC03
-#define ACFG_CS0L_VAL	0xa0330D01
-#define ACFG_CS0A_VAL	0x00220800
-
-#define ACFG_CS1U_VAL	0x00000f00
-#define ACFG_CS1L_VAL	0x00000D01
-#define ACFG_CS1A_VAL	0
-
-#define ACFG_CS2U_VAL	0
-#define ACFG_CS2L_VAL	0
-#define ACFG_CS2A_VAL	0
-
-#define ACFG_CS3U_VAL	0
-#define ACFG_CS3L_VAL	0
-#define ACFG_CS3A_VAL	0
-
-#define ACFG_CS4U_VAL	0
-#define ACFG_CS4L_VAL	0
-#define ACFG_CS4A_VAL	0
-
-/* FPGA 16 bit data bus */
-#define ACFG_CS5U_VAL	0x00000600
-#define ACFG_CS5L_VAL	0x00000D01
-#define ACFG_CS5A_VAL	0
-
-#define ACFG_EIM_VAL	0x00002200
-
-
-/*
- * FPGA specific settings
- */
-
-/* CLKO */
-#define ACFG_CCSR_VAL 0x00000305
-/* drive strength CLKO set to 2 */
-#define ACFG_DSCR10_VAL 0x00020000
-/* drive strength A1..A12 set to 2 */
-#define ACFG_DSCR3_VAL 0x02AAAAA8
-/* drive strength ctrl */
-#define ACFG_DSCR7_VAL 0x00020880
-/* drive strength data */
-#define ACFG_DSCR2_VAL 0xAAAAAAAA
-
-
-/*
- * Default configuration for GPIOs and peripherals
- */
-#define ACFG_DDIR_A_VAL		0x00000000
-#define ACFG_OCR1_A_VAL		0x00000000
-#define ACFG_OCR2_A_VAL		0x00000000
-#define ACFG_ICFA1_A_VAL	0xFFFFFFFF
-#define ACFG_ICFA2_A_VAL	0xFFFFFFFF
-#define ACFG_ICFB1_A_VAL	0xFFFFFFFF
-#define ACFG_ICFB2_A_VAL	0xFFFFFFFF
-#define ACFG_DR_A_VAL		0x00000000
-#define ACFG_GIUS_A_VAL		0xFFFFFFFF
-#define ACFG_ICR1_A_VAL		0x00000000
-#define ACFG_ICR2_A_VAL		0x00000000
-#define ACFG_IMR_A_VAL		0x00000000
-#define ACFG_GPR_A_VAL		0x00000000
-#define ACFG_PUEN_A_VAL		0xFFFFFFFF
-
-#define ACFG_DDIR_B_VAL		0x00000000
-#define ACFG_OCR1_B_VAL		0x00000000
-#define ACFG_OCR2_B_VAL		0x00000000
-#define ACFG_ICFA1_B_VAL	0xFFFFFFFF
-#define ACFG_ICFA2_B_VAL	0xFFFFFFFF
-#define ACFG_ICFB1_B_VAL	0xFFFFFFFF
-#define ACFG_ICFB2_B_VAL	0xFFFFFFFF
-#define ACFG_DR_B_VAL		0x00000000
-#define ACFG_GIUS_B_VAL		0xFF3FFFF0
-#define ACFG_ICR1_B_VAL		0x00000000
-#define ACFG_ICR2_B_VAL		0x00000000
-#define ACFG_IMR_B_VAL		0x00000000
-#define ACFG_GPR_B_VAL		0x00000000
-#define ACFG_PUEN_B_VAL		0xFFFFFFFF
-
-#define ACFG_DDIR_C_VAL		0x00000000
-#define ACFG_OCR1_C_VAL		0x00000000
-#define ACFG_OCR2_C_VAL		0x00000000
-#define ACFG_ICFA1_C_VAL	0xFFFFFFFF
-#define ACFG_ICFA2_C_VAL	0xFFFFFFFF
-#define ACFG_ICFB1_C_VAL	0xFFFFFFFF
-#define ACFG_ICFB2_C_VAL	0xFFFFFFFF
-#define ACFG_DR_C_VAL		0x00000000
-#define ACFG_GIUS_C_VAL		0xFFFFC07F
-#define ACFG_ICR1_C_VAL		0x00000000
-#define ACFG_ICR2_C_VAL		0x00000000
-#define ACFG_IMR_C_VAL		0x00000000
-#define ACFG_GPR_C_VAL		0x00000000
-#define ACFG_PUEN_C_VAL		0xFFFFFF87
-
-#define ACFG_DDIR_D_VAL		0x00000000
-#define ACFG_OCR1_D_VAL		0x00000000
-#define ACFG_OCR2_D_VAL		0x00000000
-#define ACFG_ICFA1_D_VAL	0xFFFFFFFF
-#define ACFG_ICFA2_D_VAL	0xFFFFFFFF
-#define ACFG_ICFB1_D_VAL	0xFFFFFFFF
-#define ACFG_ICFB2_D_VAL	0xFFFFFFFF
-#define ACFG_DR_D_VAL		0x00000000
-#define ACFG_GIUS_D_VAL		0xFFFFFFFF
-#define ACFG_ICR1_D_VAL		0x00000000
-#define ACFG_ICR2_D_VAL		0x00000000
-#define ACFG_IMR_D_VAL		0x00000000
-#define ACFG_GPR_D_VAL		0x00000000
-#define ACFG_PUEN_D_VAL		0xFFFFFFFF
-
-#define ACFG_DDIR_E_VAL		0x00000000
-#define ACFG_OCR1_E_VAL		0x00000000
-#define ACFG_OCR2_E_VAL		0x00000000
-#define ACFG_ICFA1_E_VAL	0xFFFFFFFF
-#define ACFG_ICFA2_E_VAL	0xFFFFFFFF
-#define ACFG_ICFB1_E_VAL	0xFFFFFFFF
-#define ACFG_ICFB2_E_VAL	0xFFFFFFFF
-#define ACFG_DR_E_VAL		0x00000000
-#define ACFG_GIUS_E_VAL		0xFCFFCCF8
-#define ACFG_ICR1_E_VAL		0x00000000
-#define ACFG_ICR2_E_VAL		0x00000000
-#define ACFG_IMR_E_VAL		0x00000000
-#define ACFG_GPR_E_VAL		0x00000000
-#define ACFG_PUEN_E_VAL		0xFFFFFFFF
-
-#define ACFG_DDIR_F_VAL		0x00000000
-#define ACFG_OCR1_F_VAL		0x00000000
-#define ACFG_OCR2_F_VAL		0x00000000
-#define ACFG_ICFA1_F_VAL	0xFFFFFFFF
-#define ACFG_ICFA2_F_VAL	0xFFFFFFFF
-#define ACFG_ICFB1_F_VAL	0xFFFFFFFF
-#define ACFG_ICFB2_F_VAL	0xFFFFFFFF
-#define ACFG_DR_F_VAL		0x00000000
-#define ACFG_GIUS_F_VAL		0xFF7F8000
-#define ACFG_ICR1_F_VAL		0x00000000
-#define ACFG_ICR2_F_VAL		0x00000000
-#define ACFG_IMR_F_VAL		0x00000000
-#define ACFG_GPR_F_VAL		0x00000000
-#define ACFG_PUEN_F_VAL		0xFFFFFFFF
-
-/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */
-#define ACFG_GPCR_VAL		0x0003000F
-
-#define ACFG_ESDMISC_VAL	ESDMISC_LHD+ESDMISC_MDDREN
-
-/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */
-#if (CONFIG_NR_DRAM_BANKS == 1)
-#define ACFG_FMCR_VAL 0xFFFFFFF9
-#elif (CONFIG_NR_DRAM_BANKS == 2)
-#define ACFG_FMCR_VAL 0xFFFFFFFB
-#endif
-
-#define ACFG_AIPI1_PSR0_VAL	0x20040304
-#define ACFG_AIPI1_PSR1_VAL	0xDFFBFCFB
-#define ACFG_AIPI2_PSR0_VAL	0x00000000
-#define ACFG_AIPI2_PSR1_VAL	0xFFFFFFFF
-
-/* PCCR enable DMA FEC I2C1 IIM SDHC1 */
-#define ACFG_PCCR0_VAL		0x05070410
-#define ACFG_PCCR1_VAL		0xA14A0608
-
-/*
- * From here, there should not be any user configuration.
- * All Equations are automatic
- */
-
-/* fixme none integer value (7.5ns) => 2*hclock = 15ns */
-#define ACFG_2XHCLK_LGTH	(2000/CONFIG_HCLK_FREQ)	/* ns */
-
-/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/
-#define CSCR_MASK 0x0300800D
-
-#define ACFG_CSCR_VAL						\
-	(CSCR_MASK						\
-	|((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28)	\
-	|((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12)	\
-	|((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8))
-
-/* SSIx CLKO NFC H264 MSHC */
-#define ACFG_PCDR0_VAL\
-	(((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0)	\
-	|((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6)	\
-	|(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\
-	|(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\
-	|(((CONFIG_CLK0_DIV)&0x07)<<22)\
-	|(((CONFIG_CLK0_EN)&0x01)<<25)\
-	|(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26))
-
-/* PERCLKx  */
-#define ACFG_PCDR1_VAL\
-	(((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0)	\
-	|((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8)	\
-	|((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16)	\
-	|((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24))
-
-/* SDRAM controller programming Values */
-#if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \
-	(ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1))
-#define REG_FIELD_SCL_VAL 3
-#define REG_FIELD_SCLIMX_VAL 0
-#else
-#define REG_FIELD_SCL_VAL\
-	((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \
-		ACFG_2XHCLK_LGTH)
-#define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL
-#endif
-
-#if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH))
-#define REG_FIELD_SRC_VAL 0
-#else
-#define REG_FIELD_SRC_VAL\
-	((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \
-		ACFG_2XHCLK_LGTH)
-#endif
-
-/* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/
-#define REG_ESDCTL_BASE_CONFIG (0x80020485\
-				| (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\
-				| (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\
-				| (((ACFG_SDRAM_REFRESH)&0x7)<<13))
-
-#define ACFG_NORMAL_RW_CMD	((0x0<<28)+REG_ESDCTL_BASE_CONFIG)
-#define ACFG_PRECHARGE_CMD	((0x1<<28)+REG_ESDCTL_BASE_CONFIG)
-#define ACFG_AUTOREFRESH_CMD	((0x2<<28)+REG_ESDCTL_BASE_CONFIG)
-#define ACFG_SET_MODE_REG_CMD	((0x3<<28)+REG_ESDCTL_BASE_CONFIG)
-
-/* ESDRAMC Configuration Registers : force CL=3 to lpddr */
-#define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\
-	| (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \
-		ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\
-	| (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\
-	| (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \
-		ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \
-	| (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\
-	| (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\
-	| (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \
-		ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \
-	| (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
-		ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \
-	| (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\
-	| (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
-		ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \
-	| (((REG_FIELD_SRC_VAL)&0x0F)<<0))
-
-/* Issue Mode register Command to SDRAM */
-#define ACFG_SDRAM_MODE_REGISTER_VAL\
-	((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\
-	| (((REG_FIELD_SCL_VAL)&0x7)<<(4))\
-	| ((0)<<(3)) /* sequentiql access */ \
-	/*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/)
-
-/* Issue Extended Mode register Command to SDRAM */
-#define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\
-	((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\
-	| (ACFG_SDRAM_DRIVE_STRENGH<<(5))\
-	| (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2)))
-
-/* Issue Precharge all Command to SDRAM */
-#define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10)
-
-#endif /* __APF27_H */
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
deleted file mode 100644
index 9e2f39f9814f..000000000000
--- a/board/armadeus/apf27/fpga.c
+++ /dev/null
@@ -1,226 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002-2013
- * Eric Jarrige <eric.jarrige@armadeus.org>
- *
- * based on the files by
- * Rich Ireland, Enterasys Networks, rireland at enterasys.com
- * and
- * Keith Outwater, keith_outwater at mvis.com
- */
-#include <common.h>
-#include <log.h>
-#include <linux/delay.h>
-
-#include <asm/arch/imx-regs.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <command.h>
-#include <config.h>
-#include "fpga.h"
-#include <spartan3.h>
-#include "apf27.h"
-
-/*
- * Note that these are pointers to code that is in Flash.  They will be
- * relocated at runtime.
- * Spartan2 code is used to download our Spartan 3 :) code is compatible.
- * Just take care about the file size
- */
-xilinx_spartan3_slave_parallel_fns fpga_fns = {
-	fpga_pre_fn,
-	fpga_pgm_fn,
-	fpga_init_fn,
-	NULL,
-	fpga_done_fn,
-	fpga_clk_fn,
-	fpga_cs_fn,
-	fpga_wr_fn,
-	fpga_rdata_fn,
-	fpga_wdata_fn,
-	fpga_busy_fn,
-	fpga_abort_fn,
-	fpga_post_fn,
-};
-
-xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-	{xilinx_spartan3,
-	 slave_parallel,
-	 1196128l/8,
-	 (void *)&fpga_fns,
-	 0,
-	 &spartan3_op,
-	 "3s200aft256"}
-};
-
-/*
- * Initialize GPIO port B before download
- */
-int fpga_pre_fn(int cookie)
-{
-	/* Initialize GPIO pins */
-	gpio_set_value(ACFG_FPGA_PWR, 1);
-	imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
-	imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
-	imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-	imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-	imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-	imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-	imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO);
-	gpio_set_value(ACFG_FPGA_RESET, 1);
-	imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-	imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-	gpio_set_value(ACFG_FPGA_PRG, 1);
-	gpio_set_value(ACFG_FPGA_CLK, 1);
-	gpio_set_value(ACFG_FPGA_RW, 1);
-	gpio_set_value(ACFG_FPGA_CS, 1);
-	gpio_set_value(ACFG_FPGA_SUSPEND, 0);
-	gpio_set_value(ACFG_FPGA_PWR, 0);
-	udelay(30000); /*wait until supply started*/
-
-	return cookie;
-}
-
-/*
- * Set the FPGA's active-low program line to the specified level
- */
-int fpga_pgm_fn(int assert, int flush, int cookie)
-{
-	debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
-	      assert ? "high" : "low");
-	gpio_set_value(ACFG_FPGA_PRG, !assert);
-	return assert;
-}
-
-/*
- * Set the FPGA's active-high clock line to the specified level
- */
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
-	      assert_clk ? "high" : "low");
-	gpio_set_value(ACFG_FPGA_CLK, !assert_clk);
-	return assert_clk;
-}
-
-/*
- * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
- * asserted (low).
- */
-int fpga_init_fn(int cookie)
-{
-	int value;
-	debug("%s:%d: INIT check... ", __func__, __LINE__);
-	value = gpio_get_value(ACFG_FPGA_INIT);
-	/* printf("init value read %x",value); */
-#ifdef CONFIG_SYS_FPGA_IS_PROTO
-	return value;
-#else
-	return !value;
-#endif
-}
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-int fpga_done_fn(int cookie)
-{
-	debug("%s:%d: DONE check... %s", __func__, __LINE__,
-	      gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
-	return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL;
-}
-
-/*
- * Set the FPGA's wr line to the specified level
- */
-int fpga_wr_fn(int assert_write, int flush, int cookie)
-{
-	debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,
-	      assert_write ? "high" : "low");
-	gpio_set_value(ACFG_FPGA_RW, !assert_write);
-	return assert_write;
-}
-
-int fpga_cs_fn(int assert_cs, int flush, int cookie)
-{
-	debug("%s:%d: FPGA CS %s ", __func__, __LINE__,
-	      assert_cs ? "high" : "low");
-	gpio_set_value(ACFG_FPGA_CS, !assert_cs);
-	return assert_cs;
-}
-
-int fpga_rdata_fn(unsigned char *data, int cookie)
-{
-	debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,
-	      *((char *)ACFG_FPGA_RDATA));
-	*data = (unsigned char)
-		((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF);
-	return *data;
-}
-
-int fpga_wdata_fn(unsigned char data, int flush, int cookie)
-{
-	debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,
-	      data);
-	*((unsigned short *)ACFG_FPGA_WDATA) = data;
-	return data;
-}
-
-int fpga_abort_fn(int cookie)
-{
-	return fpga_post_fn(cookie);
-}
-
-
-int fpga_busy_fn(int cookie)
-{
-	return 1;
-}
-
-int fpga_post_fn(int cookie)
-{
-	debug("%s:%d: FPGA POST ", __func__, __LINE__);
-
-	imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN);
-	imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN);
-	imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN);
-	gpio_set_value(ACFG_FPGA_PRG, 1);
-	gpio_set_value(ACFG_FPGA_RESET, 0);
-	imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-	return cookie;
-}
-
-void apf27_fpga_setup(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	struct system_control_regs *system =
-		(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
-
-	/* Configure FPGA CLKO */
-	writel(ACFG_CCSR_VAL, &pll->ccsr);
-
-	/* Configure strentgh for FPGA */
-	writel(ACFG_DSCR10_VAL, &system->dscr10);
-	writel(ACFG_DSCR3_VAL, &system->dscr3);
-	writel(ACFG_DSCR7_VAL, &system->dscr7);
-	writel(ACFG_DSCR2_VAL, &system->dscr2);
-}
-
-/*
- * Initialize the fpga.  Return 1 on success, 0 on failure.
- */
-void APF27_init_fpga(void)
-{
-	int i;
-
-	apf27_fpga_setup();
-
-	fpga_init();
-
-	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
-		debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
-		fpga_add(fpga_xilinx, &fpga[i]);
-	}
-
-	return;
-}
diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h
deleted file mode 100644
index d6394e976a85..000000000000
--- a/board/armadeus/apf27/fpga.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2002-2013
- * Eric Jarrige <eric.jarrige@armadeus.org>
- *
- * based on the files by
- * Rich Ireland, Enterasys Networks, rireland at enterasys.com
- * and
- * Keith Outwater, keith_outwater at mvis.com
- */
-extern void APF27_init_fpga(void);
-
-extern int fpga_pre_fn(int cookie);
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
-extern int fpga_init_fn(int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int fpga_rdata_fn(unsigned char *data, int cookie);
-extern int fpga_wdata_fn(unsigned char data, int flush, int cookie);
-extern int fpga_abort_fn(int cookie);
-extern int fpga_post_fn(int cookie);
-extern int fpga_busy_fn(int cookie);
diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
deleted file mode 100644
index 0991b7ddf499..000000000000
--- a/board/armadeus/apf27/lowlevel_init.S
+++ /dev/null
@@ -1,166 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
- */
-
-#include <config.h>
-#include <generated/asm-offsets.h>
-#include <asm/macro.h>
-#include <asm/arch/imx-regs.h>
-#include "apf27.h"
-
-	.macro init_aipi
-	/*
-	 * setup AIPI1 and AIPI2
-	 */
-	write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
-	write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
-	write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
-	write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
-
-	/* Change SDRAM signal strengh */
-	ldr r0, =GPCR
-	ldr r1, =ACFG_GPCR_VAL
-	ldr r5, [r0]
-	orr r5, r5, r1
-	str r5, [r0]
-
-	.endm /* init_aipi */
-
-	.macro init_clock
-	ldr r0, =CSCR
-	/* disable MPLL/SPLL first */
-	ldr r1, [r0]
-	bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
-	str r1, [r0]
-
- 	/*
-	 * pll clock initialization predefined in apf27.h
-	 */
-	write32 MPCTL0, ACFG_MPCTL0_VAL
-	write32 SPCTL0, ACFG_SPCTL0_VAL
-
-	write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
-
-	/*
-	 * add some delay here
-	 */
-	mov r1, #0x1000
-	1:  subs r1, r1, #0x1
-	bne 1b
-
-	/* peripheral clock divider */
-	write32 PCDR0, ACFG_PCDR0_VAL
-	write32 PCDR1, ACFG_PCDR1_VAL
-
-	/* Configure PCCR0 and PCCR1 */
-	write32 PCCR0, ACFG_PCCR0_VAL
-	write32 PCCR1, ACFG_PCCR1_VAL
-
-	.endm /* init_clock */
-
-	.macro init_ddr
-	/* wait for SDRAM/LPDDR ready (SDRAMRDY) */
-	ldr		r0, =IMX_ESD_BASE
-	ldr		r4, =ESDMISC_SDRAM_RDY
-2:	ldr		r1, [r0, #ESDMISC_ROF]
-	ands		r1, r1, r4
-	bpl		2b
-
-	/* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
-	ldr		r0, =IMX_ESD_BASE
-	ldr		r4, =ACFG_ESDMISC_VAL
-	orr		r1, r4, #ESDMISC_MDDR_DL_RST
-	str		r1, [r0, #ESDMISC_ROF]
-
-	/* Hold for more than 200ns */
-	ldr		r1, =0x10000
-1:	subs		r1, r1, #0x1
-	bne		1b
-
-	str		r4, [r0]
-
-	ldr		r0, =IMX_ESD_BASE
-	ldr		r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
-	str		r1, [r0, #ESDCFG0_ROF]
-
-	ldr		r0, =IMX_ESD_BASE
-	ldr		r1, =ACFG_PRECHARGE_CMD
-	str		r1, [r0, #ESDCTL0_ROF]
-
-	/* write8(0xA0001000, any value) */
-	ldr		r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
-	strb		r2, [r1]
-
-	ldr		r1, =ACFG_AUTOREFRESH_CMD
-	str		r1, [r0, #ESDCTL0_ROF]
-
-	ldr 		r4, =PHYS_SDRAM_1	/* CSD0 base address	*/
-
-	ldr 		r6,=0x7		/* load loop counter	*/
-1:	str 		r5,[r4]		/* run auto-refresh cycle to array 0 */
-	subs 		r6,r6,#1
-	bne 1b
-
-	ldr		r1, =ACFG_SET_MODE_REG_CMD
-	str		r1, [r0, #ESDCTL0_ROF]
-
-	/* set standard mode register */
-	ldr		r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
-	strb		r2, [r4]
-
-	/* set extended mode register */
-	ldr		r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
-	strb		r5, [r4]
-
-	ldr		r1, =ACFG_NORMAL_RW_CMD
-	str		r1, [r0, #ESDCTL0_ROF]
-
-	/* 2nd sdram */
-	ldr		r0, =IMX_ESD_BASE
-	ldr		r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
-	str		r1, [r0, #ESDCFG1_ROF]
-
-	ldr		r0, =IMX_ESD_BASE
-	ldr		r1, =ACFG_PRECHARGE_CMD
-	str		r1, [r0, #ESDCTL1_ROF]
-
-	/* write8(0xB0001000, any value) */
-	ldr		r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
-	strb		r2, [r1]
-
-	ldr		r1, =ACFG_AUTOREFRESH_CMD
-	str		r1, [r0, #ESDCTL1_ROF]
-
-	ldr 		r4, =PHYS_SDRAM_2	/* CSD1 base address */
-
-	ldr 		r6,=0x7		/* load loop counter */
-1:	str 		r5,[r4]		/* run auto-refresh cycle to array 0 */
-	subs 		r6,r6,#1
-	bne 1b
-
-	ldr		r1, =ACFG_SET_MODE_REG_CMD
-	str		r1, [r0, #ESDCTL1_ROF]
-
-	/* set standard mode register */
-	ldr		r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
-	strb		r2, [r4]
-
-	/* set extended mode register */
-	ldr		r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
-	strb		r2, [r4]
-
-	ldr		r1, =ACFG_NORMAL_RW_CMD
-	str		r1, [r0, #ESDCTL1_ROF]
-	.endm /* init_ddr */
-
-.globl lowlevel_init
-lowlevel_init:
-
-	init_aipi
-	init_clock
-#ifdef CONFIG_SPL_BUILD
-	init_ddr
-#endif
-
-	mov	pc, lr
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
deleted file mode 100644
index edb8c2b47732..000000000000
--- a/configs/apf27_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_ARM=y
-# CONFIG_SPL_USE_ARCH_MEMCPY is not set
-CONFIG_TARGET_APF27=y
-CONFIG_SYS_TEXT_BASE=0xA0000800
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xA0000000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x180000
-CONFIG_IDENT_STRING=" apf27 patch 3.10"
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_BOOTDELAY=5
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySMX0,115200 mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs) ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
-CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="run check_flash check_env;"
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="BIOS> "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_DHCP=y
-CONFIG_BOOTP_DNS2=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_SPARTAN3=y
-CONFIG_MXC_GPIO=y
-CONFIG_MMC_MXC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXC=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_OF_LIBFDT=y
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 79ad0a1b3435..404cc6b7d703 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -635,7 +635,7 @@ config MCFUART
 
 config MXC_UART
 	bool "IMX serial port support"
-	depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 \
+	depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \
 		|| MX5 || MX6 || MX7 || IMX8M
 	help
 	  If you have a machine based on a Motorola IMX CPU you
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
deleted file mode 100644
index b69e5772a68e..000000000000
--- a/include/configs/apf27.h
+++ /dev/null
@@ -1,266 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * Configuration settings for the Armadeus Project motherboard APF27
- *
- * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#define CONFIG_ENV_VERSION	10
-#define CONFIG_BOARD_NAME apf27
-
-/*
- * SoC configurations
- */
-#define CONFIG_MX27			/* This is a Freescale i.MX27 Chip */
-#define CONFIG_MACH_TYPE	1698	/* APF27 */
-
-/*
- * Enable the call to miscellaneous platform dependent initialization.
- */
-
-/*
- * SPL
- */
-#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
-#define CONFIG_SPL_MAX_SIZE	2048
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x800
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	CONFIG_SYS_MONITOR_LEN - 0x800
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_HOSTNAME	"apf27"
-#define CONFIG_ROOTPATH	"/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
-
-/*
- * Memory configurations
- */
-#define CONFIG_NR_DRAM_POPULATED 1
-
-#define ACFG_SDRAM_MBYTE_SYZE 64
-
-#define PHYS_SDRAM_1			0xA0000000
-#define PHYS_SDRAM_2			0xB0000000
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (512<<10))
-
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
-		+ PHYS_SDRAM_1_SIZE - 0x0100000)
-
-/*
- * FLASH organization
- */
-#define	ACFG_MONITOR_OFFSET		0x00000000
-#define	CONFIG_SYS_MONITOR_LEN		0x00100000	/* 1MiB */
-#define CONFIG_ENV_RANGE		0X00080000	/* 512kB */
-#define	CONFIG_FIRMWARE_OFFSET		0x00200000
-#define	CONFIG_FIRMWARE_SIZE		0x00080000	/* 512kB  */
-#define	CONFIG_KERNEL_OFFSET		0x00300000
-#define	CONFIG_ROOTFS_OFFSET		0x00800000
-
-/*
- * U-Boot general configurations
- */
-#define CONFIG_SYS_CBSIZE		2048		/* console I/O buffer */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-						/* Boot argument buffer size */
-
-/*
- * Boot Linux
- */
-#define CONFIG_CMDLINE_TAG		/* send commandline to Kernel	*/
-#define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
-#define CONFIG_INITRD_TAG		/* send initrd params	*/
-
-#define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"
-
-#define ACFG_CONSOLE_DEV	ttySMX0
-#define CONFIG_BOOTCOMMAND	"run ubifsboot"
-#define CONFIG_SYS_AUTOLOAD	"no"
-/*
- * Default load address for user programs and kernel
- */
-#define CONFIG_LOADADDR			0xA0000000
-#define	CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-
-/*
- * Extra Environments
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"env_version="		__stringify(CONFIG_ENV_VERSION)		"\0" \
-	"consoledev="		__stringify(ACFG_CONSOLE_DEV)		"\0" \
-	"mtdparts="	 	CONFIG_MTDPARTS_DEFAULT	"\0" \
-	"partition=nand0,6\0"						\
-	"u-boot_addr="		__stringify(ACFG_MONITOR_OFFSET)	"\0" \
-	"env_addr="		__stringify(CONFIG_ENV_OFFSET)		"\0" \
-	"firmware_addr="	__stringify(CONFIG_FIRMWARE_OFFSET)	"\0" \
-	"firmware_size="	__stringify(CONFIG_FIRMWARE_SIZE)	"\0" \
-	"kernel_addr="		__stringify(CONFIG_KERNEL_OFFSET)	"\0" \
-	"rootfs_addr="		__stringify(CONFIG_ROOTFS_OFFSET)	"\0" \
-	"board_name="		__stringify(CONFIG_BOARD_NAME)		"\0" \
-	"kernel_addr_r=A0000000\0" \
-	"check_env=if test -n ${flash_env_version}; "			\
-		"then env default env_version; "			\
-		"else env set flash_env_version ${env_version}; env save; "\
-		"fi; "							\
-		"if itest ${flash_env_version} < ${env_version}; then " \
-			"echo \"*** Warning - Environment version"	\
-			" change suggests: run flash_reset_env; reset\"; "\
-			"env default flash_reset_env; "\
-		"fi; \0"						\
-	"check_flash=nand lock; nand unlock ${env_addr}; \0"	\
-	"flash_reset_env=env default -f -a; saveenv; run update_env;"	\
-		"echo Flash environment variables erased!\0"		\
-	"download_uboot=tftpboot ${loadaddr} ${board_name}"		\
-		"-u-boot-with-spl.bin\0"				\
-	"flash_uboot=nand unlock ${u-boot_addr} ;"			\
-		"nand erase.part u-boot;"		\
-		"if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
-			"then nand lock; nand unlock ${env_addr};"	\
-				"echo Flashing of uboot succeed;"	\
-			"else echo Flashing of uboot failed;"		\
-		"fi; \0"						\
-	"update_uboot=run download_uboot flash_uboot\0"			\
-	"download_env=tftpboot ${loadaddr} ${board_name}"		\
-		"-u-boot-env.txt\0"				\
-	"flash_env=env import -t ${loadaddr}; env save; \0"		\
-	"update_env=run download_env flash_env\0"			\
-	"update_all=run update_env update_uboot\0"			\
-	"unlock_regs=mw 10000008 0; mw 10020008 0\0"			\
-
-/*
- * Serial Driver
- */
-#define CONFIG_MXC_UART_BASE		UART1_BASE
-
-/*
- * NOR
- */
-
-/*
- * NAND
- */
-
-#define CONFIG_MXC_NAND_REGS_BASE	0xD8000000
-#define CONFIG_SYS_NAND_BASE		CONFIG_MXC_NAND_REGS_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-#define CONFIG_SYS_NAND_PAGE_COUNT	CONFIG_SYS_NAND_BLOCK_SIZE / \
-						CONFIG_SYS_NAND_PAGE_SIZE
-#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	11
-#define NAND_MAX_CHIPS			1
-
-#define CONFIG_FLASH_SHOW_PROGRESS	45
-#define CONFIG_SYS_NAND_QUIET		1
-
-/*
- * Partitions & Filsystems
- */
-
-/*
- * Ethernet (on SOC imx FEC)
- */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_PHYADDR		0x1f
-
-/*
- * FPGA
- */
-#define CONFIG_FPGA_COUNT		1
-#define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_CHECK_CTRLC
-#define CONFIG_SYS_FPGA_CHECK_ERROR
-
-/*
- * Fuses - IIM
- */
-#ifdef CONFIG_CMD_IMX_FUSE
-#define IIM_MAC_BANK		0
-#define IIM_MAC_ROW		5
-#define IIM0_SCC_KEY		11
-#define IIM1_SUID		1
-#endif
-
-/*
- * I2C
- */
-
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
-#define CONFIG_SYS_MXC_I2C1_SPEED	100000	/* 100 kHz */
-#define CONFIG_SYS_MXC_I2C1_SLAVE	0x7F
-#define CONFIG_SYS_MXC_I2C2_SPEED	100000	/* 100 kHz */
-#define CONFIG_SYS_MXC_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_I2C_NOPROBES		{ }
-
-#ifdef CONFIG_CMD_EEPROM
-# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24LC02 */
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* msec */
-#endif /* CONFIG_CMD_EEPROM */
-#endif /* CONFIG_CMD_I2C */
-
-/*
- * SD/MMC
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MXC_MCI_REGS_BASE	0x10014000
-#endif
-
-/*
- * RTC
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1374
-#define CONFIG_SYS_RTC_BUS_NUM		0
-#endif /* CONFIG_CMD_DATE */
-
-/*
- * PLL
- *
- *  31 | x  |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
- *     |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
- */
-#define CONFIG_MX27_CLK32		32768	/* 32768 or 32000 Hz crystal */
-
-#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
-/* micron 64MB */
-#define PHYS_SDRAM_1_SIZE			0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2_SIZE			0x04000000 /* 64 MB */
-#endif
-
-#if (ACFG_SDRAM_MBYTE_SYZE == 128)
-/* micron 128MB */
-#define PHYS_SDRAM_1_SIZE			0x08000000 /* 128 MB */
-#define PHYS_SDRAM_2_SIZE			0x08000000 /* 128 MB */
-#endif
-
-#if (ACFG_SDRAM_MBYTE_SYZE == 256)
-/* micron 256MB */
-#define PHYS_SDRAM_1_SIZE			0x10000000 /* 256 MB */
-#define PHYS_SDRAM_2_SIZE			0x10000000 /* 256 MB */
-#endif
-
-#endif /* __CONFIG_H */
-- 
2.17.1