* [PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again
@ 2021-02-09 13:47 Heiko Stuebner
2021-02-09 13:47 ` [PATCH 1/8] rockchip: rk3368: adjust CONFIG_SYS_LOAD_ADDR Heiko Stuebner
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Heiko Stuebner @ 2021-02-09 13:47 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
With current u-boot (and probably for some time now) rk3368-lion
can't boot anymore. As the patches indicate, that is partially
on the lion support but also on general rk3368-support not fitting
current expectations anymore.
So this series, adapts options to what other Rockchip SoCs do
and makes lion also bootable again.
Heiko Stuebner (8):
rockchip: rk3368: adjust CONFIG_SYS_LOAD_ADDR
rockchip: rk3368: set CONFIG_SYS_BOOTM_LEN to 64MB
rockchip: rk3368: increase SYS_MALLOC_F_LEN to 0x4000
rockchip: rk3368: move STACK_R_ADDR address and into Kconfig
rockchip: rk3368: sync clock dt-binding header from Linux
rockchip: rk3368: sync main rk3368 dtsi from Linux
rockchip: rk3368: sync down rk3368-lion board devicetree from Linux
rockchip: lion: update board defconfig
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/rk3368-geekbox-u-boot.dtsi | 2 +
...ot.dtsi => rk3368-lion-haikou-u-boot.dtsi} | 6 +
arch/arm/dts/rk3368-lion-haikou.dts | 140 +++++
.../dts/{rk3368-lion.dts => rk3368-lion.dtsi} | 271 ++++++--
arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 3 +
arch/arm/dts/rk3368-sheep-u-boot.dtsi | 2 +
arch/arm/dts/rk3368-u-boot.dtsi | 27 +
arch/arm/dts/rk3368.dtsi | 578 +++++++++++-------
arch/arm/mach-rockchip/rk3368/Kconfig | 5 +-
configs/lion-rk3368_defconfig | 19 +-
include/configs/rk3368_common.h | 4 +-
include/dt-bindings/clock/rk3368-cru.h | 31 +-
13 files changed, 769 insertions(+), 321 deletions(-)
rename arch/arm/dts/{rk3368-lion-u-boot.dtsi => rk3368-lion-haikou-u-boot.dtsi} (96%)
create mode 100644 arch/arm/dts/rk3368-lion-haikou.dts
rename arch/arm/dts/{rk3368-lion.dts => rk3368-lion.dtsi} (54%)
create mode 100644 arch/arm/dts/rk3368-u-boot.dtsi
--
2.29.2
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/8] rockchip: rk3368: adjust CONFIG_SYS_LOAD_ADDR
2021-02-09 13:47 [PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again Heiko Stuebner
@ 2021-02-09 13:47 ` Heiko Stuebner
2021-02-09 13:47 ` [PATCH 2/8] rockchip: rk3368: set CONFIG_SYS_BOOTM_LEN to 64MB Heiko Stuebner
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2021-02-09 13:47 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
CONFIG_SYS_LOAD_ADDR currently is at 0x00280000 which is only 512KB
behind the area where we load u-boot to, which depending on u-boot size
may overlap at some point.
So for safety just pick the same value rk3399 has and set
CONFIG_SYS_LOAD_ADDR to 0x00800800 on rk3368 as well.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
include/configs/rk3368_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index f178a06945..86498b4c82 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -24,7 +24,7 @@
#define CONFIG_IRAM_BASE 0xff8c0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
-#define CONFIG_SYS_LOAD_ADDR 0x00280000
+#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_BSS_START_ADDR 0x400000
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/8] rockchip: rk3368: set CONFIG_SYS_BOOTM_LEN to 64MB
2021-02-09 13:47 [PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again Heiko Stuebner
2021-02-09 13:47 ` [PATCH 1/8] rockchip: rk3368: adjust CONFIG_SYS_LOAD_ADDR Heiko Stuebner
@ 2021-02-09 13:47 ` Heiko Stuebner
2021-02-09 13:47 ` [PATCH 3/8] rockchip: rk3368: increase SYS_MALLOC_F_LEN to 0x4000 Heiko Stuebner
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2021-02-09 13:47 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Mimicing for example the rk3399, set the SYS_BOOTM_LEN to 64MB so
that regular kernel images can get loaded without problems.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
include/configs/rk3368_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 86498b4c82..fbbb8cf267 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -31,6 +31,8 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
#define CONFIG_SPL_STACK 0x00188000
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00500000\0" \
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/8] rockchip: rk3368: increase SYS_MALLOC_F_LEN to 0x4000
2021-02-09 13:47 [PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again Heiko Stuebner
2021-02-09 13:47 ` [PATCH 1/8] rockchip: rk3368: adjust CONFIG_SYS_LOAD_ADDR Heiko Stuebner
2021-02-09 13:47 ` [PATCH 2/8] rockchip: rk3368: set CONFIG_SYS_BOOTM_LEN to 64MB Heiko Stuebner
@ 2021-02-09 13:47 ` Heiko Stuebner
2021-02-09 13:47 ` [PATCH 4/8] rockchip: rk3368: move STACK_R_ADDR address and into Kconfig Heiko Stuebner
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2021-02-09 13:47 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
To prevent running out of memory, increase SYS_MALLOC_F_LEN to 0x4000
similar to what rk3399 uses.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
arch/arm/mach-rockchip/rk3368/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index d6ca5f1d24..c31915e7dc 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -49,7 +49,7 @@ config SYS_SOC
default "rk3368"
config SYS_MALLOC_F_LEN
- default 0x2000
+ default 0x4000
config SPL_LIBCOMMON_SUPPORT
default y
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/8] rockchip: rk3368: move STACK_R_ADDR address and into Kconfig
2021-02-09 13:47 [PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again Heiko Stuebner
` (2 preceding siblings ...)
2021-02-09 13:47 ` [PATCH 3/8] rockchip: rk3368: increase SYS_MALLOC_F_LEN to 0x4000 Heiko Stuebner
@ 2021-02-09 13:47 ` Heiko Stuebner
2021-02-09 13:47 ` [PATCH 5/8] rockchip: rk3368: sync clock dt-binding header from Linux Heiko Stuebner
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2021-02-09 13:47 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
With the STACK_R_ADDR at 0x600000 (6MB) we're competing with
with the loading address of either u-boot or atf parts, so move
that away to 0x4000000 (64MB) similar to rk3399.
Only lion currently sets that at all but not sheep the second
rk3368 board, so just move that to the Kconfig for rk3368 similar
to rk3399 as well.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
arch/arm/mach-rockchip/rk3368/Kconfig | 3 +++
configs/lion-rk3368_defconfig | 1 -
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index c31915e7dc..78eb96df3d 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -65,6 +65,9 @@ source "board/rockchip/evb_px5/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds"
+config SPL_STACK_R_ADDR
+ default 0x04000000
+
config TPL_MAX_SIZE
default 28672
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 583dd44da3..b409715060 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -9,7 +9,6 @@ CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xFF180000
CONFIG_DEBUG_UART_CLOCK=24000000
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/8] rockchip: rk3368: sync clock dt-binding header from Linux
2021-02-09 13:47 [PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again Heiko Stuebner
` (3 preceding siblings ...)
2021-02-09 13:47 ` [PATCH 4/8] rockchip: rk3368: move STACK_R_ADDR address and into Kconfig Heiko Stuebner
@ 2021-02-09 13:47 ` Heiko Stuebner
2021-02-09 13:47 ` [PATCH 6/8] rockchip: rk3368: sync main rk3368 dtsi " Heiko Stuebner
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2021-02-09 13:47 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
This is the state as of v5.10 in Linux.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
include/dt-bindings/clock/rk3368-cru.h | 31 ++++++++++++--------------
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index 9c5dd9ba2f..0a06c5f514 100644
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -1,15 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
@@ -44,13 +35,12 @@
#define SCLK_I2S_8CH 82
#define SCLK_SPDIF_8CH 83
#define SCLK_I2S_2CH 84
-#define SCLK_TIMER0 85
-#define SCLK_TIMER1 86
-#define SCLK_TIMER2 87
-#define SCLK_TIMER3 88
-#define SCLK_TIMER4 89
-#define SCLK_TIMER5 90
-#define SCLK_TIMER6 91
+#define SCLK_TIMER00 85
+#define SCLK_TIMER01 86
+#define SCLK_TIMER02 87
+#define SCLK_TIMER03 88
+#define SCLK_TIMER04 89
+#define SCLK_TIMER05 90
#define SCLK_OTGPHY0 93
#define SCLK_OTG_ADP 96
#define SCLK_HSICPHY480M 97
@@ -82,6 +72,12 @@
#define SCLK_SFC 126
#define SCLK_MAC 127
#define SCLK_MACREF_OUT 128
+#define SCLK_TIMER10 133
+#define SCLK_TIMER11 134
+#define SCLK_TIMER12 135
+#define SCLK_TIMER13 136
+#define SCLK_TIMER14 137
+#define SCLK_TIMER15 138
#define DCLK_VOP 190
#define MCLK_CRYPTO 191
@@ -151,6 +147,7 @@
#define PCLK_ISP 366
#define PCLK_VIP 367
#define PCLK_WDT 368
+#define PCLK_EFUSE256 369
/* hclk gates */
#define HCLK_SFC 448
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 6/8] rockchip: rk3368: sync main rk3368 dtsi from Linux
2021-02-09 13:47 [PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again Heiko Stuebner
` (4 preceding siblings ...)
2021-02-09 13:47 ` [PATCH 5/8] rockchip: rk3368: sync clock dt-binding header from Linux Heiko Stuebner
@ 2021-02-09 13:47 ` Heiko Stuebner
2021-02-09 13:47 ` [PATCH 7/8] rockchip: rk3368: sync down rk3368-lion board devicetree " Heiko Stuebner
2021-02-09 13:47 ` [PATCH 8/8] rockchip: lion: update board defconfig Heiko Stuebner
7 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2021-02-09 13:47 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
This is the state as of v5.10 + the recently added timer0 phandle
targetted at the 5.12 merge window.
With this the non-mainline nodes like the dmc move to a separate
rk3368-u-boot.dtsi that is included from the board-specific
-u-boot.dtsi files, similar to how rk3399 does this.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
arch/arm/dts/rk3368-geekbox-u-boot.dtsi | 2 +
arch/arm/dts/rk3368-lion-u-boot.dtsi | 2 +
arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 3 +
arch/arm/dts/rk3368-sheep-u-boot.dtsi | 2 +
arch/arm/dts/rk3368-u-boot.dtsi | 27 ++
arch/arm/dts/rk3368.dtsi | 578 ++++++++++++++----------
6 files changed, 383 insertions(+), 231 deletions(-)
create mode 100644 arch/arm/dts/rk3368-u-boot.dtsi
diff --git a/arch/arm/dts/rk3368-geekbox-u-boot.dtsi b/arch/arm/dts/rk3368-geekbox-u-boot.dtsi
index 30ea9e433a..0b724fa45f 100644
--- a/arch/arm/dts/rk3368-geekbox-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-geekbox-u-boot.dtsi
@@ -3,6 +3,8 @@
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
+#include "rk3368-u-boot.dtsi"
+
&pinctrl {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi
index 6d54214de9..9bd6352755 100644
--- a/arch/arm/dts/rk3368-lion-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi
@@ -3,6 +3,8 @@
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
+#include "rk3368-u-boot.dtsi"
+
/ {
config {
u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
index 936ce55727..264fb7adf0 100644
--- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
@@ -2,6 +2,9 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
+
+#include "rk3368-u-boot.dtsi"
+
/ {
chosen {
u-boot,spl-boot-order = &emmc;
diff --git a/arch/arm/dts/rk3368-sheep-u-boot.dtsi b/arch/arm/dts/rk3368-sheep-u-boot.dtsi
index 30ea9e433a..0b724fa45f 100644
--- a/arch/arm/dts/rk3368-sheep-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-sheep-u-boot.dtsi
@@ -3,6 +3,8 @@
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
+#include "rk3368-u-boot.dtsi"
+
&pinctrl {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3368-u-boot.dtsi b/arch/arm/dts/rk3368-u-boot.dtsi
new file mode 100644
index 0000000000..2767c2678d
--- /dev/null
+++ b/arch/arm/dts/rk3368-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include <dt-bindings/memory/rk3368-dmc.h>
+
+/ {
+ dmc: dmc at ff610000 {
+ compatible = "rockchip,rk3368-dmc", "syscon";
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ rockchip,msch = <&service_msch>;
+ reg = <0 0xff610000 0 0x400
+ 0 0xff620000 0 0x400>;
+ };
+
+ service_msch: syscon at ffac0000 {
+ compatible = "rockchip,rk3368-msch", "syscon";
+ reg = <0x0 0xffac0000 0x0 0x2000>;
+ };
+
+ sgrf: syscon at ff740000 {
+ compatible = "rockchip,rk3368-sgrf", "syscon";
+ reg = <0x0 0xff740000 0x0 0x1000>;
+ };
+};
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index b4f4f6139d..cd2c322071 100644
--- a/arch/arm/dts/rk3368.dtsi
+++ b/arch/arm/dts/rk3368.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/rk3368-cru.h>
@@ -45,8 +8,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/memory/rk3368-dmc.h>
/ {
compatible = "rockchip,rk3368";
@@ -108,84 +71,99 @@
};
};
- idle-states {
- entry-method = "psci";
-
- cpu_sleep: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x1010000>;
- entry-latency-us = <0x3fffffff>;
- exit-latency-us = <0x40000000>;
- min-residency-us = <0xffffffff>;
- };
- };
-
cpu_l0: cpu at 0 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
-
#cooling-cells = <2>; /* min followed by max */
};
cpu_l1: cpu at 1 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_l2: cpu at 2 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_l3: cpu at 3 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_b0: cpu at 100 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
-
#cooling-cells = <2>; /* min followed by max */
};
cpu_b1: cpu at 101 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_b2: cpu at 102 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_b3: cpu at 103 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
+ amba: bus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dmac_peri: dma-controller at ff250000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff250000 0x0 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC_PERI>;
+ clock-names = "apb_pclk";
+ };
+
+ dmac_bus: dma-controller at ff600000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff600000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC_BUS>;
+ clock-names = "apb_pclk";
};
};
@@ -228,54 +206,45 @@
#clock-cells = <0>;
};
- dmc: dmc at ff610000 {
- compatible = "rockchip,rk3368-dmc", "syscon";
- rockchip,cru = <&cru>;
- rockchip,grf = <&grf>;
- rockchip,msch = <&service_msch>;
- reg = <0 0xff610000 0 0x400
- 0 0xff620000 0 0x400>;
- };
-
- service_msch: syscon at ffac0000 {
- compatible = "rockchip,rk3368-msch", "syscon";
- reg = <0x0 0xffac0000 0x0 0x2000>;
- status = "okay";
- };
-
- sdmmc: dwmmc at ff0c0000 {
+ sdmmc: mmc at ff0c0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_MMC0>;
+ reset-names = "reset";
status = "disabled";
};
- sdio0: dwmmc at ff0d0000 {
+ sdio0: mmc at ff0d0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0d0000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_SDIO0>;
+ reset-names = "reset";
status = "disabled";
};
- emmc: dwmmc at ff0f0000 {
+ emmc: mmc at ff0f0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0f0000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
status = "disabled";
};
@@ -286,6 +255,8 @@
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
status = "disabled";
};
@@ -328,16 +299,16 @@
status = "disabled";
};
- i2c1: i2c at ff140000 {
+ i2c2: i2c at ff140000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff140000 0x0 0x1000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
- clocks = <&cru PCLK_I2C1>;
+ clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
- pinctrl-0 = <&i2c1_xfer>;
+ pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
@@ -389,8 +360,6 @@
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer>;
status = "disabled";
};
@@ -403,8 +372,6 @@
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-1 = <&uart0_xfer>;
status = "disabled";
};
@@ -417,8 +384,6 @@
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_xfer>;
status = "disabled";
};
@@ -431,8 +396,6 @@
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_xfer>;
status = "disabled";
};
@@ -465,12 +428,18 @@
map0 {
trip = <&cpu_alert0>;
cooling-device =
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
- <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -498,7 +467,10 @@
map0 {
trip = <&gpu_alert0>;
cooling-device =
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -513,9 +485,9 @@
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
+ pinctrl-2 = <&otp_pin>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -543,7 +515,6 @@
reg = <0x0 0xff500000 0x0 0x100>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>;
- clock-names = "usbhost";
status = "disabled";
};
@@ -558,7 +529,6 @@
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
- g-use-dma;
status = "disabled";
};
@@ -575,16 +545,16 @@
status = "disabled";
};
- i2c2: i2c at ff660000 {
+ i2c1: i2c at ff660000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff660000 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
- clocks = <&cru PCLK_I2C2>;
+ clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
- pinctrl-0 = <&i2c2_xfer>;
+ pinctrl-0 = <&i2c1_xfer>;
status = "disabled";
};
@@ -633,7 +603,6 @@
uart2: serial at ff690000 {
compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
reg = <0x0 0xff690000 0x0 0x100>;
- clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -654,16 +623,26 @@
clocks = <&cru PCLK_MAILBOX>;
clock-names = "pclk_mailbox";
#mbox-cells = <1>;
+ status = "disabled";
};
pmugrf: syscon at ff738000 {
- compatible = "rockchip,rk3368-pmugrf", "syscon";
+ compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff738000 0x0 0x1000>;
- };
- sgrf: syscon at ff740000 {
- compatible = "rockchip,rk3368-sgrf", "syscon";
- reg = <0x0 0xff740000 0x0 0x1000>;
+ pmu_io_domains: io-domains {
+ compatible = "rockchip,rk3368-pmu-io-voltage-domain";
+ status = "disabled";
+ };
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x200>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ };
};
cru: clock-controller at ff760000 {
@@ -675,8 +654,13 @@
};
grf: syscon at ff770000 {
- compatible = "rockchip,rk3368-grf", "syscon";
+ compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x1000>;
+
+ io_domains: io-domains {
+ compatible = "rockchip,rk3368-io-voltage-domain";
+ status = "disabled";
+ };
};
wdt: watchdog at ff800000 {
@@ -693,6 +677,118 @@
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
};
+ spdif: spdif at ff880000 {
+ compatible = "rockchip,rk3368-spdif";
+ reg = <0x0 0xff880000 0x0 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac_bus 3>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx>;
+ status = "disabled";
+ };
+
+ i2s_2ch: i2s-2ch at ff890000 {
+ compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff890000 0x0 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
+ dmas = <&dmac_bus 6>, <&dmac_bus 7>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2s_8ch: i2s-8ch at ff898000 {
+ compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff898000 0x0 0x1000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
+ dmas = <&dmac_bus 0>, <&dmac_bus 1>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_8ch_bus>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu at ff900800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff900800 0x0 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep_mmu";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ isp_mmu: iommu at ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>,
+ <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_mmu";
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
+ vop_mmu: iommu at ff930300 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff930300 0x0 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ hevc_mmu: iommu at ff9a0440 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0440 0x0 0x40>,
+ <0x0 0xff9a0480 0x0 0x40>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hevc_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vpu_mmu: iommu at ff9a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0800 0x0 0x100>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu_mmu", "vdpu_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ efuse256: efuse at ffb00000 {
+ compatible = "rockchip,rk3368-efuse";
+ reg = <0x0 0xffb00000 0x0 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE256>;
+ clock-names = "pclk_efuse";
+
+ cpu_leakage: cpu-leakage at 17 {
+ reg = <0x17 0x1>;
+ };
+ temp_adjust: temp-adjust at 1f {
+ reg = <0x1f 0x1>;
+ };
+ };
+
gic: interrupt-controller at ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -700,7 +796,7 @@
#address-cells = <0>;
reg = <0x0 0xffb71000 0x0 0x1000>,
- <0x0 0xffb72000 0x0 0x1000>,
+ <0x0 0xffb72000 0x0 0x2000>,
<0x0 0xffb74000 0x0 0x2000>,
<0x0 0xffb76000 0x0 0x2000>;
interrupts = <GIC_PPI 9
@@ -786,325 +882,345 @@
emmc {
emmc_clk: emmc-clk {
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
- rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
};
emmc_pwr: emmc-pwr {
- rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
};
emmc_bus1: emmc-bus1 {
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
};
emmc_bus4: emmc-bus4 {
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
- <1 19 RK_FUNC_2 &pcfg_pull_up>,
- <1 20 RK_FUNC_2 &pcfg_pull_up>,
- <1 21 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
+ <1 RK_PC3 2 &pcfg_pull_up>,
+ <1 RK_PC4 2 &pcfg_pull_up>,
+ <1 RK_PC5 2 &pcfg_pull_up>;
};
emmc_bus8: emmc-bus8 {
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
- <1 19 RK_FUNC_2 &pcfg_pull_up>,
- <1 20 RK_FUNC_2 &pcfg_pull_up>,
- <1 21 RK_FUNC_2 &pcfg_pull_up>,
- <1 22 RK_FUNC_2 &pcfg_pull_up>,
- <1 23 RK_FUNC_2 &pcfg_pull_up>,
- <1 24 RK_FUNC_2 &pcfg_pull_up>,
- <1 25 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
+ <1 RK_PC3 2 &pcfg_pull_up>,
+ <1 RK_PC4 2 &pcfg_pull_up>,
+ <1 RK_PC5 2 &pcfg_pull_up>,
+ <1 RK_PC6 2 &pcfg_pull_up>,
+ <1 RK_PC7 2 &pcfg_pull_up>,
+ <1 RK_PD0 2 &pcfg_pull_up>,
+ <1 RK_PD1 2 &pcfg_pull_up>;
};
};
gmac {
rgmii_pins: rgmii-pins {
- rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
- <3 24 RK_FUNC_1 &pcfg_pull_none>,
- <3 19 RK_FUNC_1 &pcfg_pull_none>,
- <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 15 RK_FUNC_1 &pcfg_pull_none>,
- <3 16 RK_FUNC_1 &pcfg_pull_none>,
- <3 17 RK_FUNC_1 &pcfg_pull_none>,
- <3 18 RK_FUNC_1 &pcfg_pull_none>,
- <3 25 RK_FUNC_1 &pcfg_pull_none>,
- <3 20 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ <3 RK_PC3 1 &pcfg_pull_none>,
+ <3 RK_PB0 1 &pcfg_pull_none_12ma>,
+ <3 RK_PB1 1 &pcfg_pull_none_12ma>,
+ <3 RK_PB2 1 &pcfg_pull_none_12ma>,
+ <3 RK_PB6 1 &pcfg_pull_none_12ma>,
+ <3 RK_PD4 1 &pcfg_pull_none_12ma>,
+ <3 RK_PB5 1 &pcfg_pull_none_12ma>,
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ <3 RK_PC2 1 &pcfg_pull_none>,
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ <3 RK_PC4 1 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
- rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
- <3 24 RK_FUNC_1 &pcfg_pull_none>,
- <3 19 RK_FUNC_1 &pcfg_pull_none>,
- <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 15 RK_FUNC_1 &pcfg_pull_none>,
- <3 16 RK_FUNC_1 &pcfg_pull_none>,
- <3 20 RK_FUNC_1 &pcfg_pull_none>,
- <3 21 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ <3 RK_PC3 1 &pcfg_pull_none>,
+ <3 RK_PB0 1 &pcfg_pull_none_12ma>,
+ <3 RK_PB1 1 &pcfg_pull_none_12ma>,
+ <3 RK_PB5 1 &pcfg_pull_none_12ma>,
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ <3 RK_PC5 1 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
- rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
- <0 7 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
+ <0 RK_PA7 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
- rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
- <2 22 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
+ <2 RK_PC6 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
- rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
- <3 31 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
+ <3 RK_PD7 2 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
- rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
- <1 17 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
+ <1 RK_PC1 1 &pcfg_pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
- rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
- <3 25 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
+ <3 RK_PD1 2 &pcfg_pull_none>;
};
};
i2c5 {
i2c5_xfer: i2c5-xfer {
- rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
- <3 27 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
+ <3 RK_PD3 2 &pcfg_pull_none>;
+ };
+ };
+
+ i2s {
+ i2s_8ch_bus: i2s-8ch-bus {
+ rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
+ <2 RK_PB5 1 &pcfg_pull_none>,
+ <2 RK_PB6 1 &pcfg_pull_none>,
+ <2 RK_PB7 1 &pcfg_pull_none>,
+ <2 RK_PC0 1 &pcfg_pull_none>,
+ <2 RK_PC1 1 &pcfg_pull_none>,
+ <2 RK_PC2 1 &pcfg_pull_none>,
+ <2 RK_PC3 1 &pcfg_pull_none>,
+ <2 RK_PC4 1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
- rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
- rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
- rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
};
};
sdio0 {
sdio0_bus1: sdio0-bus1 {
- rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
};
sdio0_bus4: sdio0-bus4 {
- rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
- <2 29 RK_FUNC_1 &pcfg_pull_up>,
- <2 30 RK_FUNC_1 &pcfg_pull_up>,
- <2 31 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
+ <2 RK_PD5 1 &pcfg_pull_up>,
+ <2 RK_PD6 1 &pcfg_pull_up>,
+ <2 RK_PD7 1 &pcfg_pull_up>;
};
sdio0_cmd: sdio0-cmd {
- rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
};
sdio0_clk: sdio0-clk {
- rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
};
sdio0_cd: sdio0-cd {
- rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
};
sdio0_wp: sdio0-wp {
- rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
};
sdio0_pwr: sdio0-pwr {
- rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
};
sdio0_bkpwr: sdio0-bkpwr {
- rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
};
sdio0_int: sdio0-int {
- rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_clk: sdmmc-clk {
- rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
};
sdmmc_cd: sdmmc-cd {
- rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
};
sdmmc_bus1: sdmmc-bus1 {
- rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
};
sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
- <2 6 RK_FUNC_1 &pcfg_pull_up>,
- <2 7 RK_FUNC_1 &pcfg_pull_up>,
- <2 8 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
+ <2 RK_PA6 1 &pcfg_pull_up>,
+ <2 RK_PA7 1 &pcfg_pull_up>,
+ <2 RK_PB0 1 &pcfg_pull_up>;
+ };
+ };
+
+ spdif {
+ spdif_tx: spdif-tx {
+ rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
};
};
spi0 {
spi0_clk: spi0-clk {
- rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
- rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
- rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
- rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
- rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
};
};
spi1 {
spi1_clk: spi1-clk {
- rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
- rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
};
spi1_cs1: spi1-cs1 {
- rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
- rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
- rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
};
};
spi2 {
spi2_clk: spi2-clk {
- rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
};
spi2_cs0: spi2-cs0 {
- rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
};
spi2_rx: spi2-rx {
- rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
};
spi2_tx: spi2-tx {
- rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
};
};
tsadc {
- otp_gpio: otp-gpio {
- rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ otp_pin: otp-pin {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
- rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
- rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
- <2 25 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
+ <2 RK_PD1 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
- rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
- rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
- rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
- <0 21 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
+ <0 RK_PC5 3 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
- rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
- rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
- <2 5 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
+ <2 RK_PA5 2 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
uart3 {
uart3_xfer: uart3-xfer {
- rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
- <3 30 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
+ <3 RK_PD6 3 &pcfg_pull_none>;
};
uart3_cts: uart3-cts {
- rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
};
uart3_rts: uart3-rts {
- rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
};
};
uart4 {
uart4_xfer: uart4-xfer {
- rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
- <0 26 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
+ <0 RK_PD2 3 &pcfg_pull_none>;
};
uart4_cts: uart4-cts {
- rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
};
uart4_rts: uart4-rts {
- rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
};
};
};
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 7/8] rockchip: rk3368: sync down rk3368-lion board devicetree from Linux
2021-02-09 13:47 [PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again Heiko Stuebner
` (5 preceding siblings ...)
2021-02-09 13:47 ` [PATCH 6/8] rockchip: rk3368: sync main rk3368 dtsi " Heiko Stuebner
@ 2021-02-09 13:47 ` Heiko Stuebner
2021-02-09 13:47 ` [PATCH 8/8] rockchip: lion: update board defconfig Heiko Stuebner
7 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2021-02-09 13:47 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
This brings the actual rk3368-lion devicetree files from Linux 5.10
instead of using something separate.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
arch/arm/dts/Makefile | 2 +-
...ot.dtsi => rk3368-lion-haikou-u-boot.dtsi} | 4 +
arch/arm/dts/rk3368-lion-haikou.dts | 140 +++++++++
.../dts/{rk3368-lion.dts => rk3368-lion.dtsi} | 271 +++++++++++++-----
configs/lion-rk3368_defconfig | 2 +
5 files changed, 351 insertions(+), 68 deletions(-)
rename arch/arm/dts/{rk3368-lion-u-boot.dtsi => rk3368-lion-haikou-u-boot.dtsi} (98%)
create mode 100644 arch/arm/dts/rk3368-lion-haikou.dts
rename arch/arm/dts/{rk3368-lion.dts => rk3368-lion.dtsi} (54%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fd47e408f8..fa2e8b5ef7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -115,7 +115,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
- rk3368-lion.dtb \
+ rk3368-lion-haikou.dtb \
rk3368-sheep.dtb \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-haikou-u-boot.dtsi
similarity index 98%
rename from arch/arm/dts/rk3368-lion-u-boot.dtsi
rename to arch/arm/dts/rk3368-lion-haikou-u-boot.dtsi
index 9bd6352755..7826d1e70b 100644
--- a/arch/arm/dts/rk3368-lion-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-lion-haikou-u-boot.dtsi
@@ -38,6 +38,10 @@
};
};
+&gpio2 {
+ u-boot,dm-pre-reloc;
+};
+
&pinctrl {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3368-lion-haikou.dts b/arch/arm/dts/rk3368-lion-haikou.dts
new file mode 100644
index 0000000000..7fcb1eacea
--- /dev/null
+++ b/arch/arm/dts/rk3368-lion-haikou.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include "rk3368-lion.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3368-uQ7 Baseboard";
+ compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ i2cmux2 {
+ i2c at 0 {
+ eeprom: eeprom at 50 {
+ compatible = "atmel,24c01";
+ pagesize = <8>;
+ reg = <0x50>;
+ };
+ };
+ };
+
+ leds {
+ pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>;
+
+ sd_card_led: led-3 {
+ label = "sd_card_led";
+ gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_baseboard: vcc3v3-baseboard {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_baseboard";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <25000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ rockchip,default-sample-phase = <90>;
+ vmmc-supply = <&vcc3v3_baseboard>;
+ status = "okay";
+};
+
+&spi2 {
+ cs-gpios = <0>, <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+};
+
+&uart1 {
+ /* alternate function of GPIO5/6 */
+ status = "disabled";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&haikou_pin_hog>;
+
+ hog {
+ haikou_pin_hog: haikou-pin-hog {
+ rockchip,pins =
+ /* LID_BTN */
+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* BATLOW# */
+ <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* SLP_BTN# */
+ <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* BIOS_DISABLE# */
+ <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ sd_card_led_pin: sd-card-led-pin {
+ rockchip,pins =
+ <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_cd_pin: sdmmc-cd-pin {
+ rockchip,pins =
+ <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb_otg {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins =
+ <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3368-lion.dts b/arch/arm/dts/rk3368-lion.dtsi
similarity index 54%
rename from arch/arm/dts/rk3368-lion.dts
rename to arch/arm/dts/rk3368-lion.dtsi
index 2814542083..532e6a6828 100644
--- a/arch/arm/dts/rk3368-lion.dts
+++ b/arch/arm/dts/rk3368-lion.dtsi
@@ -1,25 +1,14 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH
*/
/dts-v1/;
#include "rk3368.dtsi"
-#include "rk3368-lion-u-boot.dtsi"
-#include <dt-bindings/input/input.h>
/ {
- model = "Theobroma Systems RK3368-uQ7 SoM";
- compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368";
-
- aliases {
- mmc0 = &emmc;
- mmc1 = &sdmmc;
- };
-
- memory at 0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
+ chosen {
+ stdout-path = "serial0:115200n8";
};
ext_gmac: gmac-clk {
@@ -29,6 +18,80 @@
#clock-cells = <0>;
};
+ i2cmux1 {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c1>;
+ mux-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+
+ /* Q7_GPO_I2C */
+ i2c at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* Q7_SMB */
+ i2c at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ i2cmux2 {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c2>;
+ mux-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+
+ /* Q7_LVDS_BLC_I2C */
+ i2c at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan: fan at 18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ #cooling-cells = <2>;
+ };
+
+ rtc_twi: rtc at 6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+ };
+
+ /* Q7_GP2_I2C */
+ i2c at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&module_led_pins>;
+
+ module_led1: led-1 {
+ label = "module_led1";
+ gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+
+ module_led2: led-2 {
+ label = "module_led2";
+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@@ -39,43 +102,81 @@
};
};
-&uart0 {
- status = "okay";
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu>;
};
&emmc {
- status = "okay";
bus-width = <8>;
- cap-mmc-highspeed;
clock-frequency = <150000000>;
- disable-wp;
- keep-power-in-suspend;
+ mmc-hs200-1_8v;
non-removable;
- num-slots = <1>;
vmmc-supply = <&vcc33_io>;
vqmmc-supply = <&vcc18_io>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
-};
-
-&sdmmc {
status = "okay";
};
&gmac {
- status = "okay";
- phy-supply = <&vcc33_io>;
- phy-mode = "rgmii";
- clock_in_out = "input";
- snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <2 10000 50000>;
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ phy-handle = <&phy0>;
+ phy-supply = <&vcc33_io>;
+ phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
tx_delay = <0x10>;
rx_delay = <0x10>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Microsemi VSC8531-02 */
+ phy0: phy at 0 {
+ compatible = "ethernet-phy-id0007.0570";
+ reg = <0>;
+ vsc8531,clk-out-frequency = <125000000>;
+ vsc8531,edge-slowdown = <7>;
+ vsc8531,led-0-mode = <1>;
+ vsc8531,led-1-mode = <2>;
+ };
+ };
};
&i2c0 {
@@ -85,7 +186,11 @@
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio0>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>, <&pmic_sleep>;
rockchip,system-power-controller;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
@@ -98,97 +203,129 @@
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc_sys>;
- clock-output-names = "xin32k", "rk808-clkout2";
- #clock-cells = <1>;
regulators {
vdd_cpu: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vdd_cpu";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
- regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
};
vdd_log: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vdd_log";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
- regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
};
vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
- regulator-name = "vcc_ddr";
};
vcc33_io: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc33_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc33_io";
+ regulator-always-on;
+ regulator-boot-on;
};
vcc33_video: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc33_video";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc33_video";
+ regulator-always-on;
+ regulator-boot-on;
};
vdd10_pll: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vdd10_pll";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
- regulator-name = "vdd10_pll";
+ regulator-always-on;
+ regulator-boot-on;
};
vcc18_io: LDO_REG4 {
- regulator-boot-on;
+ regulator-name = "vcc18_io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc18_io";
+ regulator-boot-on;
};
vdd10_video: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vdd10_video";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
- regulator-name = "vdd10_video";
+ regulator-always-on;
+ regulator-boot-on;
};
vcc18_video: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc18_video";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc18_video";
+ regulator-always-on;
+ regulator-boot-on;
};
};
};
};
-&uart0 {
+&i2c1 {
status = "okay";
};
-&spi1 {
+&i2c2 {
status = "okay";
+};
- #address-cells = <1>;
- #size-cells = <0>;
+&pinctrl {
+ leds {
+ module_led_pins: module-led-pins {
+ rockchip,pins =
+ <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
- spiflash: w25q32dw at 0 {
+ pmic_sleep: pmic-sleep {
+ rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+
+ norflash: flash at 0 {
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <49500000>;
- spi-cpol;
- spi-cpha;
+ spi-max-frequency = <50000000>;
};
};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index b409715060..f547875dee 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -32,6 +32,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_ATF=y
CONFIG_TPL=y
@@ -44,6 +45,7 @@ CONFIG_CMD_MTDPARTS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion-haikou"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 8/8] rockchip: lion: update board defconfig
2021-02-09 13:47 [PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again Heiko Stuebner
` (6 preceding siblings ...)
2021-02-09 13:47 ` [PATCH 7/8] rockchip: rk3368: sync down rk3368-lion board devicetree " Heiko Stuebner
@ 2021-02-09 13:47 ` Heiko Stuebner
7 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2021-02-09 13:47 UTC (permalink / raw)
To: u-boot
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Adds the needed target option and drivers needed for correct
bringup.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
configs/lion-rk3368_defconfig | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index f547875dee..6d6b73d977 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -9,6 +9,7 @@ CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_LION_RK3368=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xFF180000
CONFIG_DEBUG_UART_CLOCK=24000000
@@ -39,6 +40,8 @@ CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_MTDPARTS=y
@@ -62,14 +65,15 @@ CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_TPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_MSCC=y
CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_GMAC_ROCKCHIP=y
@@ -78,6 +82,7 @@ CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
@@ -88,6 +93,13 @@ CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-02-09 13:47 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-09 13:47 [PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again Heiko Stuebner
2021-02-09 13:47 ` [PATCH 1/8] rockchip: rk3368: adjust CONFIG_SYS_LOAD_ADDR Heiko Stuebner
2021-02-09 13:47 ` [PATCH 2/8] rockchip: rk3368: set CONFIG_SYS_BOOTM_LEN to 64MB Heiko Stuebner
2021-02-09 13:47 ` [PATCH 3/8] rockchip: rk3368: increase SYS_MALLOC_F_LEN to 0x4000 Heiko Stuebner
2021-02-09 13:47 ` [PATCH 4/8] rockchip: rk3368: move STACK_R_ADDR address and into Kconfig Heiko Stuebner
2021-02-09 13:47 ` [PATCH 5/8] rockchip: rk3368: sync clock dt-binding header from Linux Heiko Stuebner
2021-02-09 13:47 ` [PATCH 6/8] rockchip: rk3368: sync main rk3368 dtsi " Heiko Stuebner
2021-02-09 13:47 ` [PATCH 7/8] rockchip: rk3368: sync down rk3368-lion board devicetree " Heiko Stuebner
2021-02-09 13:47 ` [PATCH 8/8] rockchip: lion: update board defconfig Heiko Stuebner
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