From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3BD8C433E9 for ; Tue, 9 Feb 2021 15:54:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8DB4A64E79 for ; Tue, 9 Feb 2021 15:54:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232545AbhBIPyj (ORCPT ); Tue, 9 Feb 2021 10:54:39 -0500 Received: from mail-oi1-f169.google.com ([209.85.167.169]:33979 "EHLO mail-oi1-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232294AbhBIPyf (ORCPT ); Tue, 9 Feb 2021 10:54:35 -0500 Received: by mail-oi1-f169.google.com with SMTP id i3so9021062oif.1; Tue, 09 Feb 2021 07:54:18 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=n8RGtZJUggLSCRq7qMrNt9PC2BllhIR7lzoDCBdYMa8=; b=X6gPFBPVKVC+IFk33YKFkULffR9WSmqR73auE2ZKI8QH6Zm959B9Ah9KBPAc5HIHw2 3m0/Ch12gU1xVMZMzE2o3kXIwROg48sz+ETGpy46Fp189slQP51ws5IY8ktiFzgjQsAZ vNCq1Gk03+c9FBBjo7ukpZ+mfkJSwkCdc3kILDKmFkgLs39XquKtNYxRDF+9kTQJtqb+ XL656yjF8P0wwXddlgPsp8wJwuvaWFwiKSAzR7E0T7qBgV7l66BwZUlyq2zwRadQB2yk C+PyKYQsFktEH+afOEc9nj2jfQ3vZ63d5CKiJmovAjUuJLkR/q0CIiGktCZS5SL+ZHmu wwtA== X-Gm-Message-State: AOAM531lvt26+Kz089KuPI/czul41Qc9eXqZx1orEJDdiffEMtacr3x2 Me/K/ZO6suQ6oZgSFIAmKg== X-Google-Smtp-Source: ABdhPJymQc7IHN4pNsxzcoYtAeiTFpG1/W/MbAoJvQPnwIAXU6moHoTqEDDFHzxQJeoydepWxYwURg== X-Received: by 2002:aca:cfd0:: with SMTP id f199mr2909983oig.64.1612886032958; Tue, 09 Feb 2021 07:53:52 -0800 (PST) Received: from robh.at.kernel.org (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id c20sm4384328oiw.18.2021.02.09.07.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 07:53:51 -0800 (PST) Received: (nullmailer pid 3832812 invoked by uid 1000); Tue, 09 Feb 2021 15:53:50 -0000 Date: Tue, 9 Feb 2021 09:53:50 -0600 From: Rob Herring To: Irui Wang Cc: Alexandre Courbot , Hans Verkuil , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Matthias Brugger , Tomasz Figa , Hsin-Yi Wang , Maoguang Meng , Longfei Wang , Yunfei Dong , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, linux-mediatek@lists.infradead.org Subject: Re: [PATCH 1/3] dt-bindings: media: mtk-vcodec: Separating mtk vcodec encoder node Message-ID: <20210209155350.GA3827709@robh.at.kernel.org> References: <20210121061804.26423-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121061804.26423-1-irui.wang@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 21, 2021 at 02:18:02PM +0800, Irui Wang wrote: > Updates binding document since the avc and vp8 hardware encoder in > MT8173 are now separated. Separate "mediatek,mt8173-vcodec-enc" to > "mediatek,mt8173-vcodec-vp8-enc" and "mediatek,mt8173-vcodec-avc-enc". This is not a compatible change. You need to detail that and why that's okay (assuming it is). > > Signed-off-by: Hsin-Yi Wang > Signed-off-by: Maoguang Meng > Signed-off-by: Irui Wang > > --- > .../bindings/media/mediatek-vcodec.txt | 58 ++++++++++--------- > 1 file changed, 31 insertions(+), 27 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > index 8217424fd4bd..f85276e629bf 100644 > --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > @@ -4,7 +4,9 @@ Mediatek Video Codec is the video codec hw present in Mediatek SoCs which > supports high resolution encoding and decoding functionalities. > > Required properties: > -- compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder > +- compatible : must be one of the following string: > + "mediatek,mt8173-vcodec-vp8-enc" for mt8173 vp8 encoder. > + "mediatek,mt8173-vcodec-avc-enc" for mt8173 avc encoder. > "mediatek,mt8183-vcodec-enc" for MT8183 encoder. > "mediatek,mt8173-vcodec-dec" for MT8173 decoder. > - reg : Physical base address of the video codec registers and length of > @@ -13,10 +15,11 @@ Required properties: > - mediatek,larb : must contain the local arbiters in the current Socs. > - clocks : list of clock specifiers, corresponding to entries in > the clock-names property. > -- clock-names: encoder must contain "venc_sel_src", "venc_sel",, > - "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll", > - "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", > - "venc_lt_sel", "vdec_bus_clk_src". > +- clock-names: > + avc venc must contain "venc_sel"; > + vp8 venc must contain "venc_lt_sel"; > + decoder must contain "vcodecpll", "univpll_d2", "clk_cci400_sel", > + "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel", "vdec_bus_clk_src". > - iommus : should point to the respective IOMMU block with master port as > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > @@ -80,14 +83,10 @@ vcodec_dec: vcodec@16000000 { > assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; > }; > > - vcodec_enc: vcodec@18002000 { > - compatible = "mediatek,mt8173-vcodec-enc"; > - reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ > - <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ > - interrupts = , > - ; > - mediatek,larb = <&larb3>, > - <&larb5>; > +vcodec_enc: vcodec@18002000 { > + compatible = "mediatek,mt8173-vcodec-avc-enc"; > + reg = <0 0x18002000 0 0x1000>; > + interrupts = ; > iommus = <&iommu M4U_PORT_VENC_RCPU>, > <&iommu M4U_PORT_VENC_REC>, > <&iommu M4U_PORT_VENC_BSDMA>, > @@ -98,8 +97,20 @@ vcodec_dec: vcodec@16000000 { > <&iommu M4U_PORT_VENC_REF_LUMA>, > <&iommu M4U_PORT_VENC_REF_CHROMA>, > <&iommu M4U_PORT_VENC_NBM_RDMA>, > - <&iommu M4U_PORT_VENC_NBM_WDMA>, > - <&iommu M4U_PORT_VENC_RCPU_SET2>, > + <&iommu M4U_PORT_VENC_NBM_WDMA>; > + mediatek,larb = <&larb3>; > + mediatek,vpu = <&vpu>; > + clocks = <&topckgen CLK_TOP_VENC_SEL>; > + clock-names = "venc_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; > + }; > + > +vcodec_enc_lt: vcodec@19002000 { > + compatible = "mediatek,mt8173-vcodec-vp8-enc"; > + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ > + interrupts = ; > + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, > <&iommu M4U_PORT_VENC_REC_FRM_SET2>, > <&iommu M4U_PORT_VENC_BSDMA_SET2>, > <&iommu M4U_PORT_VENC_SV_COMA_SET2>, > @@ -108,17 +119,10 @@ vcodec_dec: vcodec@16000000 { > <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, > <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, > <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; > + mediatek,larb = <&larb5>; > mediatek,vpu = <&vpu>; > - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, > - <&topckgen CLK_TOP_VENC_SEL>, > - <&topckgen CLK_TOP_UNIVPLL1_D2>, > - <&topckgen CLK_TOP_VENC_LT_SEL>; > - clock-names = "venc_sel_src", > - "venc_sel", > - "venc_lt_sel_src", > - "venc_lt_sel"; > - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, > - <&topckgen CLK_TOP_VENC_LT_SEL>; > - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, > - <&topckgen CLK_TOP_UNIVPLL1_D2>; > + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > + clock-names = "venc_lt_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; > }; > -- > 2.18.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6E94C433E0 for ; Tue, 9 Feb 2021 15:54:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 212BE64E70 for ; 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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id c20sm4384328oiw.18.2021.02.09.07.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 07:53:51 -0800 (PST) Received: (nullmailer pid 3832812 invoked by uid 1000); Tue, 09 Feb 2021 15:53:50 -0000 Date: Tue, 9 Feb 2021 09:53:50 -0600 From: Rob Herring To: Irui Wang Subject: Re: [PATCH 1/3] dt-bindings: media: mtk-vcodec: Separating mtk vcodec encoder node Message-ID: <20210209155350.GA3827709@robh.at.kernel.org> References: <20210121061804.26423-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210121061804.26423-1-irui.wang@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210209_105354_387428_1A2952BF X-CRM114-Status: GOOD ( 19.67 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew-CT Chen , Tiffany Lin , srv_heupstream@mediatek.com, Alexandre Courbot , Tomasz Figa , Yunfei Dong , Longfei Wang , linux-kernel@vger.kernel.org, Matthias Brugger , devicetree@vger.kernel.org, Maoguang Meng , linux-mediatek@lists.infradead.org, Hsin-Yi Wang , Hans Verkuil , Mauro Carvalho Chehab , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, Jan 21, 2021 at 02:18:02PM +0800, Irui Wang wrote: > Updates binding document since the avc and vp8 hardware encoder in > MT8173 are now separated. Separate "mediatek,mt8173-vcodec-enc" to > "mediatek,mt8173-vcodec-vp8-enc" and "mediatek,mt8173-vcodec-avc-enc". This is not a compatible change. You need to detail that and why that's okay (assuming it is). > > Signed-off-by: Hsin-Yi Wang > Signed-off-by: Maoguang Meng > Signed-off-by: Irui Wang > > --- > .../bindings/media/mediatek-vcodec.txt | 58 ++++++++++--------- > 1 file changed, 31 insertions(+), 27 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > index 8217424fd4bd..f85276e629bf 100644 > --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > @@ -4,7 +4,9 @@ Mediatek Video Codec is the video codec hw present in Mediatek SoCs which > supports high resolution encoding and decoding functionalities. > > Required properties: > -- compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder > +- compatible : must be one of the following string: > + "mediatek,mt8173-vcodec-vp8-enc" for mt8173 vp8 encoder. > + "mediatek,mt8173-vcodec-avc-enc" for mt8173 avc encoder. > "mediatek,mt8183-vcodec-enc" for MT8183 encoder. > "mediatek,mt8173-vcodec-dec" for MT8173 decoder. > - reg : Physical base address of the video codec registers and length of > @@ -13,10 +15,11 @@ Required properties: > - mediatek,larb : must contain the local arbiters in the current Socs. > - clocks : list of clock specifiers, corresponding to entries in > the clock-names property. > -- clock-names: encoder must contain "venc_sel_src", "venc_sel",, > - "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll", > - "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", > - "venc_lt_sel", "vdec_bus_clk_src". > +- clock-names: > + avc venc must contain "venc_sel"; > + vp8 venc must contain "venc_lt_sel"; > + decoder must contain "vcodecpll", "univpll_d2", "clk_cci400_sel", > + "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel", "vdec_bus_clk_src". > - iommus : should point to the respective IOMMU block with master port as > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > @@ -80,14 +83,10 @@ vcodec_dec: vcodec@16000000 { > assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; > }; > > - vcodec_enc: vcodec@18002000 { > - compatible = "mediatek,mt8173-vcodec-enc"; > - reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ > - <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ > - interrupts = , > - ; > - mediatek,larb = <&larb3>, > - <&larb5>; > +vcodec_enc: vcodec@18002000 { > + compatible = "mediatek,mt8173-vcodec-avc-enc"; > + reg = <0 0x18002000 0 0x1000>; > + interrupts = ; > iommus = <&iommu M4U_PORT_VENC_RCPU>, > <&iommu M4U_PORT_VENC_REC>, > <&iommu M4U_PORT_VENC_BSDMA>, > @@ -98,8 +97,20 @@ vcodec_dec: vcodec@16000000 { > <&iommu M4U_PORT_VENC_REF_LUMA>, > <&iommu M4U_PORT_VENC_REF_CHROMA>, > <&iommu M4U_PORT_VENC_NBM_RDMA>, > - <&iommu M4U_PORT_VENC_NBM_WDMA>, > - <&iommu M4U_PORT_VENC_RCPU_SET2>, > + <&iommu M4U_PORT_VENC_NBM_WDMA>; > + mediatek,larb = <&larb3>; > + mediatek,vpu = <&vpu>; > + clocks = <&topckgen CLK_TOP_VENC_SEL>; > + clock-names = "venc_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; > + }; > + > +vcodec_enc_lt: vcodec@19002000 { > + compatible = "mediatek,mt8173-vcodec-vp8-enc"; > + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ > + interrupts = ; > + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, > <&iommu M4U_PORT_VENC_REC_FRM_SET2>, > <&iommu M4U_PORT_VENC_BSDMA_SET2>, > <&iommu M4U_PORT_VENC_SV_COMA_SET2>, > @@ -108,17 +119,10 @@ vcodec_dec: vcodec@16000000 { > <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, > <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, > <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; > + mediatek,larb = <&larb5>; > mediatek,vpu = <&vpu>; > - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, > - <&topckgen CLK_TOP_VENC_SEL>, > - <&topckgen CLK_TOP_UNIVPLL1_D2>, > - <&topckgen CLK_TOP_VENC_LT_SEL>; > - clock-names = "venc_sel_src", > - "venc_sel", > - "venc_lt_sel_src", > - "venc_lt_sel"; > - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, > - <&topckgen CLK_TOP_VENC_LT_SEL>; > - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, > - <&topckgen CLK_TOP_UNIVPLL1_D2>; > + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > + clock-names = "venc_lt_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; > }; > -- > 2.18.0 > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1A1CC433E0 for ; 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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id c20sm4384328oiw.18.2021.02.09.07.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 07:53:51 -0800 (PST) Received: (nullmailer pid 3832812 invoked by uid 1000); Tue, 09 Feb 2021 15:53:50 -0000 Date: Tue, 9 Feb 2021 09:53:50 -0600 From: Rob Herring To: Irui Wang Subject: Re: [PATCH 1/3] dt-bindings: media: mtk-vcodec: Separating mtk vcodec encoder node Message-ID: <20210209155350.GA3827709@robh.at.kernel.org> References: <20210121061804.26423-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210121061804.26423-1-irui.wang@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210209_105354_387428_1A2952BF X-CRM114-Status: GOOD ( 19.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew-CT Chen , Tiffany Lin , srv_heupstream@mediatek.com, Alexandre Courbot , Tomasz Figa , Yunfei Dong , Longfei Wang , linux-kernel@vger.kernel.org, Matthias Brugger , devicetree@vger.kernel.org, Maoguang Meng , linux-mediatek@lists.infradead.org, Hsin-Yi Wang , Hans Verkuil , Mauro Carvalho Chehab , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 21, 2021 at 02:18:02PM +0800, Irui Wang wrote: > Updates binding document since the avc and vp8 hardware encoder in > MT8173 are now separated. Separate "mediatek,mt8173-vcodec-enc" to > "mediatek,mt8173-vcodec-vp8-enc" and "mediatek,mt8173-vcodec-avc-enc". This is not a compatible change. You need to detail that and why that's okay (assuming it is). > > Signed-off-by: Hsin-Yi Wang > Signed-off-by: Maoguang Meng > Signed-off-by: Irui Wang > > --- > .../bindings/media/mediatek-vcodec.txt | 58 ++++++++++--------- > 1 file changed, 31 insertions(+), 27 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > index 8217424fd4bd..f85276e629bf 100644 > --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > @@ -4,7 +4,9 @@ Mediatek Video Codec is the video codec hw present in Mediatek SoCs which > supports high resolution encoding and decoding functionalities. > > Required properties: > -- compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder > +- compatible : must be one of the following string: > + "mediatek,mt8173-vcodec-vp8-enc" for mt8173 vp8 encoder. > + "mediatek,mt8173-vcodec-avc-enc" for mt8173 avc encoder. > "mediatek,mt8183-vcodec-enc" for MT8183 encoder. > "mediatek,mt8173-vcodec-dec" for MT8173 decoder. > - reg : Physical base address of the video codec registers and length of > @@ -13,10 +15,11 @@ Required properties: > - mediatek,larb : must contain the local arbiters in the current Socs. > - clocks : list of clock specifiers, corresponding to entries in > the clock-names property. > -- clock-names: encoder must contain "venc_sel_src", "venc_sel",, > - "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll", > - "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", > - "venc_lt_sel", "vdec_bus_clk_src". > +- clock-names: > + avc venc must contain "venc_sel"; > + vp8 venc must contain "venc_lt_sel"; > + decoder must contain "vcodecpll", "univpll_d2", "clk_cci400_sel", > + "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel", "vdec_bus_clk_src". > - iommus : should point to the respective IOMMU block with master port as > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > @@ -80,14 +83,10 @@ vcodec_dec: vcodec@16000000 { > assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; > }; > > - vcodec_enc: vcodec@18002000 { > - compatible = "mediatek,mt8173-vcodec-enc"; > - reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ > - <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ > - interrupts = , > - ; > - mediatek,larb = <&larb3>, > - <&larb5>; > +vcodec_enc: vcodec@18002000 { > + compatible = "mediatek,mt8173-vcodec-avc-enc"; > + reg = <0 0x18002000 0 0x1000>; > + interrupts = ; > iommus = <&iommu M4U_PORT_VENC_RCPU>, > <&iommu M4U_PORT_VENC_REC>, > <&iommu M4U_PORT_VENC_BSDMA>, > @@ -98,8 +97,20 @@ vcodec_dec: vcodec@16000000 { > <&iommu M4U_PORT_VENC_REF_LUMA>, > <&iommu M4U_PORT_VENC_REF_CHROMA>, > <&iommu M4U_PORT_VENC_NBM_RDMA>, > - <&iommu M4U_PORT_VENC_NBM_WDMA>, > - <&iommu M4U_PORT_VENC_RCPU_SET2>, > + <&iommu M4U_PORT_VENC_NBM_WDMA>; > + mediatek,larb = <&larb3>; > + mediatek,vpu = <&vpu>; > + clocks = <&topckgen CLK_TOP_VENC_SEL>; > + clock-names = "venc_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; > + }; > + > +vcodec_enc_lt: vcodec@19002000 { > + compatible = "mediatek,mt8173-vcodec-vp8-enc"; > + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ > + interrupts = ; > + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, > <&iommu M4U_PORT_VENC_REC_FRM_SET2>, > <&iommu M4U_PORT_VENC_BSDMA_SET2>, > <&iommu M4U_PORT_VENC_SV_COMA_SET2>, > @@ -108,17 +119,10 @@ vcodec_dec: vcodec@16000000 { > <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, > <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, > <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; > + mediatek,larb = <&larb5>; > mediatek,vpu = <&vpu>; > - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, > - <&topckgen CLK_TOP_VENC_SEL>, > - <&topckgen CLK_TOP_UNIVPLL1_D2>, > - <&topckgen CLK_TOP_VENC_LT_SEL>; > - clock-names = "venc_sel_src", > - "venc_sel", > - "venc_lt_sel_src", > - "venc_lt_sel"; > - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, > - <&topckgen CLK_TOP_VENC_LT_SEL>; > - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, > - <&topckgen CLK_TOP_UNIVPLL1_D2>; > + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > + clock-names = "venc_lt_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; > }; > -- > 2.18.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel