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From: Ard Biesheuvel <ardb@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: Nicolas Pitre <nico@fluxnic.net>, Marc Zyngier <maz@kernel.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Russell King <linux@armlinux.org.uk>,
	kernel-team@android.com, Ard Biesheuvel <ardb@kernel.org>
Subject: [PATCH v2 1/3] ARM: cache-v7: add missing ISB after cache level selection
Date: Wed, 10 Feb 2021 19:55:30 +0100	[thread overview]
Message-ID: <20210210185532.8425-2-ardb@kernel.org> (raw)
In-Reply-To: <20210210185532.8425-1-ardb@kernel.org>

A write to CCSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 arch/arm/mm/cache-v7.S | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index dc8f152f3556..307f381eee71 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -38,9 +38,10 @@ icache_size:
  * procedures.
  */
 ENTRY(v7_invalidate_l1)
-       mov     r0, #0
-       mcr     p15, 2, r0, c0, c0, 0
-       mrc     p15, 1, r0, c0, c0, 0
+	mov	r0, #0
+	mcr	p15, 2, r0, c0, c0, 0	@ select L1 data cache in CSSELR
+	isb
+	mrc	p15, 1, r0, c0, c0, 0	@ read cache geometry from CCSIDR
 
        movw    r1, #0x7fff
        and     r2, r1, r0, lsr #13
-- 
2.30.0


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  reply	other threads:[~2021-02-10 18:56 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-10 18:55 [PATCH v2 0/3] ARM: v7: get rid of boot time mini stack Ard Biesheuvel
2021-02-10 18:55 ` Ard Biesheuvel [this message]
2021-02-10 18:55 ` [PATCH v2 2/3] ARM: cache-v7: refactor v7_invalidate_l1 to avoid clobbering r5/r6 Ard Biesheuvel
2021-02-10 18:55 ` [PATCH v2 3/3] ARM: cache-v7: get rid of mini-stack Ard Biesheuvel
2021-03-01 15:53   ` Russell King - ARM Linux admin
2021-03-01 16:10     ` Ard Biesheuvel
2021-03-01 14:38 ` [PATCH v2 0/3] ARM: v7: get rid of boot time mini stack Linus Walleij

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