From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94D50C433E6 for ; Wed, 10 Feb 2021 18:57:00 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 53BED60C41 for ; Wed, 10 Feb 2021 18:57:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 53BED60C41 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IhcfEWJNu1z6OnpiCcOofvsJnRka9RyytKJokHFKG70=; b=ZIF8YnYOuqsAJ3Mde7IqfhSaN UEqXu+5s2vOJ2M2v+QsJwzHBNGTjq2uxYVb0A/jB071SsVJ1zt1N76oDUi/l1TrSMCmGvl5jxVuUz cZNv7OCB6/+YP7jguTef3jA7P7FGtugJpPDbj8CnFbQEvTP7N2hf4hjxtZcxk2QUjaX3txUsN1dZ4 lRvT6Eax9/YfYiReSvNFi6cq30qRsXty+RgpiCioHHkXoEzoO2FdQf9+9ZNu23iZV1hgF+RF2XCP+ khJqSWzU53Iu03L+DDq9/MwCfJP++27c2maFe+mIhxEz2ELp3XXvZr8Otcf11Y0pR5MoP35doIaBH z+qtsym6A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9uea-0001nJ-Ed; Wed, 10 Feb 2021 18:55:56 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9ueT-0001lF-7t for linux-arm-kernel@lists.infradead.org; Wed, 10 Feb 2021 18:55:50 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1AF0264E3B; Wed, 10 Feb 2021 18:55:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612983348; bh=81PR4MCGDuJyKoWR2LSx0GWPA1ftrT/kJVfSHoylZwI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hhlRzL962xx/nTdw+Uy7Elb2i2YR9vRmtNIxG9Iih/GFwYFEKKwoMNf62Uazg3Zd2 bpI+IqyInHNzb9gX3JZe7kE2VmG5MjM9W7poSk7ERdOTW56NApsHhv3IQgKgKaczNj Y0anIVuV0+hzDVVLoBx5pnmFkWIoRh13bJb1QdrsvVqZwLqyL2kJgP6v32OPMYNejQ D3ButEyhpQAmUjNJ8CPKkL9J1qRYlncQnPYL8kPfxh8kWDqfCoBBK7HQZ9ATeRYTIo 69tvcZiAuk+GD1U9XH6s+JK5W0YNWv0smyTnNYledyFO9m+t7tDNHVAy+CTEUPhGn4 a7DMCcaMPL+mQ== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/3] ARM: cache-v7: refactor v7_invalidate_l1 to avoid clobbering r5/r6 Date: Wed, 10 Feb 2021 19:55:31 +0100 Message-Id: <20210210185532.8425-3-ardb@kernel.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210185532.8425-1-ardb@kernel.org> References: <20210210185532.8425-1-ardb@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210210_135549_469191_45DAADD7 X-CRM114-Status: GOOD ( 14.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicolas Pitre , Marc Zyngier , Linus Walleij , Russell King , kernel-team@android.com, Ard Biesheuvel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The cache invalidation code in v7_invalidate_l1 can be tweaked to re-read the associativity from CCSIDR, and keep the set/way identifier component in a single register that is assigned in the outer loop. This way, we need 2 registers less. Given that the number of sets is typically much larger than the associativity, rearrange the code so that the outer loop has the fewer number of iterations, ensuring that the re-read of CCSIDR only occurs a handful of times in practice. Fix the whitespace while at it, and update the comment to indicate that this code is no longer a clone of anything else. Acked-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/mm/cache-v7.S | 51 ++++++++++---------- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 307f381eee71..76201ee9ee59 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -33,9 +33,8 @@ icache_size: * processor. We fix this by performing an invalidate, rather than a * clean + invalidate, before jumping into the kernel. * - * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. + * This function needs to be called for both secondary cores startup and + * primary core resume procedures. */ ENTRY(v7_invalidate_l1) mov r0, #0 @@ -43,32 +42,32 @@ ENTRY(v7_invalidate_l1) isb mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR - movw r1, #0x7fff - and r2, r1, r0, lsr #13 + movw r3, #0x3ff + and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3] + clz r1, r3 @ WayShift + mov r2, #1 + mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] + movs r1, r2, lsl r1 @ #1 shifted left by same amount + moveq r1, #1 @ r1 needs value > 0 even if only 1 way - movw r1, #0x3ff + and r2, r0, #0x7 + add r2, r2, #4 @ SetShift - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets +1: movw r4, #0x7fff + and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<