From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25DAFC433E0 for ; Wed, 10 Feb 2021 18:57:06 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D70E364E32 for ; Wed, 10 Feb 2021 18:57:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D70E364E32 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=saIY2DTTd0sgs5miI73l/Q4THhOnfb0BS8L9/eGeRkU=; b=Xjk+WBrcl5PCSu83AljNA73af CgiiHG6NmZfnmiSlADi8xZxHtjmgut6ECRwCSaHE7LSDHXot0dQE9KvqWlwcVk0B0eI5e6ZtUhrO7 3kr94Uieb29HNmgzyk2XYrO8ATBTpKFjeonbuW2AG8dHCv8shbUnGiEJDkWEln/lNNB3JrppkMAFJ AH0ybBCfZ6rZ7YFi9H1UICEIEy/srO4sHw9u58usVum/+I35FZQeKMFV9n/B1DZdH0L8Ns3gJdY8g SUk35i593z6RHpEaWPT/ocQEWBturD4ROjY3B24KBdMV64R5spptylbOSPX5usitmhuUOZiQlBxV0 97Ppl7Lkg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9uec-0001nh-Fk; Wed, 10 Feb 2021 18:55:58 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9ueV-0001m7-MP for linux-arm-kernel@lists.infradead.org; Wed, 10 Feb 2021 18:55:53 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 3395060C41; Wed, 10 Feb 2021 18:55:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612983351; bh=myRBRdz/Yt6iPpx3WSXm960tD4KCzY2ooTgvFtDf5mg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S/bKMnM8xg/Oow1g6k5Fs8Jov2GS33wMFyrKoOtl/hNNBX0AUbPzfryMPOuAzYgx4 /PyVzzUx2ld04T6/5zEcyc3N8C6sYWzgbYsBhK9YuTRVPOToSBdpvU+LtHa1EN39AI LBsUvG6FrZhYufenqQHOdT69+g9DLetP+tM2uHCberIFeosH/Q4ySFrEmuoxOgbcNQ n03fB3TOnnLbXFW3WpSmz5rsIMpyr7Cwnbrp5l1Qzc6s3T/B1pKNZaqZCzpnxx3FRp 4Dh+MYOAbITqbZwmmm+FXxlA4pn6YYu3dw95Jk+4rm01rmryUqy7QQkIfH/CaIn2V6 D+f7PXXp60BIw== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/3] ARM: cache-v7: get rid of mini-stack Date: Wed, 10 Feb 2021 19:55:32 +0100 Message-Id: <20210210185532.8425-4-ardb@kernel.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210185532.8425-1-ardb@kernel.org> References: <20210210185532.8425-1-ardb@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210210_135551_928592_21F91DAE X-CRM114-Status: GOOD ( 14.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicolas Pitre , Marc Zyngier , Linus Walleij , Russell King , kernel-team@android.com, Ard Biesheuvel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that we have reduced the number of registers that we need to preserve when calling v7_invalidate_l1 from the boot code, we can use scratch registers to preserve the remaining ones, and get rid of the mini stack entirely. This works around any issues regarding cache behavior in relation to the uncached accesses to this memory, which is hard to get right in the general case (i.e., both bare metal and under virtualization) While at it, switch v7_invalidate_l1 to using ip as a scratch register instead of r4. This makes the function AAPCS compliant, and removes the need to stash r4 in ip across the call. Acked-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/memory.h | 15 -------- arch/arm/mm/cache-v7.S | 10 ++--- arch/arm/mm/proc-v7.S | 39 +++++++++----------- 3 files changed, 23 insertions(+), 41 deletions(-) diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 2f841cb65c30..a711322d9f40 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -150,21 +150,6 @@ extern unsigned long vectors_base; */ #define PLAT_PHYS_OFFSET UL(CONFIG_PHYS_OFFSET) -#ifdef CONFIG_XIP_KERNEL -/* - * When referencing data in RAM from the XIP region in a relative manner - * with the MMU off, we need the relative offset between the two physical - * addresses. The macro below achieves this, which is: - * __pa(v_data) - __xip_pa(v_text) - */ -#define PHYS_RELATIVE(v_data, v_text) \ - (((v_data) - PAGE_OFFSET + PLAT_PHYS_OFFSET) - \ - ((v_text) - XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) + \ - CONFIG_XIP_PHYS_ADDR)) -#else -#define PHYS_RELATIVE(v_data, v_text) ((v_data) - (v_text)) -#endif - #ifndef __ASSEMBLY__ /* diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 76201ee9ee59..830bbfb26ca5 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -53,12 +53,12 @@ ENTRY(v7_invalidate_l1) and r2, r0, #0x7 add r2, r2, #4 @ SetShift -1: movw r4, #0x7fff - and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] +1: movw ip, #0x7fff + and r0, ip, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] -2: mov r4, r0, lsl r2 @ NumSet << SetShift - orr r4, r4, r3 @ Reg = (Temp<