From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A1D6C433DB for ; Fri, 12 Feb 2021 16:20:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C927364E70 for ; Fri, 12 Feb 2021 16:20:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C927364E70 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:50848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAbBh-0004be-Sd for qemu-devel@archiver.kernel.org; Fri, 12 Feb 2021 11:20:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59946) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lAbAE-0002wz-Ga; Fri, 12 Feb 2021 11:19:26 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:44117) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lAbAA-0001zE-Cl; Fri, 12 Feb 2021 11:19:26 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07716797|-1; CH=blue; DM=|OVERLOAD|false|; DS=CONTINUE|ham_system_inform|0.317209-0.00875136-0.67404; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047211; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JYHUiP2_1613146748; Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JYHUiP2_1613146748) by smtp.aliyun-inc.com(10.147.40.26); Sat, 13 Feb 2021 00:19:08 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Subject: [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions Date: Fri, 12 Feb 2021 23:02:55 +0800 Message-Id: <20210212150256.885-38-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com> References: <20210212150256.885-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, LIU Zhiwei , qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 +++ target/riscv/insn32-64.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 6 ++++ target/riscv/packed_helper.c | 41 +++++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d3dd1fb248..6e9c205481 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1471,4 +1471,9 @@ DEF_HELPER_3(smdrs32, tl, env, tl, tl) DEF_HELPER_3(smxds32, tl, env, tl, tl) DEF_HELPER_3(sraiw_u, tl, env, tl, tl) + +DEF_HELPER_3(pkbb32, tl, env, tl, tl) +DEF_HELPER_3(pkbt32, tl, env, tl, tl) +DEF_HELPER_3(pktt32, tl, env, tl, tl) +DEF_HELPER_3(pktb32, tl, env, tl, tl) #endif diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 32066d3ac2..62cfd74830 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -166,3 +166,8 @@ smdrs32 0110100 ..... ..... 010 ..... 1111111 @r smxds32 0111100 ..... ..... 010 ..... 1111111 @r sraiw_u 0011010 ..... ..... 001 ..... 1111111 @sh5 + +pkbb32 0000111 ..... ..... 010 ..... 1111111 @r +pkbt32 0001111 ..... ..... 010 ..... 1111111 @r +pktt32 0010111 ..... ..... 010 ..... 1111111 @r +pktb32 0011111 ..... ..... 010 ..... 1111111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 57827d2e15..868b308ed6 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -1215,4 +1215,10 @@ GEN_RVP_R_OOL(smxds32); /* (RV64 Only) Non-SIMD 32-bit Shift Instructions */ GEN_RVP_SHIFTI(sraiw_u, sraiw_u, NULL); + +/* (RV64 Only) 32-bit Packing Instructions */ +GEN_RVP_R_OOL(pkbb32); +GEN_RVP_R_OOL(pkbt32); +GEN_RVP_R_OOL(pktt32); +GEN_RVP_R_OOL(pktb32); #endif diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 69a7788e99..e9add8fe5b 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -3818,4 +3818,45 @@ static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va, } RVPR(sraiw_u, 1, sizeof(target_ulong)); + +/* (RV64 Only) 32-bit packing instructions here */ +static inline void do_pkbb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR(pkbb32, 2, 4); + +static inline void do_pkbt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR(pkbt32, 2, 4); + +static inline void do_pktb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR(pktb32, 2, 4); + +static inline void do_pktt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR(pktt32, 2, 4); #endif -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1lAbAG-000338-NF for mharc-qemu-riscv@gnu.org; Fri, 12 Feb 2021 11:19:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59946) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lAbAE-0002wz-Ga; Fri, 12 Feb 2021 11:19:26 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:44117) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lAbAA-0001zE-Cl; Fri, 12 Feb 2021 11:19:26 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07716797|-1; CH=blue; DM=|OVERLOAD|false|; DS=CONTINUE|ham_system_inform|0.317209-0.00875136-0.67404; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047211; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JYHUiP2_1613146748; Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JYHUiP2_1613146748) by smtp.aliyun-inc.com(10.147.40.26); Sat, 13 Feb 2021 00:19:08 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, alistair23@gmail.com, palmer@dabbelt.com, LIU Zhiwei Subject: [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions Date: Fri, 12 Feb 2021 23:02:55 +0800 Message-Id: <20210212150256.885-38-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com> References: <20210212150256.885-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Feb 2021 16:19:27 -0000 Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 +++ target/riscv/insn32-64.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 6 ++++ target/riscv/packed_helper.c | 41 +++++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d3dd1fb248..6e9c205481 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1471,4 +1471,9 @@ DEF_HELPER_3(smdrs32, tl, env, tl, tl) DEF_HELPER_3(smxds32, tl, env, tl, tl) DEF_HELPER_3(sraiw_u, tl, env, tl, tl) + +DEF_HELPER_3(pkbb32, tl, env, tl, tl) +DEF_HELPER_3(pkbt32, tl, env, tl, tl) +DEF_HELPER_3(pktt32, tl, env, tl, tl) +DEF_HELPER_3(pktb32, tl, env, tl, tl) #endif diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 32066d3ac2..62cfd74830 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -166,3 +166,8 @@ smdrs32 0110100 ..... ..... 010 ..... 1111111 @r smxds32 0111100 ..... ..... 010 ..... 1111111 @r sraiw_u 0011010 ..... ..... 001 ..... 1111111 @sh5 + +pkbb32 0000111 ..... ..... 010 ..... 1111111 @r +pkbt32 0001111 ..... ..... 010 ..... 1111111 @r +pktt32 0010111 ..... ..... 010 ..... 1111111 @r +pktb32 0011111 ..... ..... 010 ..... 1111111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 57827d2e15..868b308ed6 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -1215,4 +1215,10 @@ GEN_RVP_R_OOL(smxds32); /* (RV64 Only) Non-SIMD 32-bit Shift Instructions */ GEN_RVP_SHIFTI(sraiw_u, sraiw_u, NULL); + +/* (RV64 Only) 32-bit Packing Instructions */ +GEN_RVP_R_OOL(pkbb32); +GEN_RVP_R_OOL(pkbt32); +GEN_RVP_R_OOL(pktt32); +GEN_RVP_R_OOL(pktb32); #endif diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 69a7788e99..e9add8fe5b 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -3818,4 +3818,45 @@ static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va, } RVPR(sraiw_u, 1, sizeof(target_ulong)); + +/* (RV64 Only) 32-bit packing instructions here */ +static inline void do_pkbb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR(pkbb32, 2, 4); + +static inline void do_pkbt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR(pkbt32, 2, 4); + +static inline void do_pktb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR(pktb32, 2, 4); + +static inline void do_pktt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR(pktt32, 2, 4); #endif -- 2.17.1