* [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size
@ 2021-02-15 15:56 Chris Wilson
2021-02-15 15:56 ` [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma Chris Wilson
` (9 more replies)
0 siblings, 10 replies; 25+ messages in thread
From: Chris Wilson @ 2021-02-15 15:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld, Chris Wilson
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_node
allocation. That is we will offset the vma->pages so that the first page
is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
All users must then not use i915_vma.node.start directly, but compute
the guard offset, thus all users are converted to use a
i915_vma_offset() wrapper.
The notable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 6 +--
.../gpu/drm/i915/gem/i915_gem_client_blt.c | 3 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 41 ++++++++++---------
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_blt.c | 13 +++---
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 15 +++----
.../drm/i915/gem/selftests/i915_gem_context.c | 19 ++++++---
.../drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
.../drm/i915/gem/selftests/igt_gem_utils.c | 7 ++--
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 8 ++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 ++-
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 7 +++-
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 12 +++---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 ++++----
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 17 ++++----
drivers/gpu/drm/i915/gt/selftest_lrc.c | 16 ++++----
.../drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 12 +++---
.../gpu/drm/i915/gt/selftest_workarounds.c | 9 ++--
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_scheduler.c | 4 +-
drivers/gpu/drm/i915/i915_vma.c | 21 +++++-----
drivers/gpu/drm/i915/i915_vma.h | 23 +++++++++--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 +++++-
drivers/gpu/drm/i915/selftests/i915_request.c | 20 ++++-----
.../gpu/drm/i915/selftests/i915_scheduler.c | 4 +-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 11 +++--
38 files changed, 196 insertions(+), 145 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 07db8e83f98e..2a72fb3c8416 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -237,8 +237,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
- info->fix.smem_len = vma->node.size;
+ (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
+ info->fix.smem_len = vma->size;
vaddr = i915_vma_pin_iomap(vma);
if (IS_ERR(vaddr)) {
@@ -248,7 +248,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out_unpin;
}
info->screen_base = vaddr;
- info->screen_size = vma->node.size;
+ info->screen_size = vma->size;
drm_fb_helper_fill_info(info, &ifbdev->helper, sizes);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 44821d94544f..864510b3a7fd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -218,7 +218,8 @@ static void clear_pages_worker(struct work_struct *work)
}
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
out_request:
if (unlikely(err)) {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index fe170186dd42..7f985902c24a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -368,22 +368,23 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
const struct i915_vma *vma,
unsigned int flags)
{
- if (vma->node.size < entry->pad_to_size)
+ const u64 start = i915_vma_offset(vma);
+ const u64 size = i915_vma_size(vma);
+
+ if (size < entry->pad_to_size)
return true;
- if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
+ if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
return true;
- if (flags & EXEC_OBJECT_PINNED &&
- vma->node.start != entry->offset)
+ if (flags & EXEC_OBJECT_PINNED && start != entry->offset)
return true;
- if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
- vma->node.start < BATCH_OFFSET_BIAS)
+ if (flags & __EXEC_OBJECT_NEEDS_BIAS && start < BATCH_OFFSET_BIAS)
return true;
if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
- (vma->node.start + vma->node.size + 4095) >> 32)
+ (start + size + 4095) >> 32)
return true;
if (flags & __EXEC_OBJECT_NEEDS_MAP &&
@@ -428,7 +429,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
u64 pin_flags;
if (vma->node.size)
- pin_flags = vma->node.start;
+ pin_flags = __i915_vma_offset(vma);
else
pin_flags = entry->offset & PIN_OFFSET_MASK;
@@ -607,8 +608,8 @@ static int eb_reserve_vma(struct i915_execbuffer *eb,
if (err)
return err;
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
@@ -899,8 +900,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
return err;
if (eb_pin_vma(eb, entry, ev)) {
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
} else {
@@ -977,7 +978,7 @@ static inline u64
relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
const struct i915_vma *target)
{
- return gen8_canonical_addr((int)reloc->delta + target->node.start);
+ return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target));
}
static void reloc_cache_clear(struct reloc_cache *cache)
@@ -1173,7 +1174,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
if (err) /* no inactive aperture space, use cpu reloc */
return NULL;
} else {
- cache->node.start = vma->node.start;
+ cache->node.start = i915_ggtt_offset(vma);
cache->node.mm = (void *)vma;
}
}
@@ -1338,7 +1339,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
goto err_request;
err = eb->engine->emit_bb_start(rq,
- batch->node.start, PAGE_SIZE,
+ i915_vma_offset(batch), PAGE_SIZE,
cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
if (err)
goto skip_request;
@@ -1458,7 +1459,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb,
else if (IS_ERR(batch))
return false;
- addr = gen8_canonical_addr(vma->node.start + offset);
+ addr = gen8_canonical_addr(i915_vma_offset(vma) + offset);
if (gen >= 8) {
if (offset & 7) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
@@ -1558,7 +1559,7 @@ relocate_entry(struct i915_vma *vma,
}
}
- return target->node.start | UPDATE;
+ return i915_vma_offset(target) | UPDATE;
}
static u64
@@ -1622,7 +1623,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
* more work needs to be done.
*/
if (!DBG_FORCE_RELOC &&
- gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
+ gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset)
return 0;
/* Check that the relocation address is valid... */
@@ -2554,7 +2555,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch)
}
err = eb->engine->emit_bb_start(eb->request,
- batch->node.start +
+ i915_vma_offset(batch) +
eb->batch_start_offset,
eb->batch_len,
eb->batch_flags);
@@ -2564,7 +2565,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch)
if (eb->trampoline) {
GEM_BUG_ON(eb->batch_start_offset);
err = eb->engine->emit_bb_start(eb->request,
- eb->trampoline->node.start +
+ i915_vma_offset(eb->trampoline) +
eb->batch_len,
0, 0);
if (err)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index ec28a6cde49b..02cb84285dbb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -365,7 +365,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
- (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
+ (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
min_t(u64, vma->size, area->vm_end - area->vm_start),
&ggtt->iomap);
if (ret)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index d6dac21fce0b..acd142406d00 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -62,7 +62,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
}
rem = vma->size;
- offset = vma->node.start;
+ offset = i915_vma_offset(vma);
do {
u32 size = min_t(u64, rem, block_size);
@@ -199,8 +199,8 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
if (likely(!err))
err = ce->engine->emit_bb_start(rq,
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
out_request:
if (unlikely(err))
@@ -284,8 +284,8 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
}
rem = src->size;
- src_offset = src->node.start;
- dst_offset = dst->node.start;
+ src_offset = i915_vma_offset(src);
+ dst_offset = i915_vma_offset(dst);
do {
size = min_t(u64, rem, block_size);
@@ -423,7 +423,8 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
}
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
out_request:
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index b64a0788381f..7a1a90cd8bcd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -376,7 +376,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
mutex_lock(&i915->ggtt.vm.mutex);
list_for_each_entry_safe(vma, next,
&i915->ggtt.vm.bound_list, vm_link) {
- unsigned long count = vma->node.size >> PAGE_SHIFT;
+ unsigned long count = i915_vma_size(vma) >> PAGE_SHIFT;
if (!vma->iomap || i915_vma_is_active(vma))
continue;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index d589d3d81085..b92bcb04f563 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -166,11 +166,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma,
return true;
size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return false;
alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
- if (!IS_ALIGNED(vma->node.start, alignment))
+ if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment))
return false;
return true;
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 10ee24b252dd..4b50af149cfc 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -377,7 +377,7 @@ static int igt_check_page_sizes(struct i915_vma *vma)
* Maintaining alignment is required to utilise huge pages in the ppGGT.
*/
if (i915_gem_object_is_lmem(obj) &&
- IS_ALIGNED(vma->node.start, SZ_2M) &&
+ IS_ALIGNED(i915_vma_offset(vma), SZ_2M) &&
vma->page_sizes.sg & SZ_2M &&
vma->page_sizes.gtt < SZ_2M) {
pr_err("gtt pages mismatch for LMEM, expected 2M GTT pages, sg(%u), gtt(%u)\n",
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 175581724d44..5a1cb2894840 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -212,14 +212,14 @@ static int prepare_blit(const struct tiled_blits *t,
*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
*cs++ = 0;
*cs++ = t->height << 16 | t->width;
- *cs++ = lower_32_bits(dst->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(dst->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(dst->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(dst->vma));
*cs++ = 0;
*cs++ = src_pitch;
- *cs++ = lower_32_bits(src->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(src->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(src->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(src->vma));
*cs++ = MI_BATCH_BUFFER_END;
@@ -435,7 +435,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
{
int err;
- if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) {
+ if (drm_mm_node_allocated(&vma->node) && i915_vma_offset(vma) != addr) {
err = i915_vma_unbind(vma);
if (err)
return err;
@@ -445,6 +445,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
if (err)
return err;
+ GEM_BUG_ON(i915_vma_offset(vma) != addr);
return 0;
}
@@ -491,8 +492,8 @@ tiled_blit(struct tiled_blits *t,
err = move_to_active(dst->vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- t->batch->node.start,
- t->batch->node.size,
+ i915_vma_offset(t->batch),
+ i915_vma_size(t->batch),
0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index df949320f2b5..937c5edbff35 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -905,8 +905,8 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
*cmd = MI_BATCH_BUFFER_END;
__i915_gem_object_flush_map(rpcs, 0, 64);
@@ -992,7 +992,8 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
}
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
if (err)
goto skip_request;
@@ -1561,7 +1562,10 @@ static int write_to_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
+ 0);
if (err)
goto skip_request;
@@ -1668,7 +1672,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
*cmd++ = reg;
- *cmd++ = vma->node.start + result;
+ *cmd++ = i915_vma_offset(vma) + result;
*cmd = MI_BATCH_BUFFER_END;
i915_gem_object_flush_map(obj);
@@ -1699,7 +1703,10 @@ static int read_from_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, flags);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
+ flags);
if (err)
goto skip_request;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 39293d98f34d..d37706807703 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -1145,7 +1145,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
if (err == 0)
err = i915_vma_move_to_active(vma, rq, 0);
- err = engine->emit_bb_start(rq, vma->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
index b7e064667d39..f3f43cf6a0ac 100644
--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
+++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
@@ -62,8 +62,8 @@ igt_emit_store_dw(struct i915_vma *vma,
goto err;
}
- GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size);
- offset += vma->node.start;
+ GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > i915_vma_size(vma));
+ offset += i915_vma_offset(vma);
for (n = 0; n < count; n++) {
if (gen >= 8) {
@@ -153,7 +153,8 @@ int igt_gpu_fill_dw(struct intel_context *ce,
flags |= I915_DISPATCH_SECURE;
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_offset(batch),
flags);
skip_request:
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index e08dff376339..d16cfa75c03a 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -111,7 +111,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
{
struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_directory * const pd = ppgtt->pd;
- unsigned int first_entry = vma->node.start / I915_GTT_PAGE_SIZE;
+ unsigned int first_entry = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
unsigned int act_pt = first_entry / GEN6_PTES;
unsigned int act_pte = first_entry % GEN6_PTES;
const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index de575fdb033f..52e6f08d0ced 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -105,7 +105,7 @@ static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)
static u32 batch_addr(const struct batch_chunk *bc)
{
- return bc->vma->node.start;
+ return i915_vma_offset(bc->vma);
}
static void batch_add(struct batch_chunk *bc, const u32 d)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 176c19633412..9d88d81c30d2 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -419,7 +419,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
{
const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
- u64 start = vma->node.start;
+ u64 start = i915_vma_offset(vma);
GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm));
@@ -502,8 +502,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
if (maybe_64K != -1 &&
(index == I915_PDES ||
(i915_vm_has_scratch_64K(vma->vm) &&
- !iter->sg && IS_ALIGNED(vma->node.start +
- vma->node.size,
+ !iter->sg && IS_ALIGNED(i915_vma_offset(vma) +
+ i915_vma_size(vma),
I915_GTT_PAGE_SIZE_2M)))) {
vaddr = kmap_atomic_px(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
@@ -547,7 +547,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
gen8_ppgtt_insert_huge(vma, &iter, cache_level, flags);
} else {
- u64 idx = vma->node.start >> GEN8_PTE_SHIFT;
+ u64 idx = i915_vma_offset(vma) >> GEN8_PTE_SHIFT;
do {
struct i915_page_directory * const pdp =
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index b0b8ded834f0..c5803c434d33 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -440,7 +440,8 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
unsigned int flags = (cache_level == I915_CACHE_NONE) ?
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
- intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
+ intel_gtt_insert_sg_entries(vma->pages,
+ i915_ggtt_offset(vma) >> PAGE_SHIFT,
flags);
}
@@ -631,7 +632,7 @@ static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
struct i915_vma *vma)
{
if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_ggtt_offset(vma), vma->size);
if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND))
ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index e891552611d5..87160e3fed37 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -215,7 +215,8 @@ static int fence_update(struct i915_fence_reg *fence,
return ret;
}
- fence->start = vma->node.start;
+ GEM_BUG_ON(vma->fence_size > i915_vma_size(vma));
+ fence->start = i915_ggtt_offset(vma);
fence->size = vma->fence_size;
fence->stride = i915_gem_object_get_stride(vma->obj);
fence->tiling = i915_gem_object_get_tiling(vma->obj);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index a91955af50a6..0d11894aa848 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -186,7 +186,10 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
u32 pte_flags;
if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) {
- vm->allocate_va_range(vm, stash, vma->node.start, vma->size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
+ vm->allocate_va_range(vm, stash,
+ i915_vma_offset(vma),
+ vma->size);
set_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma));
}
@@ -204,7 +207,7 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
{
if (test_and_clear_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma)))
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_vma_offset(vma), vma->size);
}
static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index 0f7c0a148b80..214a154665b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -61,7 +61,7 @@ static int render_state_setup(struct intel_renderstate *so,
u32 s = rodata->batch[i];
if (i * 4 == rodata->reloc[reloc_index]) {
- u64 r = s + so->vma->node.start;
+ u64 r = s + i915_vma_offset(so->vma);
s = lower_32_bits(r);
if (HAS_64BIT_RELOC(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 282089d64789..2c75e3fa6350 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -824,7 +824,7 @@ static int clear_residuals(struct i915_request *rq)
}
ret = engine->emit_bb_start(rq,
- engine->wa_ctx.vma->node.start, 0,
+ i915_vma_offset(engine->wa_ctx.vma), 0,
0);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 84d883de30ee..bba926440d7d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -162,8 +162,8 @@ static int perf_mi_bb_start(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- batch->node.start, 8,
- 0);
+ i915_vma_offset(batch),
+ 8, 0);
if (err)
goto out;
@@ -302,8 +302,8 @@ static int perf_mi_noop(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- base->node.start, 8,
- 0);
+ i915_vma_offset(base),
+ 8, 0);
if (err)
goto out;
@@ -312,8 +312,8 @@ static int perf_mi_noop(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- nop->node.start,
- nop->node.size,
+ i915_vma_offset(nop),
+ i915_vma_size(nop),
0);
if (err)
goto out;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index f625c29023ea..d7de18d8b06a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2704,11 +2704,11 @@ static int create_gang(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_EQ_SDD;
*cs++ = 0;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(vma));
+ *cs++ = upper_32_bits(i915_vma_offset(vma));
if (*prev) {
- u64 offset = (*prev)->batch->node.start;
+ u64 offset = i915_vma_offset((*prev)->batch);
/* Terminate the spinner in the next lower priority batch. */
*cs++ = MI_STORE_DWORD_IMM_GEN4;
@@ -2736,7 +2736,7 @@ static int create_gang(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
i915_request_add(rq);
@@ -3062,7 +3062,7 @@ create_gpr_user(struct intel_engine_cs *engine,
*cs++ = MI_MATH_ADD;
*cs++ = MI_MATH_STORE(MI_MATH_REG(i), MI_MATH_REG_ACCU);
- addr = result->node.start + offset + i * sizeof(*cs);
+ addr = i915_vma_offset(result) + offset + i * sizeof(*cs);
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = CS_GPR(engine, 2 * i);
*cs++ = lower_32_bits(addr);
@@ -3072,8 +3072,8 @@ create_gpr_user(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_GTE_SDD;
*cs++ = i;
- *cs++ = lower_32_bits(result->node.start);
- *cs++ = upper_32_bits(result->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(result));
+ *cs++ = upper_32_bits(i915_vma_offset(result));
}
*cs++ = MI_BATCH_BUFFER_END;
@@ -3157,7 +3157,7 @@ create_gpr_client(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(batch, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- batch->node.start,
+ i915_vma_offset(batch),
PAGE_SIZE, 0);
i915_vma_unlock(batch);
i915_vma_unpin(batch);
@@ -3486,7 +3486,7 @@ static int smoke_submit(struct preempt_smoke *smoke,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index cdb0ceff3be1..6144fe173188 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -92,7 +92,8 @@ static int hang_init(struct hang *h, struct intel_gt *gt)
static u64 hws_address(const struct i915_vma *hws,
const struct i915_request *rq)
{
- return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
+ return (i915_vma_offset(hws) +
+ offset_in_page(sizeof(u32) * rq->fence.context));
}
static int move_to_active(struct i915_vma *vma,
@@ -192,8 +193,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
} else if (INTEL_GEN(gt->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
@@ -206,7 +207,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else if (INTEL_GEN(gt->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
@@ -219,7 +220,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else {
*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -231,7 +232,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
}
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
intel_gt_chipset_flush(engine->gt);
@@ -246,7 +247,9 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
if (INTEL_GEN(gt->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = rq->engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ PAGE_SIZE, flags);
cancel_rq:
if (err) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 279091e41b41..25292b370309 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -969,8 +969,8 @@ store_context(struct intel_context *ce,
while (len--) {
*cs++ = cmd;
*cs++ = (hw[dw] & mask) + offset;
- *cs++ = lower_32_bits(scratch->node.start + x);
- *cs++ = upper_32_bits(scratch->node.start + x);
+ *cs++ = lower_32_bits(i915_vma_offset(scratch) + x);
+ *cs++ = upper_32_bits(i915_vma_offset(scratch) + x);
dw += 2;
x += 4;
@@ -1078,8 +1078,8 @@ record_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(b_before->node.start);
- *cs++ = upper_32_bits(b_before->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(b_before));
+ *cs++ = upper_32_bits(i915_vma_offset(b_before));
if (sema) {
WRITE_ONCE(*sema->va, -1);
@@ -1106,8 +1106,8 @@ record_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(b_after->node.start);
- *cs++ = upper_32_bits(b_after->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(b_after));
+ *cs++ = upper_32_bits(i915_vma_offset(b_after));
intel_ring_advance(rq, cs);
@@ -1243,8 +1243,8 @@ poison_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(batch->node.start);
- *cs++ = upper_32_bits(batch->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(batch));
+ *cs++ = upper_32_bits(i915_vma_offset(batch));
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = sema->ggtt;
diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
index 6cd9f6bc240c..92d0dc0ab68b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
@@ -50,7 +50,7 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
} else {
*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
}
- *cs++ = vma->node.start + 4000;
+ *cs++ = i915_vma_offset(vma) + 4000;
*cs++ = STACK_MAGIC;
*cs++ = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 967641fee42a..1f58db52670c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -119,14 +119,14 @@ create_spin_counter(struct intel_engine_cs *engine,
if (srm) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));
- *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
}
}
*cs++ = MI_BATCH_BUFFER_START_GEN8;
- *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
GEM_BUG_ON(cs - base > end);
i915_gem_object_flush_map(obj);
@@ -655,7 +655,7 @@ int live_rps_frequency_cs(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
@@ -796,7 +796,7 @@ int live_rps_frequency_srm(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index e5ee6136c81f..dbdaa9645428 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -475,7 +475,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
for (i = 0; i < engine->whitelist.count; i++) {
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
- u64 addr = scratch->node.start;
+ u64 addr = i915_vma_offset(scratch);
struct i915_request *rq;
u32 srm, lrm, rsvd;
u32 expect;
@@ -584,7 +584,8 @@ static int check_dirty_whitelist(struct intel_context *ce)
goto err_request;
err = engine->emit_bb_start(rq,
- batch->node.start, PAGE_SIZE,
+ i915_vma_offset(batch),
+ PAGE_SIZE,
0);
if (err)
goto err_request;
@@ -791,7 +792,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
}
for (i = 0; i < engine->whitelist.count; i++) {
- u64 offset = results->node.start + sizeof(u32) * i;
+ u64 offset = i915_vma_offset(results) + sizeof(u32) * i;
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
/* Clear non priv flags */
@@ -865,7 +866,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce)
goto err_request;
/* Perform the writes from an unprivileged "user" batch */
- err = engine->emit_bb_start(rq, batch->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0);
err_request:
err = request_add_sync(rq, err);
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index ced9a96d7c34..6c5658557461 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1442,8 +1442,8 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
/* Defer failure until attempted use */
jump_whitelist = alloc_whitelist(batch_length);
- shadow_addr = gen8_canonical_addr(shadow->node.start);
- batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);
+ shadow_addr = gen8_canonical_addr(i915_vma_offset(shadow));
+ batch_addr = gen8_canonical_addr(i915_vma_offset(batch) + batch_offset);
/*
* We use the batch length as size because the shadow object is as
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 51133b8fabb4..a65a99fa5331 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -158,7 +158,8 @@ i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
i915_vma_is_ggtt(vma) ? "g" : "pp",
- vma->node.start, vma->node.size,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
if (i915_vma_is_ggtt(vma)) {
switch (vma->ggtt_view.type) {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 291f5b818925..c7abe4ee61be 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1011,8 +1011,8 @@ i915_vma_coredump_create(const struct intel_gt *gt,
strcpy(dst->name, name);
dst->next = NULL;
- dst->gtt_offset = vma->node.start;
- dst->gtt_size = vma->node.size;
+ dst->gtt_offset = i915_vma_offset(vma);
+ dst->gtt_size = i915_vma_size(vma);
dst->gtt_page_sizes = vma->page_sizes.gtt;
dst->num_pages = num_pages;
dst->page_count = 0;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c15bead2dac7..212cac7a2ab8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1980,7 +1980,7 @@ emit_oa_config(struct i915_perf_stream *stream,
goto err_add_request;
err = rq->engine->emit_bb_start(rq,
- vma->node.start, 0,
+ i915_vma_offset(vma), 0,
I915_DISPATCH_SECURE);
if (err)
goto err_add_request;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index a8fb787278e6..cd08e75a6101 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -1127,14 +1127,14 @@ static void hexdump(struct drm_printer *m, const void *buf, size_t len)
static void
print_request_ring(struct drm_printer *m, const struct i915_request *rq)
{
+ u64 batch = rq->batch ? __i915_vma_offset(rq->batch) : ~0ull;
void *ring;
int size;
drm_printf(m,
"[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
rq->head, rq->postfix, rq->tail,
- rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
- rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
+ upper_32_bits(batch), lower_32_bits(batch));
size = rq->tail - rq->head;
if (rq->tail < rq->head)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index caa9b041616b..748f5ea1ba04 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -382,7 +382,7 @@ int i915_vma_bind(struct i915_vma *vma,
u32 vma_flags;
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(vma->size > vma->node.size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start,
vma->node.size,
@@ -459,8 +459,8 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
ptr = READ_ONCE(vma->iomap);
if (ptr == NULL) {
ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
- vma->node.start,
- vma->node.size);
+ i915_vma_offset(vma),
+ i915_vma_size(vma));
if (ptr == NULL) {
err = -ENOMEM;
goto err;
@@ -534,22 +534,22 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
if (test_bit(I915_VMA_ERROR_BIT, __i915_vma_flags(vma)))
return true;
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return true;
GEM_BUG_ON(alignment && !is_power_of_2(alignment));
- if (alignment && !IS_ALIGNED(vma->node.start, alignment))
+ if (alignment && !IS_ALIGNED(i915_vma_offset(vma), alignment))
return true;
if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma))
return true;
if (flags & PIN_OFFSET_BIAS &&
- vma->node.start < (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) < (flags & PIN_OFFSET_MASK))
return true;
if (flags & PIN_OFFSET_FIXED &&
- vma->node.start != (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
return true;
return false;
@@ -562,10 +562,11 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- fenceable = (vma->node.size >= vma->fence_size &&
- IS_ALIGNED(vma->node.start, vma->fence_alignment));
+ fenceable = (i915_vma_size(vma) >= vma->fence_size &&
+ IS_ALIGNED(i915_vma_offset(vma), vma->fence_alignment));
- mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end;
+ mappable = (i915_ggtt_offset(vma) + vma->fence_size <=
+ i915_vm_to_ggtt(vma->vm)->mappable_end);
if (mappable && fenceable)
set_bit(I915_VMA_CAN_FENCE_BIT, __i915_vma_flags(vma));
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index a64adc8c883b..3066d36b2ccd 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -110,13 +110,30 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
return !list_empty(&vma->closed_link);
}
+static inline u64 i915_vma_size(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return vma->node.size;
+}
+
+static inline u64 __i915_vma_offset(const struct i915_vma *vma)
+{
+ return vma->node.start;
+}
+
+static inline u64 i915_vma_offset(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return __i915_vma_offset(vma);
+}
+
static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
{
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(upper_32_bits(vma->node.start));
- GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1));
- return lower_32_bits(vma->node.start);
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma)));
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) + i915_vma_size(vma) - 1));
+ return lower_32_bits(i915_vma_offset(vma));
}
static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index c1adea8765a9..d33ef0cc02ea 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -231,6 +231,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
if (!mock_vma)
return -ENOMEM;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &mock_vma->node.flags);
+ if (i915_is_ggtt(vm))
+ __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(mock_vma));
+
/* Keep creating larger objects until one cannot fit into the hole */
for (size = 12; (hole_end - hole_start) >> size; size++) {
I915_RND_SUBSTATE(prng, seed_prng);
@@ -1941,6 +1945,7 @@ static int igt_cs_tlb(void *arg)
i915_vm_free_pt_stash(vm, &stash);
/* Prime the TLB with the dummy pages */
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
for (i = 0; i < count; i++) {
vma->node.start = offset + i * PAGE_SIZE;
vm->insert_entries(vm, vma, I915_CACHE_NONE, 0);
@@ -1952,8 +1957,9 @@ static int igt_cs_tlb(void *arg)
}
i915_request_put(rq);
}
-
vma->ops->clear_pages(vma);
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
+ &vma->node.flags);
err = context_sync(ce);
if (err) {
@@ -1973,6 +1979,7 @@ static int igt_cs_tlb(void *arg)
goto end;
/* Replace the TLB with target batches */
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
for (i = 0; i < count; i++) {
struct i915_request *rq;
u32 *cs = batch + i * 64 / sizeof(*cs);
@@ -2005,8 +2012,9 @@ static int igt_cs_tlb(void *arg)
i915_request_put(rq);
}
end_spin(batch, count - 1);
-
vma->ops->clear_pages(vma);
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
+ &vma->node.flags);
err = context_sync(ce);
if (err) {
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index 8035ea7565ed..61fa6c7d3907 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -668,8 +668,8 @@ empty_request(struct intel_engine_cs *engine,
return request;
err = engine->emit_bb_start(request,
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
I915_DISPATCH_SECURE);
if (err)
goto out_request;
@@ -789,14 +789,14 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
if (gen >= 8) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
} else if (gen >= 6) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
} else {
*cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
}
*cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
@@ -880,8 +880,8 @@ static int live_all_engines(void *arg)
GEM_BUG_ON(err);
err = engine->emit_bb_start(request[idx],
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
GEM_BUG_ON(err);
request[idx]->batch = batch;
@@ -1010,8 +1010,8 @@ static int live_sequential_engines(void *arg)
GEM_BUG_ON(err);
err = engine->emit_bb_start(request[idx],
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
GEM_BUG_ON(err);
request[idx]->batch = batch;
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
index f54bdbeaa48b..6ed27896391b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -568,8 +568,8 @@ __write_timestamp(struct intel_engine_cs *engine,
*cs++ = MI_STORE_REGISTER_MEM + use_64b;
*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base));
- *cs++ = lower_32_bits(vma->node.start) + sizeof(u32) * slot;
- *cs++ = upper_32_bits(vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(vma)) + sizeof(u32) * slot;
+ *cs++ = upper_32_bits(i915_vma_offset(vma));
intel_ring_advance(rq, cs);
i915_request_get(rq);
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 0e6c1ea0082a..5c4f0f71aa29 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -67,7 +67,7 @@ static unsigned int seqno_offset(u64 fence)
static u64 hws_address(const struct i915_vma *hws,
const struct i915_request *rq)
{
- return hws->node.start + seqno_offset(rq->fence.context);
+ return i915_vma_offset(hws) + seqno_offset(rq->fence.context);
}
static int move_to_active(struct i915_vma *vma,
@@ -163,8 +163,8 @@ igt_spinner_create_request(struct igt_spinner *spin,
*batch++ = MI_BATCH_BUFFER_START;
else
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
@@ -179,7 +179,10 @@ igt_spinner_create_request(struct igt_spinner *spin,
flags = 0;
if (INTEL_GEN(rq->engine->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ PAGE_SIZE,
+ flags);
cancel_rq:
if (err) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
@ 2021-02-15 15:56 ` Chris Wilson
2021-02-15 18:04 ` Matthew Auld
2021-02-15 20:33 ` [Intel-gfx] [PATCH] " Chris Wilson
2021-02-15 15:56 ` [Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround Chris Wilson
` (8 subsequent siblings)
9 siblings, 2 replies; 25+ messages in thread
From: Chris Wilson @ 2021-02-15 15:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld, Chris Wilson
Introduce the concept of padding the i915_vma with guard pages before
and aft. The major consequence is that all ordinary uses of i915_vma
must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
directly, as the drm_mm_node will include the guard pages that surround
our object.
The biggest connundrum is how exactly to mix requesting a fixed address
with guard pages, particularly through the existing uABI. The user does
not know about guard pages, so such must be transparent to the user, and
so the execobj.offset must be that of the object itself excluding the
guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
The caveat is that some placements will be impossible with guard pages,
as wrap arounds need to be avoided, and the vma itself will require a
larger node. We must we not report EINVAL but ENOSPC as these are
unavailable locations within the GTT rather than conflicting user
requirements.
In the next patch, we start using guard pages for scanout objects. While
these are limited to GGTT vma, on a few platforms these vma (or at least
an alias of the vma) is shared with userspace, so we may leak the
existence of such guards if we are not careful to ensure that the
execobj.offset is transparent and excludes the guards. (On such platforms
like ivb, without full-ppgtt, userspace has to use relocations so the
presence of more untouchable regions within its GTT such be of no further
issue.)
v2: Include the guard range in the overflow checks and placement
restrictions.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++++++++++--
drivers/gpu/drm/i915/i915_vma.c | 28 ++++++++++++++++++++++-----
drivers/gpu/drm/i915/i915_vma.h | 5 +++--
drivers/gpu/drm/i915/i915_vma_types.h | 3 ++-
4 files changed, 38 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index c5803c434d33..6b326138e765 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -238,8 +238,12 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
gte = (gen8_pte_t __iomem *)ggtt->gsm;
gte += vma->node.start / I915_GTT_PAGE_SIZE;
- end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
+ end = gte + vma->guard / I915_GTT_PAGE_SIZE;
+ while (gte < end)
+ gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+ end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, iter, vma->pages)
gen8_set_pte(gte++, pte_encode | addr);
GEM_BUG_ON(gte > end);
@@ -289,8 +293,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
gte = (gen6_pte_t __iomem *)ggtt->gsm;
gte += vma->node.start / I915_GTT_PAGE_SIZE;
- end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
+ end = gte + vma->guard / I915_GTT_PAGE_SIZE;
+ while (gte < end)
+ gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+ end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, iter, vma->pages)
iowrite32(vm->pte_encode(addr, level, flags), gte++);
GEM_BUG_ON(gte > end);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 748f5ea1ba04..31d0f8b64ec0 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -623,7 +623,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
static int
i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
- unsigned long color;
+ unsigned long color, guard;
u64 start, end;
int ret;
@@ -631,7 +631,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
size = max(size, vma->size);
- alignment = max(alignment, vma->display_alignment);
+ alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
if (flags & PIN_MAPPABLE) {
size = max_t(typeof(size), size, vma->fence_size);
alignment = max_t(typeof(alignment),
@@ -642,6 +642,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
GEM_BUG_ON(!is_power_of_2(alignment));
+ guard = vma->guard; /* retain guard across rebinds */
+ guard = ALIGN(guard, alignment);
+
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
@@ -651,12 +654,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
if (flags & PIN_ZONE_4G)
end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);
GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
+ GEM_BUG_ON(2 * guard > end);
/* If binding the object/GGTT view requires more space than the entire
* aperture has, reject it early before evicting everything in a vain
* attempt to find space.
*/
- if (size > end) {
+ if (size > end - 2 * guard) {
DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu > %s aperture=%llu\n",
size, flags & PIN_MAPPABLE ? "mappable" : "total",
end);
@@ -669,16 +673,29 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
if (flags & PIN_OFFSET_FIXED) {
u64 offset = flags & PIN_OFFSET_MASK;
+
if (!IS_ALIGNED(offset, alignment) ||
range_overflows(offset, size, end))
return -EINVAL;
+ /*
+ * The caller knows not of the guard added by others and
+ * requests for the offset of the start of its buffer
+ * to be fixed, which may not be the same as the position
+ * of the vma->node due to the guard pages.
+ */
+ if (offset < guard || offset > end - size - 2 * guard)
+ return -ENOSPC;
+
ret = i915_gem_gtt_reserve(vma->vm, &vma->node,
- size, offset, color,
- flags);
+ size + 2 * guard,
+ offset - guard,
+ color, flags);
if (ret)
return ret;
} else {
+ size += 2 * guard;
+
/*
* We only support huge gtt pages through the 48b PPGTT,
* however we also don't want to force any alignment for
@@ -725,6 +742,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, color));
list_add_tail(&vma->vm_link, &vma->vm->bound_list);
+ vma->guard = guard;
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 3066d36b2ccd..5004ece1eb9a 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -113,12 +113,13 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
static inline u64 i915_vma_size(const struct i915_vma *vma)
{
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- return vma->node.size;
+ return vma->node.size - 2 * vma->guard;
}
static inline u64 __i915_vma_offset(const struct i915_vma *vma)
{
- return vma->node.start;
+ /* The actual start of the vma->pages is after the guard pages. */
+ return vma->node.start + vma->guard;
}
static inline u64 i915_vma_offset(const struct i915_vma *vma)
diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h
index f5cb848b7a7e..6e55a71543ea 100644
--- a/drivers/gpu/drm/i915/i915_vma_types.h
+++ b/drivers/gpu/drm/i915/i915_vma_types.h
@@ -182,14 +182,15 @@ struct i915_vma {
struct i915_fence_reg *fence;
u64 size;
- u64 display_alignment;
struct i915_page_sizes page_sizes;
/* mmap-offset associated with fencing for this vma */
struct i915_mmap_offset *mmo;
+ u32 guard; /* padding allocated around vma->pages within the node */
u32 fence_size;
u32 fence_alignment;
+ u32 display_alignment;
/**
* Count of the number of times this vma has been opened by different
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
2021-02-15 15:56 ` [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma Chris Wilson
@ 2021-02-15 15:56 ` Chris Wilson
2021-02-15 18:07 ` Matthew Auld
` (2 more replies)
2021-02-15 17:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size Patchwork
` (7 subsequent siblings)
9 siblings, 3 replies; 25+ messages in thread
From: Chris Wilson @ 2021-02-15 15:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld, Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 160 PTE,
warning that the accesses will wrap around the ends of the GGTT.
Currently, we fill the entire GGTT with scratch pages when using VT-d to
always ensure there are valid entries around every vma, including
scanout. However, writing every PTE is slow as on recent devices we
perform 8MiB of uncached writes, incurring an extra 100ms during resume.
If instead we focus on only putting guard pages around scanout, we can
avoid touching the whole GGTT. To avoid having to introduce extra nodes
around each scanout vma, we adjust the scanout drm_mm_node to be smaller
than the allocated space, and fixup the extra PTE during dma binding.
v2: Move the guard from modifying drm_mm_node.start which is still used
by the drm_mm itself, into an adjustment of node.start at the point of
use.
v3: Pass the requested guard padding from the caller, so we can drop the
VT-d w/a knowledge from the i915_vma allocator.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com> # v2
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 6 ++++++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +---------------------
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/i915_vma.c | 8 +++++++
4 files changed, 16 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 0478b069c202..4b577cf7ec7e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -16,6 +16,8 @@
#include "i915_gem_lmem.h"
#include "i915_gem_mman.h"
+#define VTD_GUARD (160 * I915_GTT_PAGE_SIZE) /* 160 PTE padding */
+
static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
return !(obj->cache_level == I915_CACHE_NONE ||
@@ -345,6 +347,10 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
if (ret)
goto err;
+ /* VT-d may overfetch before/after the vma, so pad with scratch */
+ if (intel_scanout_needs_vtd_wa(i915))
+ flags |= PIN_OFFSET_GUARD | VTD_GUARD;
+
/*
* As the user may map the buffer once pinned in the display plane
* (e.g. libkms for the bootup splash), we have to ensure that we
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 6b326138e765..251b50884d1c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -319,27 +319,6 @@ static void nop_clear_range(struct i915_address_space *vm,
{
}
-static void gen8_ggtt_clear_range(struct i915_address_space *vm,
- u64 start, u64 length)
-{
- struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
- unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
- unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
- const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
- gen8_pte_t __iomem *gtt_base =
- (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
- const int max_entries = ggtt_total_entries(ggtt) - first_entry;
- int i;
-
- if (WARN(num_entries > max_entries,
- "First entry = %d; Num entries = %d (max=%d)\n",
- first_entry, num_entries, max_entries))
- num_entries = max_entries;
-
- for (i = 0; i < num_entries; i++)
- gen8_set_pte(>t_base[i], scratch_pte);
-}
-
static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
{
/*
@@ -907,8 +886,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.cleanup = gen6_gmch_remove;
ggtt->vm.insert_page = gen8_ggtt_insert_page;
ggtt->vm.clear_range = nop_clear_range;
- if (intel_scanout_needs_vtd_wa(i915))
- ggtt->vm.clear_range = gen8_ggtt_clear_range;
ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
@@ -1054,7 +1031,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
ggtt->vm.clear_range = nop_clear_range;
- if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
+ if (!HAS_FULL_PPGTT(i915))
ggtt->vm.clear_range = gen6_ggtt_clear_range;
ggtt->vm.insert_page = gen6_ggtt_insert_page;
ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c9b0ee5e1d23..f3ae9afdee15 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -41,6 +41,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
#define PIN_HIGH BIT_ULL(5)
#define PIN_OFFSET_BIAS BIT_ULL(6)
#define PIN_OFFSET_FIXED BIT_ULL(7)
+#define PIN_OFFSET_GUARD BIT_ULL(8)
#define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
#define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 31d0f8b64ec0..7e8dd194aa0f 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -552,6 +552,9 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
return true;
+ if (flags & PIN_OFFSET_GUARD && vma->guard < (flags & PIN_OFFSET_MASK))
+ return true;
+
return false;
}
@@ -629,6 +632,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND));
GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
+ GEM_BUG_ON(hweight64(flags & (PIN_OFFSET_GUARD | PIN_OFFSET_FIXED | PIN_OFFSET_BIAS)) > 1);
size = max(size, vma->size);
alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
@@ -643,6 +647,10 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(!is_power_of_2(alignment));
guard = vma->guard; /* retain guard across rebinds */
+ if (flags & PIN_OFFSET_GUARD) {
+ GEM_BUG_ON(overflows_type(flags & PIN_OFFSET_MASK, u32));
+ guard = max_t(u32, guard, flags & PIN_OFFSET_MASK);
+ }
guard = ALIGN(guard, alignment);
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
2021-02-15 15:56 ` [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma Chris Wilson
2021-02-15 15:56 ` [Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround Chris Wilson
@ 2021-02-15 17:38 ` Patchwork
2021-02-15 19:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (6 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-02-15 17:38 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3393 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size
URL : https://patchwork.freedesktop.org/series/87102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9777 -> Patchwork_19681
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/index.html
Known issues
------------
Here are the changes found in Patchwork_19681 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600: NOTRUN -> [SKIP][3] ([fdo#109271]) +34 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/fi-snb-2600/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][4] -> [FAIL][5] ([i915#1161] / [i915#262])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/fi-snb-2600/igt@kms_chamelium@hdmi-crc-fast.html
#### Possible fixes ####
* igt@gem_render_tiled_blits@basic:
- fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (44 -> 39)
------------------------------
Additional (1): fi-snb-2600
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-ehl-2 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9777 -> Patchwork_19681
CI-20190529: 20190529
CI_DRM_9777: 5fd19bfd239ec997f3bcac75d6af8c9340066b12 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6003: 627cc5353535d61fa33c5f7ff7e64f154c84f10a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19681: 9c3df91baf50b31410603beded019bc7ed2d37f3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9c3df91baf50 drm/i915: Refine VT-d scanout workaround
0915f5c609a1 drm/i915: Introduce guard pages to i915_vma
7c5ce7841d01 drm/i915: Wrap all access to i915_vma.node.start|size
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/index.html
[-- Attachment #1.2: Type: text/html, Size: 4251 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma
2021-02-15 15:56 ` [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma Chris Wilson
@ 2021-02-15 18:04 ` Matthew Auld
2021-02-15 18:15 ` Chris Wilson
2021-02-15 20:33 ` [Intel-gfx] [PATCH] " Chris Wilson
1 sibling, 1 reply; 25+ messages in thread
From: Matthew Auld @ 2021-02-15 18:04 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld
On Mon, 15 Feb 2021 at 15:56, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Introduce the concept of padding the i915_vma with guard pages before
> and aft. The major consequence is that all ordinary uses of i915_vma
> must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
> directly, as the drm_mm_node will include the guard pages that surround
> our object.
>
> The biggest connundrum is how exactly to mix requesting a fixed address
> with guard pages, particularly through the existing uABI. The user does
> not know about guard pages, so such must be transparent to the user, and
> so the execobj.offset must be that of the object itself excluding the
> guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
> The caveat is that some placements will be impossible with guard pages,
> as wrap arounds need to be avoided, and the vma itself will require a
> larger node. We must we not report EINVAL but ENOSPC as these are
> unavailable locations within the GTT rather than conflicting user
> requirements.
>
> In the next patch, we start using guard pages for scanout objects. While
> these are limited to GGTT vma, on a few platforms these vma (or at least
> an alias of the vma) is shared with userspace, so we may leak the
> existence of such guards if we are not careful to ensure that the
> execobj.offset is transparent and excludes the guards. (On such platforms
> like ivb, without full-ppgtt, userspace has to use relocations so the
> presence of more untouchable regions within its GTT such be of no further
> issue.)
>
> v2: Include the guard range in the overflow checks and placement
> restrictions.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++++++++++--
> drivers/gpu/drm/i915/i915_vma.c | 28 ++++++++++++++++++++++-----
> drivers/gpu/drm/i915/i915_vma.h | 5 +++--
> drivers/gpu/drm/i915/i915_vma_types.h | 3 ++-
> 4 files changed, 38 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index c5803c434d33..6b326138e765 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -238,8 +238,12 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
>
> gte = (gen8_pte_t __iomem *)ggtt->gsm;
> gte += vma->node.start / I915_GTT_PAGE_SIZE;
> - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
>
> + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> + while (gte < end)
> + gen8_set_pte(gte++, vm->scratch[0]->encode);
> +
> + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> for_each_sgt_daddr(addr, iter, vma->pages)
> gen8_set_pte(gte++, pte_encode | addr);
> GEM_BUG_ON(gte > end);
> @@ -289,8 +293,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
>
> gte = (gen6_pte_t __iomem *)ggtt->gsm;
> gte += vma->node.start / I915_GTT_PAGE_SIZE;
> - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
>
> + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> + while (gte < end)
> + gen8_set_pte(gte++, vm->scratch[0]->encode);
> +
> + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> for_each_sgt_daddr(addr, iter, vma->pages)
> iowrite32(vm->pte_encode(addr, level, flags), gte++);
> GEM_BUG_ON(gte > end);
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 748f5ea1ba04..31d0f8b64ec0 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -623,7 +623,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
> static int
> i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> {
> - unsigned long color;
> + unsigned long color, guard;
> u64 start, end;
> int ret;
>
> @@ -631,7 +631,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
>
> size = max(size, vma->size);
> - alignment = max(alignment, vma->display_alignment);
> + alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
> if (flags & PIN_MAPPABLE) {
> size = max_t(typeof(size), size, vma->fence_size);
> alignment = max_t(typeof(alignment),
> @@ -642,6 +642,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
> GEM_BUG_ON(!is_power_of_2(alignment));
>
> + guard = vma->guard; /* retain guard across rebinds */
> + guard = ALIGN(guard, alignment);
> +
> start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
> GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
>
> @@ -651,12 +654,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> if (flags & PIN_ZONE_4G)
> end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);
> GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> + GEM_BUG_ON(2 * guard > end);
>
> /* If binding the object/GGTT view requires more space than the entire
> * aperture has, reject it early before evicting everything in a vain
> * attempt to find space.
> */
> - if (size > end) {
> + if (size > end - 2 * guard) {
> DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu > %s aperture=%llu\n",
> size, flags & PIN_MAPPABLE ? "mappable" : "total",
> end);
> @@ -669,16 +673,29 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
>
> if (flags & PIN_OFFSET_FIXED) {
> u64 offset = flags & PIN_OFFSET_MASK;
> +
> if (!IS_ALIGNED(offset, alignment) ||
> range_overflows(offset, size, end))
> return -EINVAL;
>
> + /*
> + * The caller knows not of the guard added by others and
> + * requests for the offset of the start of its buffer
> + * to be fixed, which may not be the same as the position
> + * of the vma->node due to the guard pages.
> + */
> + if (offset < guard || offset > end - size - 2 * guard)
(offset < guard || offset + size > end - guard)?
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround
2021-02-15 15:56 ` [Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround Chris Wilson
@ 2021-02-15 18:07 ` Matthew Auld
2021-02-20 11:08 ` [Intel-gfx] [PATCH] " Chris Wilson
2021-02-20 11:10 ` Chris Wilson
2 siblings, 0 replies; 25+ messages in thread
From: Matthew Auld @ 2021-02-15 18:07 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld
On Mon, 15 Feb 2021 at 15:56, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> VT-d may cause overfetch of the scanout PTE, both before and after the
> vma (depending on the scanout orientation). bspec recommends that we
> provide a tile-row in either directions, and suggests using 160 PTE,
> warning that the accesses will wrap around the ends of the GGTT.
> Currently, we fill the entire GGTT with scratch pages when using VT-d to
> always ensure there are valid entries around every vma, including
> scanout. However, writing every PTE is slow as on recent devices we
> perform 8MiB of uncached writes, incurring an extra 100ms during resume.
>
> If instead we focus on only putting guard pages around scanout, we can
> avoid touching the whole GGTT. To avoid having to introduce extra nodes
> around each scanout vma, we adjust the scanout drm_mm_node to be smaller
> than the allocated space, and fixup the extra PTE during dma binding.
>
> v2: Move the guard from modifying drm_mm_node.start which is still used
> by the drm_mm itself, into an adjustment of node.start at the point of
> use.
>
> v3: Pass the requested guard padding from the caller, so we can drop the
> VT-d w/a knowledge from the i915_vma allocator.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com> # v2
Looks good,
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma
2021-02-15 18:04 ` Matthew Auld
@ 2021-02-15 18:15 ` Chris Wilson
2021-02-15 19:31 ` Matthew Auld
0 siblings, 1 reply; 25+ messages in thread
From: Chris Wilson @ 2021-02-15 18:15 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development, Matthew Auld
Quoting Matthew Auld (2021-02-15 18:04:08)
> On Mon, 15 Feb 2021 at 15:56, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > Introduce the concept of padding the i915_vma with guard pages before
> > and aft. The major consequence is that all ordinary uses of i915_vma
> > must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
> > directly, as the drm_mm_node will include the guard pages that surround
> > our object.
> >
> > The biggest connundrum is how exactly to mix requesting a fixed address
> > with guard pages, particularly through the existing uABI. The user does
> > not know about guard pages, so such must be transparent to the user, and
> > so the execobj.offset must be that of the object itself excluding the
> > guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
> > The caveat is that some placements will be impossible with guard pages,
> > as wrap arounds need to be avoided, and the vma itself will require a
> > larger node. We must we not report EINVAL but ENOSPC as these are
> > unavailable locations within the GTT rather than conflicting user
> > requirements.
> >
> > In the next patch, we start using guard pages for scanout objects. While
> > these are limited to GGTT vma, on a few platforms these vma (or at least
> > an alias of the vma) is shared with userspace, so we may leak the
> > existence of such guards if we are not careful to ensure that the
> > execobj.offset is transparent and excludes the guards. (On such platforms
> > like ivb, without full-ppgtt, userspace has to use relocations so the
> > presence of more untouchable regions within its GTT such be of no further
> > issue.)
> >
> > v2: Include the guard range in the overflow checks and placement
> > restrictions.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Matthew Auld <matthew.auld@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++++++++++--
> > drivers/gpu/drm/i915/i915_vma.c | 28 ++++++++++++++++++++++-----
> > drivers/gpu/drm/i915/i915_vma.h | 5 +++--
> > drivers/gpu/drm/i915/i915_vma_types.h | 3 ++-
> > 4 files changed, 38 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > index c5803c434d33..6b326138e765 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > @@ -238,8 +238,12 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
> >
> > gte = (gen8_pte_t __iomem *)ggtt->gsm;
> > gte += vma->node.start / I915_GTT_PAGE_SIZE;
> > - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
> >
> > + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> > + while (gte < end)
> > + gen8_set_pte(gte++, vm->scratch[0]->encode);
> > +
> > + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> > for_each_sgt_daddr(addr, iter, vma->pages)
> > gen8_set_pte(gte++, pte_encode | addr);
> > GEM_BUG_ON(gte > end);
> > @@ -289,8 +293,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
> >
> > gte = (gen6_pte_t __iomem *)ggtt->gsm;
> > gte += vma->node.start / I915_GTT_PAGE_SIZE;
> > - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
> >
> > + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> > + while (gte < end)
> > + gen8_set_pte(gte++, vm->scratch[0]->encode);
> > +
> > + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> > for_each_sgt_daddr(addr, iter, vma->pages)
> > iowrite32(vm->pte_encode(addr, level, flags), gte++);
> > GEM_BUG_ON(gte > end);
> > diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> > index 748f5ea1ba04..31d0f8b64ec0 100644
> > --- a/drivers/gpu/drm/i915/i915_vma.c
> > +++ b/drivers/gpu/drm/i915/i915_vma.c
> > @@ -623,7 +623,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
> > static int
> > i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > {
> > - unsigned long color;
> > + unsigned long color, guard;
> > u64 start, end;
> > int ret;
> >
> > @@ -631,7 +631,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
> >
> > size = max(size, vma->size);
> > - alignment = max(alignment, vma->display_alignment);
> > + alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
> > if (flags & PIN_MAPPABLE) {
> > size = max_t(typeof(size), size, vma->fence_size);
> > alignment = max_t(typeof(alignment),
> > @@ -642,6 +642,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
> > GEM_BUG_ON(!is_power_of_2(alignment));
> >
> > + guard = vma->guard; /* retain guard across rebinds */
> > + guard = ALIGN(guard, alignment);
> > +
> > start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
> > GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
> >
> > @@ -651,12 +654,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > if (flags & PIN_ZONE_4G)
> > end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);
> > GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> > + GEM_BUG_ON(2 * guard > end);
> >
> > /* If binding the object/GGTT view requires more space than the entire
> > * aperture has, reject it early before evicting everything in a vain
> > * attempt to find space.
> > */
> > - if (size > end) {
> > + if (size > end - 2 * guard) {
> > DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu > %s aperture=%llu\n",
> > size, flags & PIN_MAPPABLE ? "mappable" : "total",
> > end);
> > @@ -669,16 +673,29 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> >
> > if (flags & PIN_OFFSET_FIXED) {
> > u64 offset = flags & PIN_OFFSET_MASK;
> > +
> > if (!IS_ALIGNED(offset, alignment) ||
> > range_overflows(offset, size, end))
> > return -EINVAL;
> >
> > + /*
> > + * The caller knows not of the guard added by others and
> > + * requests for the offset of the start of its buffer
> > + * to be fixed, which may not be the same as the position
> > + * of the vma->node due to the guard pages.
> > + */
> > + if (offset < guard || offset > end - size - 2 * guard)
>
> (offset < guard || offset + size > end - guard)?
Padding is afterwards as well as before; so total size grows by 2 *
guard. And since VT-d says that the overfetch wraps past the end of the
GTT to the front, we can't simply shrink the node if it abuts the end.
So I'm confident the right check is end - size - 2*guard, and since we
already check that 2*guard is less than end, and size is less than end
minus the 2*guard, overflows have been caught.
The only real bother is the restriction there is against the end of the
GTT and not the end of the pin zone. C'est la vie.
-Chris
>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma
2021-02-15 18:15 ` Chris Wilson
@ 2021-02-15 19:31 ` Matthew Auld
2021-02-15 20:29 ` Chris Wilson
0 siblings, 1 reply; 25+ messages in thread
From: Matthew Auld @ 2021-02-15 19:31 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld
On Mon, 15 Feb 2021 at 18:15, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Quoting Matthew Auld (2021-02-15 18:04:08)
> > On Mon, 15 Feb 2021 at 15:56, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > >
> > > Introduce the concept of padding the i915_vma with guard pages before
> > > and aft. The major consequence is that all ordinary uses of i915_vma
> > > must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
> > > directly, as the drm_mm_node will include the guard pages that surround
> > > our object.
> > >
> > > The biggest connundrum is how exactly to mix requesting a fixed address
> > > with guard pages, particularly through the existing uABI. The user does
> > > not know about guard pages, so such must be transparent to the user, and
> > > so the execobj.offset must be that of the object itself excluding the
> > > guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
> > > The caveat is that some placements will be impossible with guard pages,
> > > as wrap arounds need to be avoided, and the vma itself will require a
> > > larger node. We must we not report EINVAL but ENOSPC as these are
> > > unavailable locations within the GTT rather than conflicting user
> > > requirements.
> > >
> > > In the next patch, we start using guard pages for scanout objects. While
> > > these are limited to GGTT vma, on a few platforms these vma (or at least
> > > an alias of the vma) is shared with userspace, so we may leak the
> > > existence of such guards if we are not careful to ensure that the
> > > execobj.offset is transparent and excludes the guards. (On such platforms
> > > like ivb, without full-ppgtt, userspace has to use relocations so the
> > > presence of more untouchable regions within its GTT such be of no further
> > > issue.)
> > >
> > > v2: Include the guard range in the overflow checks and placement
> > > restrictions.
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Matthew Auld <matthew.auld@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++++++++++--
> > > drivers/gpu/drm/i915/i915_vma.c | 28 ++++++++++++++++++++++-----
> > > drivers/gpu/drm/i915/i915_vma.h | 5 +++--
> > > drivers/gpu/drm/i915/i915_vma_types.h | 3 ++-
> > > 4 files changed, 38 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > index c5803c434d33..6b326138e765 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > @@ -238,8 +238,12 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
> > >
> > > gte = (gen8_pte_t __iomem *)ggtt->gsm;
> > > gte += vma->node.start / I915_GTT_PAGE_SIZE;
> > > - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
> > >
> > > + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> > > + while (gte < end)
> > > + gen8_set_pte(gte++, vm->scratch[0]->encode);
> > > +
> > > + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> > > for_each_sgt_daddr(addr, iter, vma->pages)
> > > gen8_set_pte(gte++, pte_encode | addr);
> > > GEM_BUG_ON(gte > end);
> > > @@ -289,8 +293,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
> > >
> > > gte = (gen6_pte_t __iomem *)ggtt->gsm;
> > > gte += vma->node.start / I915_GTT_PAGE_SIZE;
> > > - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
> > >
> > > + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> > > + while (gte < end)
> > > + gen8_set_pte(gte++, vm->scratch[0]->encode);
> > > +
> > > + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> > > for_each_sgt_daddr(addr, iter, vma->pages)
> > > iowrite32(vm->pte_encode(addr, level, flags), gte++);
> > > GEM_BUG_ON(gte > end);
> > > diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> > > index 748f5ea1ba04..31d0f8b64ec0 100644
> > > --- a/drivers/gpu/drm/i915/i915_vma.c
> > > +++ b/drivers/gpu/drm/i915/i915_vma.c
> > > @@ -623,7 +623,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
> > > static int
> > > i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > > {
> > > - unsigned long color;
> > > + unsigned long color, guard;
> > > u64 start, end;
> > > int ret;
> > >
> > > @@ -631,7 +631,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > > GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
> > >
> > > size = max(size, vma->size);
> > > - alignment = max(alignment, vma->display_alignment);
> > > + alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
> > > if (flags & PIN_MAPPABLE) {
> > > size = max_t(typeof(size), size, vma->fence_size);
> > > alignment = max_t(typeof(alignment),
> > > @@ -642,6 +642,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > > GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
> > > GEM_BUG_ON(!is_power_of_2(alignment));
> > >
> > > + guard = vma->guard; /* retain guard across rebinds */
> > > + guard = ALIGN(guard, alignment);
> > > +
> > > start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
> > > GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
> > >
> > > @@ -651,12 +654,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > > if (flags & PIN_ZONE_4G)
> > > end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);
> > > GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> > > + GEM_BUG_ON(2 * guard > end);
> > >
> > > /* If binding the object/GGTT view requires more space than the entire
> > > * aperture has, reject it early before evicting everything in a vain
> > > * attempt to find space.
> > > */
> > > - if (size > end) {
> > > + if (size > end - 2 * guard) {
> > > DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu > %s aperture=%llu\n",
> > > size, flags & PIN_MAPPABLE ? "mappable" : "total",
> > > end);
> > > @@ -669,16 +673,29 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > >
> > > if (flags & PIN_OFFSET_FIXED) {
> > > u64 offset = flags & PIN_OFFSET_MASK;
> > > +
> > > if (!IS_ALIGNED(offset, alignment) ||
> > > range_overflows(offset, size, end))
> > > return -EINVAL;
> > >
> > > + /*
> > > + * The caller knows not of the guard added by others and
> > > + * requests for the offset of the start of its buffer
> > > + * to be fixed, which may not be the same as the position
> > > + * of the vma->node due to the guard pages.
> > > + */
> > > + if (offset < guard || offset > end - size - 2 * guard)
> >
> > (offset < guard || offset + size > end - guard)?
>
> Padding is afterwards as well as before; so total size grows by 2 *
> guard. And since VT-d says that the overfetch wraps past the end of the
> GTT to the front, we can't simply shrink the node if it abuts the end.
>
> So I'm confident the right check is end - size - 2*guard, and since we
> already check that 2*guard is less than end, and size is less than end
> minus the 2*guard, overflows have been caught.
I thought here the range [offset, offset + size] sits in between both
sides of the padding. The offset < guard checks the left side, and so
offset > end - size - guard will check the right side, but I didn't
see a check for size > guard anywhere, hence the above.
>
> The only real bother is the restriction there is against the end of the
> GTT and not the end of the pin zone. C'est la vie.
> -Chris
>
>
> >
> > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
` (2 preceding siblings ...)
2021-02-15 17:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size Patchwork
@ 2021-02-15 19:49 ` Patchwork
2021-02-15 21:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev2) Patchwork
` (5 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-02-15 19:49 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30303 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size
URL : https://patchwork.freedesktop.org/series/87102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9777_full -> Patchwork_19681_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19681_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-snb2/igt@gem_ctx_persistence@engines-hostile-preempt.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][2] -> [TIMEOUT][3] ([i915#1037] / [i915#2481])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb5/igt@gem_eio@unwedge-stress.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][4] ([i915#2846])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][5] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk7/igt@gem_exec_fair@basic-none-solo@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-glk4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb7/igt@gem_exec_fair@basic-pace@vcs1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-tglb3/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_params@invalid-fence-in-submit:
- shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([i915#2055])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-hsw6/igt@gem_exec_params@invalid-fence-in-submit.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-hsw1/igt@gem_exec_params@invalid-fence-in-submit.html
* igt@gem_exec_params@secure-non-master:
- shard-iclb: NOTRUN -> [SKIP][15] ([fdo#112283])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@gem_exec_params@secure-non-master.html
* igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2389])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb1/igt@gem_exec_reloc@basic-many-active@vcs1.html
* igt@gem_exec_reloc@basic-parallel:
- shard-kbl: NOTRUN -> [TIMEOUT][17] ([i915#1729])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@gem_exec_reloc@basic-parallel.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl1/igt@gem_huc_copy@huc-copy.html
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl6/igt@gem_huc_copy@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-skl: NOTRUN -> [WARN][20] ([i915#2658])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl3/igt@gem_pread@exhaustion.html
* igt@gem_softpin@full:
- shard-snb: NOTRUN -> [SKIP][21] ([fdo#109271]) +160 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-snb2/igt@gem_softpin@full.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][22] ([i915#3002])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@process-exit-mmap@gtt:
- shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#1699]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@gem_userptr_blits@process-exit-mmap@gtt.html
* igt@gem_userptr_blits@process-exit-mmap@wb:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#1699]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl2/igt@gem_userptr_blits@process-exit-mmap@wb.html
* igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#112306])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@gen9_exec_parse@secure-batches.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][26] ([i915#1886] / [i915#2291])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl3/igt@i915_selftest@live@gt_pm.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][27] -> [FAIL][28] ([i915#2574])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-tglb8/igt@kms_async_flips@test-time-stamp.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#110723])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_chamelium@dp-mode-timings:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +26 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl2/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_color@pipe-a-ctm-0-25:
- shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl2/igt@kms_color@pipe-a-ctm-0-25.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl10/igt@kms_color@pipe-a-ctm-0-25.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109284] / [fdo#111827])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-a-degamma:
- shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +16 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl1/igt@kms_color_chamelium@pipe-a-degamma.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-snb: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +9 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-snb2/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-skl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +4 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl3/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][37] ([i915#1319])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl1/igt@kms_content_protection@atomic.html
- shard-apl: NOTRUN -> [TIMEOUT][38] ([i915#1319])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl7/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109300] / [fdo#111066])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][40] ([i915#2105])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl2/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-random:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#54]) +6 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-random:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [fdo#109279])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271]) +176 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109274] / [fdo#109278]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: NOTRUN -> [FAIL][46] ([i915#2346])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109274]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][48] -> [FAIL][49] ([i915#79])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [PASS][50] -> [FAIL][51] ([i915#79])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#2122])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-skl: NOTRUN -> [FAIL][54] ([i915#2628])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-kbl: NOTRUN -> [FAIL][55] ([i915#2641])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#2672])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271]) +42 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][58] ([fdo#109280])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- shard-snb: [PASS][59] -> [SKIP][60] ([fdo#109271]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-snb7/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-snb2/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#533]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#533]) +3 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][63] -> [INCOMPLETE][64] ([i915#198]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][67] -> [FAIL][68] ([fdo#108145] / [i915#265]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][69] ([fdo#108145] / [i915#265]) +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-min:
- shard-iclb: NOTRUN -> [SKIP][70] ([fdo#109278]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-min.html
* igt@kms_plane_scaling@scaler-with-pixel-format@pipe-b-scaler-with-pixel-format:
- shard-glk: [PASS][71] -> [DMESG-WARN][72] ([i915#118] / [i915#95])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk6/igt@kms_plane_scaling@scaler-with-pixel-format@pipe-b-scaler-with-pixel-format.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-glk8/igt@kms_plane_scaling@scaler-with-pixel-format@pipe-b-scaler-with-pixel-format.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +5 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658]) +4 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-iclb: NOTRUN -> [SKIP][75] ([i915#658])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][76] -> [SKIP][77] ([fdo#109441]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2437]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@kms_writeback@writeback-pixel-formats.html
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2437])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl2/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271]) +254 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl7/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@perf@polling:
- shard-skl: [PASS][81] -> [FAIL][82] ([i915#1542])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl10/igt@perf@polling.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl4/igt@perf@polling.html
* igt@perf@polling-parameterized:
- shard-hsw: [PASS][83] -> [FAIL][84] ([i915#1542])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-hsw6/igt@perf@polling-parameterized.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-hsw8/igt@perf@polling-parameterized.html
* igt@prime_nv_api@nv_i915_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109291])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb8/igt@prime_nv_api@nv_i915_import_twice_check_flink_name.html
* igt@sysfs_clients@busy@vcs1:
- shard-kbl: [PASS][86] -> [FAIL][87] ([i915#3019])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-kbl6/igt@sysfs_clients@busy@vcs1.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl2/igt@sysfs_clients@busy@vcs1.html
* igt@sysfs_clients@recycle:
- shard-snb: [PASS][88] -> [FAIL][89] ([i915#3028])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-snb5/igt@sysfs_clients@recycle.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-snb7/igt@sysfs_clients@recycle.html
* igt@sysfs_clients@sema-10@vcs0:
- shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#3026]) +3 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl3/igt@sysfs_clients@sema-10@vcs0.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][91] ([i915#1037] / [i915#3063]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb6/igt@gem_eio@unwedge-stress.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-tglb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@hang:
- shard-iclb: [INCOMPLETE][93] ([i915#1895] / [i915#2295] / [i915#3031]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb1/igt@gem_exec_balancer@hang.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb8/igt@gem_exec_balancer@hang.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-apl: [SKIP][95] ([fdo#109271]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-apl2/igt@gem_exec_fair@basic-flow@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-apl6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][97] ([i915#2842]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-iclb: [FAIL][99] ([i915#2842]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [FAIL][101] ([i915#2842]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk5/igt@gem_exec_fair@basic-pace@vcs0.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-glk5/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][103] ([i915#2849]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-iclb: [DMESG-WARN][105] ([i915#2803]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb2/igt@gem_exec_schedule@u-fairslice@vcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@gem_exec_schedule@u-fairslice@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][107] ([i915#2190]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-tglb7/igt@gem_huc_copy@huc-copy.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [INCOMPLETE][109] ([i915#198]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl5/igt@i915_suspend@sysfs-reader.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl2/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-skl: [FAIL][111] ([i915#54]) -> [PASS][112] +5 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- shard-skl: [DMESG-WARN][113] ([i915#1982]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl2/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl7/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2:
- shard-glk: [FAIL][115] ([i915#79]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][117] ([i915#1188]) -> [PASS][118] +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][119] ([fdo#109441]) -> [PASS][120] +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb3/igt@kms_psr@psr2_no_drrs.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@sysfs_clients@recycle:
- shard-hsw: [FAIL][121] ([i915#3028]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-hsw1/igt@sysfs_clients@recycle.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-hsw4/igt@sysfs_clients@recycle.html
- shard-iclb: [FAIL][123] ([i915#3028]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb3/igt@sysfs_clients@recycle.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb2/igt@sysfs_clients@recycle.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [FAIL][125] ([i915#2851]) -> [FAIL][126] ([i915#2842])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb7/igt@gem_exec_fair@basic-pace@rcs0.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-tglb3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][127] ([i915#658]) -> [SKIP][128] ([i915#588])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb3/igt@i915_pm_dc@dc3co-vpb-simulation.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][129] ([i915#2684]) -> [WARN][130] ([i915#1804] / [i915#2684])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-iclb: [SKIP][131] ([i915#658]) -> [SKIP][132] ([i915#2920]) +2 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb7/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][133] ([i915#2920]) -> [SKIP][134] ([i915#658]) +1 similar issue
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: [FAIL][135] ([i915#2295]) -> ([FAIL][136], [FAIL][137]) ([i915#2295] / [i915#3002])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-kbl2/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl7/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-kbl4/igt@runner@aborted.html
- shard-iclb: ([FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141]) ([i915#2295] / [i915#2426] / [i915#2724] / [i915#3002]) -> ([FAIL][142], [FAIL][143], [FAIL][144]) ([i915#2295] / [i915#2724] / [i915#3002])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb4/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb2/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb6/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb8/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb7/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb7/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-iclb3/igt@runner@aborted.html
- shard-snb: ([FAIL][145], [FAIL][146], [FAIL][147]) ([i915#2292] / [i915#2426] / [i915#3002] / [i915#698]) -> [FAIL][148] ([i915#3002] / [i915#698])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-snb7/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-snb7/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-snb6/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/shard-snb2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19681/index.html
[-- Attachment #1.2: Type: text/html, Size: 35161 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma
2021-02-15 19:31 ` Matthew Auld
@ 2021-02-15 20:29 ` Chris Wilson
0 siblings, 0 replies; 25+ messages in thread
From: Chris Wilson @ 2021-02-15 20:29 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development, Matthew Auld
Quoting Matthew Auld (2021-02-15 19:31:39)
> On Mon, 15 Feb 2021 at 18:15, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > Quoting Matthew Auld (2021-02-15 18:04:08)
> > > On Mon, 15 Feb 2021 at 15:56, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > > >
> > > > Introduce the concept of padding the i915_vma with guard pages before
> > > > and aft. The major consequence is that all ordinary uses of i915_vma
> > > > must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
> > > > directly, as the drm_mm_node will include the guard pages that surround
> > > > our object.
> > > >
> > > > The biggest connundrum is how exactly to mix requesting a fixed address
> > > > with guard pages, particularly through the existing uABI. The user does
> > > > not know about guard pages, so such must be transparent to the user, and
> > > > so the execobj.offset must be that of the object itself excluding the
> > > > guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
> > > > The caveat is that some placements will be impossible with guard pages,
> > > > as wrap arounds need to be avoided, and the vma itself will require a
> > > > larger node. We must we not report EINVAL but ENOSPC as these are
> > > > unavailable locations within the GTT rather than conflicting user
> > > > requirements.
> > > >
> > > > In the next patch, we start using guard pages for scanout objects. While
> > > > these are limited to GGTT vma, on a few platforms these vma (or at least
> > > > an alias of the vma) is shared with userspace, so we may leak the
> > > > existence of such guards if we are not careful to ensure that the
> > > > execobj.offset is transparent and excludes the guards. (On such platforms
> > > > like ivb, without full-ppgtt, userspace has to use relocations so the
> > > > presence of more untouchable regions within its GTT such be of no further
> > > > issue.)
> > > >
> > > > v2: Include the guard range in the overflow checks and placement
> > > > restrictions.
> > > >
> > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > Cc: Matthew Auld <matthew.auld@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++++++++++--
> > > > drivers/gpu/drm/i915/i915_vma.c | 28 ++++++++++++++++++++++-----
> > > > drivers/gpu/drm/i915/i915_vma.h | 5 +++--
> > > > drivers/gpu/drm/i915/i915_vma_types.h | 3 ++-
> > > > 4 files changed, 38 insertions(+), 10 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > > index c5803c434d33..6b326138e765 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > > @@ -238,8 +238,12 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
> > > >
> > > > gte = (gen8_pte_t __iomem *)ggtt->gsm;
> > > > gte += vma->node.start / I915_GTT_PAGE_SIZE;
> > > > - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
> > > >
> > > > + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> > > > + while (gte < end)
> > > > + gen8_set_pte(gte++, vm->scratch[0]->encode);
> > > > +
> > > > + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> > > > for_each_sgt_daddr(addr, iter, vma->pages)
> > > > gen8_set_pte(gte++, pte_encode | addr);
> > > > GEM_BUG_ON(gte > end);
> > > > @@ -289,8 +293,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
> > > >
> > > > gte = (gen6_pte_t __iomem *)ggtt->gsm;
> > > > gte += vma->node.start / I915_GTT_PAGE_SIZE;
> > > > - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
> > > >
> > > > + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> > > > + while (gte < end)
> > > > + gen8_set_pte(gte++, vm->scratch[0]->encode);
> > > > +
> > > > + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> > > > for_each_sgt_daddr(addr, iter, vma->pages)
> > > > iowrite32(vm->pte_encode(addr, level, flags), gte++);
> > > > GEM_BUG_ON(gte > end);
> > > > diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> > > > index 748f5ea1ba04..31d0f8b64ec0 100644
> > > > --- a/drivers/gpu/drm/i915/i915_vma.c
> > > > +++ b/drivers/gpu/drm/i915/i915_vma.c
> > > > @@ -623,7 +623,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
> > > > static int
> > > > i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > > > {
> > > > - unsigned long color;
> > > > + unsigned long color, guard;
> > > > u64 start, end;
> > > > int ret;
> > > >
> > > > @@ -631,7 +631,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > > > GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
> > > >
> > > > size = max(size, vma->size);
> > > > - alignment = max(alignment, vma->display_alignment);
> > > > + alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
> > > > if (flags & PIN_MAPPABLE) {
> > > > size = max_t(typeof(size), size, vma->fence_size);
> > > > alignment = max_t(typeof(alignment),
> > > > @@ -642,6 +642,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > > > GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
> > > > GEM_BUG_ON(!is_power_of_2(alignment));
> > > >
> > > > + guard = vma->guard; /* retain guard across rebinds */
> > > > + guard = ALIGN(guard, alignment);
> > > > +
> > > > start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
> > > > GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
> > > >
> > > > @@ -651,12 +654,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > > > if (flags & PIN_ZONE_4G)
> > > > end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);
> > > > GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> > > > + GEM_BUG_ON(2 * guard > end);
> > > >
> > > > /* If binding the object/GGTT view requires more space than the entire
> > > > * aperture has, reject it early before evicting everything in a vain
> > > > * attempt to find space.
> > > > */
> > > > - if (size > end) {
> > > > + if (size > end - 2 * guard) {
> > > > DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu > %s aperture=%llu\n",
> > > > size, flags & PIN_MAPPABLE ? "mappable" : "total",
> > > > end);
> > > > @@ -669,16 +673,29 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > > >
> > > > if (flags & PIN_OFFSET_FIXED) {
> > > > u64 offset = flags & PIN_OFFSET_MASK;
> > > > +
> > > > if (!IS_ALIGNED(offset, alignment) ||
> > > > range_overflows(offset, size, end))
> > > > return -EINVAL;
> > > >
> > > > + /*
> > > > + * The caller knows not of the guard added by others and
> > > > + * requests for the offset of the start of its buffer
> > > > + * to be fixed, which may not be the same as the position
> > > > + * of the vma->node due to the guard pages.
> > > > + */
> > > > + if (offset < guard || offset > end - size - 2 * guard)
> > >
> > > (offset < guard || offset + size > end - guard)?
> >
> > Padding is afterwards as well as before; so total size grows by 2 *
> > guard. And since VT-d says that the overfetch wraps past the end of the
> > GTT to the front, we can't simply shrink the node if it abuts the end.
> >
> > So I'm confident the right check is end - size - 2*guard, and since we
> > already check that 2*guard is less than end, and size is less than end
> > minus the 2*guard, overflows have been caught.
>
> I thought here the range [offset, offset + size] sits in between both
> sides of the padding.
Yes.
> The offset < guard checks the left side,
Yes.
> and so
> offset > end - size - guard will check the right side,
D'oh. You're right. Since the user offset is itself node.start + guard.
> but I didn't
> see a check for size > guard anywhere, hence the above.
size here is still the user size, which is independent of the guard, so
at this point there's no interaction between size and guard, we just
need to check the offset + size + guard is within range.
We have checked that end - size - 2*guard does not overflow, so we also
know that end - size - guard will not overflow. But as we have checked
for overflows already, we can use whatever construction looks more
natural.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Introduce guard pages to i915_vma
2021-02-15 15:56 ` [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma Chris Wilson
2021-02-15 18:04 ` Matthew Auld
@ 2021-02-15 20:33 ` Chris Wilson
1 sibling, 0 replies; 25+ messages in thread
From: Chris Wilson @ 2021-02-15 20:33 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld, Chris Wilson
Introduce the concept of padding the i915_vma with guard pages before
and aft. The major consequence is that all ordinary uses of i915_vma
must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
directly, as the drm_mm_node will include the guard pages that surround
our object.
The biggest connundrum is how exactly to mix requesting a fixed address
with guard pages, particularly through the existing uABI. The user does
not know about guard pages, so such must be transparent to the user, and
so the execobj.offset must be that of the object itself excluding the
guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
The caveat is that some placements will be impossible with guard pages,
as wrap arounds need to be avoided, and the vma itself will require a
larger node. We must we not report EINVAL but ENOSPC as these are
unavailable locations within the GTT rather than conflicting user
requirements.
In the next patch, we start using guard pages for scanout objects. While
these are limited to GGTT vma, on a few platforms these vma (or at least
an alias of the vma) is shared with userspace, so we may leak the
existence of such guards if we are not careful to ensure that the
execobj.offset is transparent and excludes the guards. (On such platforms
like ivb, without full-ppgtt, userspace has to use relocations so the
presence of more untouchable regions within its GTT such be of no further
issue.)
v2: Include the guard range in the overflow checks and placement
restrictions.
v3: Fix the check on the placement upper bound. The request user offset
is relative to the guard offset (not the node.start) and so we should
not include the initial guard offset again when computing the upper
bound of the node.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++++++++++--
drivers/gpu/drm/i915/i915_vma.c | 28 ++++++++++++++++++++++-----
drivers/gpu/drm/i915/i915_vma.h | 5 +++--
drivers/gpu/drm/i915/i915_vma_types.h | 3 ++-
4 files changed, 38 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index c5803c434d33..6b326138e765 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -238,8 +238,12 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
gte = (gen8_pte_t __iomem *)ggtt->gsm;
gte += vma->node.start / I915_GTT_PAGE_SIZE;
- end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
+ end = gte + vma->guard / I915_GTT_PAGE_SIZE;
+ while (gte < end)
+ gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+ end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, iter, vma->pages)
gen8_set_pte(gte++, pte_encode | addr);
GEM_BUG_ON(gte > end);
@@ -289,8 +293,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
gte = (gen6_pte_t __iomem *)ggtt->gsm;
gte += vma->node.start / I915_GTT_PAGE_SIZE;
- end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
+ end = gte + vma->guard / I915_GTT_PAGE_SIZE;
+ while (gte < end)
+ gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+ end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, iter, vma->pages)
iowrite32(vm->pte_encode(addr, level, flags), gte++);
GEM_BUG_ON(gte > end);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 748f5ea1ba04..01e62edf4704 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -623,7 +623,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
static int
i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
- unsigned long color;
+ unsigned long color, guard;
u64 start, end;
int ret;
@@ -631,7 +631,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
size = max(size, vma->size);
- alignment = max(alignment, vma->display_alignment);
+ alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
if (flags & PIN_MAPPABLE) {
size = max_t(typeof(size), size, vma->fence_size);
alignment = max_t(typeof(alignment),
@@ -642,6 +642,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
GEM_BUG_ON(!is_power_of_2(alignment));
+ guard = vma->guard; /* retain guard across rebinds */
+ guard = ALIGN(guard, alignment);
+
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
@@ -651,12 +654,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
if (flags & PIN_ZONE_4G)
end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);
GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
+ GEM_BUG_ON(2 * guard > end);
/* If binding the object/GGTT view requires more space than the entire
* aperture has, reject it early before evicting everything in a vain
* attempt to find space.
*/
- if (size > end) {
+ if (size > end - 2 * guard) {
DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu > %s aperture=%llu\n",
size, flags & PIN_MAPPABLE ? "mappable" : "total",
end);
@@ -669,16 +673,29 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
if (flags & PIN_OFFSET_FIXED) {
u64 offset = flags & PIN_OFFSET_MASK;
+
if (!IS_ALIGNED(offset, alignment) ||
range_overflows(offset, size, end))
return -EINVAL;
+ /*
+ * The caller knows not of the guard added by others and
+ * requests for the offset of the start of its buffer
+ * to be fixed, which may not be the same as the position
+ * of the vma->node due to the guard pages.
+ */
+ if (offset < guard || offset + size > end - guard)
+ return -ENOSPC;
+
ret = i915_gem_gtt_reserve(vma->vm, &vma->node,
- size, offset, color,
- flags);
+ size + 2 * guard,
+ offset - guard,
+ color, flags);
if (ret)
return ret;
} else {
+ size += 2 * guard;
+
/*
* We only support huge gtt pages through the 48b PPGTT,
* however we also don't want to force any alignment for
@@ -725,6 +742,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, color));
list_add_tail(&vma->vm_link, &vma->vm->bound_list);
+ vma->guard = guard;
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 3066d36b2ccd..5004ece1eb9a 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -113,12 +113,13 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
static inline u64 i915_vma_size(const struct i915_vma *vma)
{
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- return vma->node.size;
+ return vma->node.size - 2 * vma->guard;
}
static inline u64 __i915_vma_offset(const struct i915_vma *vma)
{
- return vma->node.start;
+ /* The actual start of the vma->pages is after the guard pages. */
+ return vma->node.start + vma->guard;
}
static inline u64 i915_vma_offset(const struct i915_vma *vma)
diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h
index f5cb848b7a7e..6e55a71543ea 100644
--- a/drivers/gpu/drm/i915/i915_vma_types.h
+++ b/drivers/gpu/drm/i915/i915_vma_types.h
@@ -182,14 +182,15 @@ struct i915_vma {
struct i915_fence_reg *fence;
u64 size;
- u64 display_alignment;
struct i915_page_sizes page_sizes;
/* mmap-offset associated with fencing for this vma */
struct i915_mmap_offset *mmo;
+ u32 guard; /* padding allocated around vma->pages within the node */
u32 fence_size;
u32 fence_alignment;
+ u32 display_alignment;
/**
* Count of the number of times this vma has been opened by different
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev2)
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
` (3 preceding siblings ...)
2021-02-15 19:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-02-15 21:24 ` Patchwork
2021-02-15 22:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-02-15 21:24 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2931 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev2)
URL : https://patchwork.freedesktop.org/series/87102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9777 -> Patchwork_19683
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/index.html
Known issues
------------
Here are the changes found in Patchwork_19683 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_sync@basic-all:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/fi-tgl-y/igt@gem_sync@basic-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/fi-tgl-y/igt@gem_sync@basic-all.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600: NOTRUN -> [SKIP][3] ([fdo#109271]) +34 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/fi-snb-2600/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/fi-snb-2600/igt@kms_chamelium@hdmi-crc-fast.html
#### Possible fixes ####
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (44 -> 40)
------------------------------
Additional (1): fi-snb-2600
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9777 -> Patchwork_19683
CI-20190529: 20190529
CI_DRM_9777: 5fd19bfd239ec997f3bcac75d6af8c9340066b12 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6003: 627cc5353535d61fa33c5f7ff7e64f154c84f10a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19683: 3e1d666b2e81e5de638c7f1c376e23490e65297b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3e1d666b2e81 drm/i915: Refine VT-d scanout workaround
481308fd811a drm/i915: Introduce guard pages to i915_vma
74f9d45ce050 drm/i915: Wrap all access to i915_vma.node.start|size
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/index.html
[-- Attachment #1.2: Type: text/html, Size: 3762 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev2)
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
` (4 preceding siblings ...)
2021-02-15 21:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev2) Patchwork
@ 2021-02-15 22:38 ` Patchwork
2021-02-17 14:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev3) Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-02-15 22:38 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30310 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev2)
URL : https://patchwork.freedesktop.org/series/87102/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9777_full -> Patchwork_19683_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19683_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19683_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19683_full:
### IGT changes ###
#### Possible regressions ####
* igt@syncobj_wait@wait-all-for-submit-snapshot:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl5/igt@syncobj_wait@wait-all-for-submit-snapshot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl8/igt@syncobj_wait@wait-all-for-submit-snapshot.html
Known issues
------------
Here are the changes found in Patchwork_19683_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl7/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@close-replace-race:
- shard-glk: [PASS][4] -> [TIMEOUT][5] ([i915#2918])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk9/igt@gem_ctx_persistence@close-replace-race.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-glk3/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +4 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-snb5/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#1037] / [i915#3063])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb8/igt@gem_eio@in-flight-contexts-10ms.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-tglb1/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][9] ([i915#1037] / [i915#180])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl4/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][10] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk7/igt@gem_exec_fair@basic-none-solo@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-glk2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb7/igt@gem_exec_fair@basic-pace@vcs1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-tglb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_params@secure-non-master:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#112283])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@gem_exec_params@secure-non-master.html
* igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-kbl: NOTRUN -> [FAIL][18] ([i915#2389]) +4 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl4/igt@gem_exec_reloc@basic-many-active@vcs0.html
* igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][19] ([i915#2389])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb2/igt@gem_exec_reloc@basic-many-active@vcs1.html
* igt@gem_exec_reloc@basic-parallel:
- shard-kbl: NOTRUN -> [TIMEOUT][20] ([i915#1729])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl7/igt@gem_exec_reloc@basic-parallel.html
* igt@gem_exec_schedule@u-fairslice-all:
- shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1610] / [i915#2803])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl10/igt@gem_exec_schedule@u-fairslice-all.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl10/igt@gem_exec_schedule@u-fairslice-all.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#2190])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl7/igt@gem_huc_copy@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-kbl: NOTRUN -> [WARN][24] ([i915#2658])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl2/igt@gem_pread@exhaustion.html
- shard-skl: NOTRUN -> [WARN][25] ([i915#2658])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl6/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@mmap-offset-invalidate-active@wb:
- shard-snb: NOTRUN -> [SKIP][26] ([fdo#109271]) +400 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-snb5/igt@gem_userptr_blits@mmap-offset-invalidate-active@wb.html
* igt@gem_userptr_blits@process-exit-mmap@wb:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#1699]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl6/igt@gem_userptr_blits@process-exit-mmap@wb.html
* igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][28] ([fdo#112306])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@gen9_exec_parse@secure-batches.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271]) +166 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl2/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][30] ([i915#1886] / [i915#2291])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl6/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- shard-hsw: [PASS][31] -> [INCOMPLETE][32] ([i915#2782])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-hsw1/igt@i915_selftest@live@hangcheck.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-hsw7/igt@i915_selftest@live@hangcheck.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][33] -> [FAIL][34] ([i915#2574])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-tglb7/igt@kms_async_flips@test-time-stamp.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#110723])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_chamelium@vga-edid-read:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +16 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl8/igt@kms_chamelium@vga-edid-read.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +21 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109284] / [fdo#111827])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
- shard-snb: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +23 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-snb2/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +5 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl6/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][41] ([i915#1319])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl4/igt@kms_content_protection@atomic.html
- shard-apl: NOTRUN -> [TIMEOUT][42] ([i915#1319])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl8/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109300] / [fdo#111066])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding:
- shard-skl: NOTRUN -> [FAIL][44] ([i915#54])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#54]) +9 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][47] ([i915#180])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
- shard-kbl: [PASS][48] -> [DMESG-WARN][49] ([i915#180])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-random:
- shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109278] / [fdo#109279])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109274] / [fdo#109278])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: NOTRUN -> [FAIL][52] ([i915#2346])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-iclb: NOTRUN -> [SKIP][53] ([fdo#109274]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][54] -> [FAIL][55] ([i915#2122]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1:
- shard-glk: [PASS][56] -> [FAIL][57] ([i915#2122])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk8/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-glk5/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#2672])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2642])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-skl: NOTRUN -> [FAIL][60] ([i915#2628])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-kbl: NOTRUN -> [FAIL][61] ([i915#2641])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271]) +50 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271]) +193 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#533]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl7/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl1/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [PASS][66] -> [DMESG-WARN][67] ([i915#180]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [PASS][68] -> [DMESG-WARN][69] ([i915#180] / [i915#533])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) +4 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][72] ([fdo#108145] / [i915#265]) +3 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][73] -> [FAIL][74] ([fdo#108145] / [i915#265])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-min:
- shard-iclb: NOTRUN -> [SKIP][75] ([fdo#109278])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-min.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658]) +6 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) +3 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#658])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][80] -> [SKIP][81] ([fdo#109441])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2437]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl7/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2437])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-apl6/igt@kms_writeback@writeback-pixel-formats.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][84] ([i915#2842]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][86] ([i915#2842]) -> [PASS][87] +2 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-glk: [FAIL][88] ([i915#2389]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk4/igt@gem_exec_reloc@basic-many-active@rcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-glk5/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-iclb: [DMESG-WARN][90] ([i915#2803]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb2/igt@gem_exec_schedule@u-fairslice@vcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@gem_exec_schedule@u-fairslice@vcs0.html
- shard-skl: [DMESG-WARN][92] ([i915#1610] / [i915#2803]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl7/igt@gem_exec_schedule@u-fairslice@vcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl4/igt@gem_exec_schedule@u-fairslice@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][94] ([i915#2190]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-tglb3/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw: [WARN][96] ([i915#1519]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-hsw4/igt@i915_pm_rc6_residency@rc6-idle.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-hsw4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [INCOMPLETE][98] ([i915#198]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl5/igt@i915_suspend@sysfs-reader.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl3/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
- shard-skl: [FAIL][100] ([i915#54]) -> [PASS][101] +12 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [FAIL][102] ([i915#2346]) -> [PASS][103] +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- shard-skl: [DMESG-WARN][104] ([i915#1982]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl2/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2:
- shard-glk: [FAIL][106] ([i915#79]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][108] ([fdo#108145] / [i915#265]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][110] ([fdo#109441]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@sysfs_clients@recycle:
- shard-hsw: [FAIL][112] ([i915#3028]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-hsw1/igt@sysfs_clients@recycle.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-hsw8/igt@sysfs_clients@recycle.html
* {igt@sysfs_clients@recycle-many}:
- shard-tglb: [FAIL][114] ([i915#3028]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb1/igt@sysfs_clients@recycle-many.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-tglb3/igt@sysfs_clients@recycle-many.html
#### Warnings ####
* igt@gem_exec_balancer@hang:
- shard-iclb: [INCOMPLETE][116] ([i915#1895] / [i915#2295] / [i915#3031]) -> [INCOMPLETE][117] ([i915#1895] / [i915#2295])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb1/igt@gem_exec_balancer@hang.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@gem_exec_balancer@hang.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [FAIL][118] ([i915#2851]) -> [FAIL][119] ([i915#2842])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-tglb7/igt@gem_exec_fair@basic-pace@rcs0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-tglb2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][120] ([i915#1804] / [i915#2684]) -> [WARN][121] ([i915#2684])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][122] ([i915#2684]) -> [WARN][123] ([i915#1804] / [i915#2684])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][124] ([i915#1188]) -> [INCOMPLETE][125] ([i915#146] / [i915#198] / [i915#2828])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][126] ([i915#658]) -> [SKIP][127] ([i915#2920])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][128] ([i915#2920]) -> [SKIP][129] ([i915#658])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: [FAIL][130] ([i915#2295]) -> ([FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#1436] / [i915#1814] / [i915#2295] / [i915#2505] / [i915#3002])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-kbl2/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl4/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl4/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl1/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl2/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl6/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-kbl7/igt@runner@aborted.html
- shard-iclb: ([FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140]) ([i915#2295] / [i915#2426] / [i915#2724] / [i915#3002]) -> ([FAIL][141], [FAIL][142], [FAIL][143]) ([i915#2295] / [i915#2724] / [i915#3002])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb4/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb2/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb6/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-iclb8/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb6/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb3/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/shard-iclb7/igt@runner@aborted.html
- shard-apl: ([FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([i915#2295] / [i915#3002]) -> ([FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151]) ([fdo#109271] / [i915#1814] / [i915#2295])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-apl1/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9777/shard-apl6/igt@runner@aborted.html
[146]
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19683/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev3)
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
` (5 preceding siblings ...)
2021-02-15 22:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-02-17 14:27 ` Patchwork
2021-02-17 16:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-02-17 14:27 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2676 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev3)
URL : https://patchwork.freedesktop.org/series/87102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9781 -> Patchwork_19693
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/index.html
Known issues
------------
Here are the changes found in Patchwork_19693 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-kbl-7500u: [PASS][1] -> [DMESG-WARN][2] ([i915#2605])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/fi-kbl-7500u/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/fi-kbl-7500u/igt@i915_module_load@reload.html
* igt@kms_addfb_basic@addfb25-bad-modifier:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/fi-tgl-y/igt@kms_addfb_basic@addfb25-bad-modifier.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/fi-tgl-y/igt@kms_addfb_basic@addfb25-bad-modifier.html
#### Possible fixes ####
* igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/fi-tgl-y/igt@i915_getparams_basic@basic-subslice-total.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/fi-tgl-y/igt@i915_getparams_basic@basic-subslice-total.html
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9781 -> Patchwork_19693
CI-20190529: 20190529
CI_DRM_9781: fcfb6981006e381b8ee4a97152991a615161e003 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6005: b69a3c463f0aec46b19c14ac24351d292cb11c08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19693: dde47dc31b1385bb12afd61f5b6a98bf49d53c4d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dde47dc31b13 drm/i915: Refine VT-d scanout workaround
a19a594007ea drm/i915: Introduce guard pages to i915_vma
6e60f8692b68 drm/i915: Wrap all access to i915_vma.node.start|size
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev3)
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
` (6 preceding siblings ...)
2021-02-17 14:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev3) Patchwork
@ 2021-02-17 16:33 ` Patchwork
2021-02-20 13:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev5) Patchwork
2021-02-20 15:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-02-17 16:33 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30310 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev3)
URL : https://patchwork.freedesktop.org/series/87102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9781_full -> Patchwork_19693_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
New tests
---------
New tests have been introduced between CI_DRM_9781_full and Patchwork_19693_full:
### New IGT tests (1) ###
* igt@gem_exec_reloc@basic-scanout:
- Statuses :
- Exec time: [None] s
Known issues
------------
Here are the changes found in Patchwork_19693_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-mixed-process:
- shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-hsw7/igt@gem_ctx_persistence@legacy-engines-mixed-process.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +5 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-snb2/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@unwedge-stress:
- shard-skl: [PASS][3] -> [TIMEOUT][4] ([i915#1037] / [i915#2771])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl9/igt@gem_eio@unwedge-stress.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl3/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-tglb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-iclb3/igt@gem_exec_fair@basic-pace@bcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-iclb7/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-kbl: NOTRUN -> [FAIL][13] ([i915#2389]) +9 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl6/igt@gem_exec_reloc@basic-many-active@vcs0.html
* igt@gem_exec_reloc@basic-parallel:
- shard-kbl: NOTRUN -> [TIMEOUT][14] ([i915#1729])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl4/igt@gem_exec_reloc@basic-parallel.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][15] ([i915#1610] / [i915#2803])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl4/igt@gem_exec_schedule@u-fairslice@rcs0.html
- shard-skl: [PASS][16] -> [DMESG-WARN][17] ([i915#1610] / [i915#2803])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl8/igt@gem_exec_schedule@u-fairslice@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl4/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vecs0:
- shard-tglb: [PASS][18] -> [DMESG-WARN][19] ([i915#2803])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-tglb2/igt@gem_exec_schedule@u-fairslice@vecs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-tglb7/igt@gem_exec_schedule@u-fairslice@vecs0.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][20] -> [FAIL][21] ([i915#644])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][22] ([i915#2658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl6/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-snb: NOTRUN -> [WARN][23] ([i915#2658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-snb2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][24] ([fdo#109271]) +215 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl4/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@input-checking:
- shard-glk: NOTRUN -> [DMESG-WARN][25] ([i915#3002])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk6/igt@gem_userptr_blits@input-checking.html
- shard-snb: NOTRUN -> [DMESG-WARN][26] ([i915#3002])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-snb6/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@process-exit-mmap@gtt:
- shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#1699]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl4/igt@gem_userptr_blits@process-exit-mmap@gtt.html
* igt@gem_userptr_blits@process-exit-mmap@wb:
- shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#1699]) +7 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl7/igt@gem_userptr_blits@process-exit-mmap@wb.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][29] ([i915#454])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl6/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#1937])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#1937])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl2/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@kms_ccs@pipe-c-bad-rotation-90:
- shard-skl: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111304])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl6/igt@kms_ccs@pipe-c-bad-rotation-90.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +20 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl4/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk6/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +27 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl3/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-skl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl6/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
- shard-snb: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +26 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-snb7/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][38] ([i915#1319]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl4/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][39] ([i915#1319])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl7/igt@kms_content_protection@lic.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][40] ([i915#2105])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl6/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-random:
- shard-skl: NOTRUN -> [FAIL][41] ([i915#54])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-random:
- shard-apl: NOTRUN -> [FAIL][42] ([i915#54])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
- shard-kbl: NOTRUN -> [FAIL][43] ([i915#54])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-random:
- shard-skl: [PASS][44] -> [FAIL][45] ([i915#54]) +5 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-random:
- shard-glk: NOTRUN -> [SKIP][46] ([fdo#109271]) +13 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk6/igt@kms_cursor_crc@pipe-d-cursor-256x256-random.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-snb: NOTRUN -> [SKIP][47] ([fdo#109271]) +415 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-snb6/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][48] -> [FAIL][49] ([i915#2346] / [i915#533])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [PASS][50] -> [FAIL][51] ([i915#2598])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: NOTRUN -> [DMESG-WARN][52] ([i915#180])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: NOTRUN -> [FAIL][53] ([i915#2122]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [PASS][54] -> [FAIL][55] ([i915#2122])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl3/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl10/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-kbl: NOTRUN -> [FAIL][56] ([i915#2641]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#2672])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#2642])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-apl: NOTRUN -> [FAIL][59] ([i915#2641])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
- shard-hsw: NOTRUN -> [SKIP][60] ([fdo#109271]) +20 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-hsw7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack:
- shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271]) +13 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][62] -> [FAIL][63] ([i915#1188])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#533]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][66] ([i915#265])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][67] ([fdo#108145] / [i915#265]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][68] ([i915#265])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][69] ([fdo#108145] / [i915#265]) +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-min:
- shard-hsw: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-hsw7/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-min.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +8 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658]) +7 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][73] -> [SKIP][74] ([fdo#109441]) +3 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2437]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl7/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-glk: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2437])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk2/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271]) +253 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl7/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@sysfs_clients@busy@bcs0:
- shard-kbl: [PASS][78] -> [FAIL][79] ([i915#3009])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-kbl1/igt@sysfs_clients@busy@bcs0.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl6/igt@sysfs_clients@busy@bcs0.html
* igt@sysfs_clients@busy@vecs0:
- shard-skl: [PASS][80] -> [FAIL][81] ([i915#3019])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl6/igt@sysfs_clients@busy@vecs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl10/igt@sysfs_clients@busy@vecs0.html
* igt@sysfs_clients@sema-10@rcs0:
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#3026])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl3/igt@sysfs_clients@sema-10@rcs0.html
* igt@sysfs_clients@split-10@bcs0:
- shard-kbl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#3026])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl6/igt@sysfs_clients@split-10@bcs0.html
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-glk: [PASS][84] -> [FAIL][85] ([i915#1731])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-glk7/igt@sysfs_heartbeat_interval@mixed@rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk3/igt@sysfs_heartbeat_interval@mixed@rcs0.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [FAIL][86] ([i915#2842]) -> [PASS][87] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-tglb7/igt@gem_exec_fair@basic-pace@bcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-tglb2/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [FAIL][88] ([i915#2842]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-glk1/igt@gem_exec_fair@basic-pace@rcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk5/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_schedule@u-fairslice-all:
- shard-skl: [DMESG-FAIL][90] ([i915#1610] / [i915#1982]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl9/igt@gem_exec_schedule@u-fairslice-all.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl6/igt@gem_exec_schedule@u-fairslice-all.html
* igt@gem_exec_schedule@u-fairslice@bcs0:
- shard-apl: [DMESG-WARN][92] ([i915#1610]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-apl6/igt@gem_exec_schedule@u-fairslice@bcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl1/igt@gem_exec_schedule@u-fairslice@bcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-glk: [DMESG-WARN][94] ([i915#1610] / [i915#2803]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-glk6/igt@gem_exec_schedule@u-fairslice@rcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk6/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-skl: [DMESG-WARN][96] ([i915#1610] / [i915#2803]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl8/igt@gem_exec_schedule@u-fairslice@vcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl4/igt@gem_exec_schedule@u-fairslice@vcs0.html
* igt@gem_vm_create@destroy-race:
- shard-tglb: [TIMEOUT][98] ([i915#2795]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-tglb1/igt@gem_vm_create@destroy-race.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-tglb2/igt@gem_vm_create@destroy-race.html
* igt@i915_selftest@live@gem_contexts:
- shard-skl: [INCOMPLETE][100] ([i915#198] / [i915#2782]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl2/igt@i915_selftest@live@gem_contexts.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl5/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@hangcheck:
- shard-hsw: [INCOMPLETE][102] ([i915#2782]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-hsw4/igt@i915_selftest@live@hangcheck.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-hsw1/igt@i915_selftest@live@hangcheck.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [FAIL][104] ([i915#2597]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-tglb8/igt@kms_async_flips@test-time-stamp.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-tglb7/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-skl: [FAIL][106] ([i915#54]) -> [PASS][107] +2 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][108] ([i915#96]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [FAIL][110] ([i915#2370]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-hsw8/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-hsw2/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][112] ([i915#79]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
- shard-tglb: [FAIL][114] ([i915#2598]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][116] ([i915#1188]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][118] ([fdo#108145] / [i915#265]) -> [PASS][119] +2 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][120] ([fdo#109441]) -> [PASS][121] +2 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][122] ([i915#1542]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-skl9/igt@perf@polling-parameterized.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-skl3/igt@perf@polling-parameterized.html
* igt@testdisplay:
- shard-kbl: [DMESG-WARN][124] ([i915#165] / [i915#180] / [i915#78]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-kbl2/igt@testdisplay.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl7/igt@testdisplay.html
#### Warnings ####
* igt@i915_selftest@live@gt_pm:
- shard-tglb: [DMESG-FAIL][126] ([i915#1759] / [i915#2291]) -> [DMESG-FAIL][127] ([i915#2291])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-tglb1/igt@i915_selftest@live@gt_pm.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-tglb2/igt@i915_selftest@live@gt_pm.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-onscreen:
- shard-hsw: [INCOMPLETE][128] -> [INCOMPLETE][129] ([i915#2055])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-hsw8/igt@kms_cursor_crc@pipe-c-cursor-512x512-onscreen.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-hsw2/igt@kms_cursor_crc@pipe-c-cursor-512x512-onscreen.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][130] ([i915#658]) -> [SKIP][131] ([i915#2920]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][132] ([i915#2920]) -> [SKIP][133] ([i915#658])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@runner@aborted:
- shard-kbl: [FAIL][134] ([i915#2295] / [i915#2505] / [i915#3002]) -> ([FAIL][135], [FAIL][136]) ([i915#2295] / [i915#2426] / [i915#3002])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-kbl6/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl7/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-kbl4/igt@runner@aborted.html
- shard-apl: ([FAIL][137], [FAIL][138], [FAIL][139]) ([i915#1610] / [i915#2295] / [i915#2426]) -> [FAIL][140] ([i915#2295])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-apl6/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-apl8/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-apl6/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-apl1/igt@runner@aborted.html
- shard-glk: ([FAIL][141], [FAIL][142], [FAIL][143]) ([i915#2295] / [i915#2426] / [i915#3002] / [k.org#202321]) -> ([FAIL][144], [FAIL][145], [FAIL][146]) ([i915#2295] / [i915#3002] / [k.org#202321])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-glk3/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-glk8/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9781/shard-glk6/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk6/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk5/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/shard-glk4/igt@runner@aborted.html
- shard-tglb: ([FAIL][
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19693/index.html
[-- Attachment #1.2: Type: text/html, Size: 33476 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround
2021-02-15 15:56 ` [Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround Chris Wilson
2021-02-15 18:07 ` Matthew Auld
@ 2021-02-20 11:08 ` Chris Wilson
2021-02-20 11:10 ` Chris Wilson
2 siblings, 0 replies; 25+ messages in thread
From: Chris Wilson @ 2021-02-20 11:08 UTC (permalink / raw)
To: intel-gfx; +Cc: Imre Deak, Matthew Auld, Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 168 PTE,
warning that the accesses will wrap around the ends of the GGTT.
Currently, we fill the entire GGTT with scratch pages when using VT-d to
always ensure there are valid entries around every vma, including
scanout. However, writing every PTE is slow as on recent devices we
perform 8MiB of uncached writes, incurring an extra 100ms during resume.
If instead we focus on only putting guard pages around scanout, we can
avoid touching the whole GGTT. To avoid having to introduce extra nodes
around each scanout vma, we adjust the scanout drm_mm_node to be smaller
than the allocated space, and fixup the extra PTE during dma binding.
v2: Move the guard from modifying drm_mm_node.start which is still used
by the drm_mm itself, into an adjustment of node.start at the point of
use.
v3: Pass the requested guard padding from the caller, so we can drop the
VT-d w/a knowledge from the i915_vma allocator.
v4: Bump minimum padding to 168 PTE and cautiously ensure that a full
tile row around the vma is included with the guard.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Imre Deak <imre.dead@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++++++++++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +---------------------
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/i915_vma.c | 8 +++++++
4 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 0478b069c202..32b13af0d3df 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -16,6 +16,8 @@
#include "i915_gem_lmem.h"
#include "i915_gem_mman.h"
+#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
+
static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
return !(obj->cache_level == I915_CACHE_NONE ||
@@ -345,6 +347,17 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
if (ret)
goto err;
+ /* VT-d may overfetch before/after the vma, so pad with scratch */
+ if (intel_scanout_needs_vtd_wa(i915)) {
+ unsigned int guard = VTD_GUARD;
+
+ if (i915_gem_object_is_tiled(obj))
+ guard = max(guard,
+ i915_gem_object_get_tile_row_size(obj));
+
+ flags |= PIN_OFFSET_GUARD | guard;
+ }
+
/*
* As the user may map the buffer once pinned in the display plane
* (e.g. libkms for the bootup splash), we have to ensure that we
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 6b326138e765..251b50884d1c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -319,27 +319,6 @@ static void nop_clear_range(struct i915_address_space *vm,
{
}
-static void gen8_ggtt_clear_range(struct i915_address_space *vm,
- u64 start, u64 length)
-{
- struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
- unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
- unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
- const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
- gen8_pte_t __iomem *gtt_base =
- (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
- const int max_entries = ggtt_total_entries(ggtt) - first_entry;
- int i;
-
- if (WARN(num_entries > max_entries,
- "First entry = %d; Num entries = %d (max=%d)\n",
- first_entry, num_entries, max_entries))
- num_entries = max_entries;
-
- for (i = 0; i < num_entries; i++)
- gen8_set_pte(>t_base[i], scratch_pte);
-}
-
static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
{
/*
@@ -907,8 +886,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.cleanup = gen6_gmch_remove;
ggtt->vm.insert_page = gen8_ggtt_insert_page;
ggtt->vm.clear_range = nop_clear_range;
- if (intel_scanout_needs_vtd_wa(i915))
- ggtt->vm.clear_range = gen8_ggtt_clear_range;
ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
@@ -1054,7 +1031,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
ggtt->vm.clear_range = nop_clear_range;
- if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
+ if (!HAS_FULL_PPGTT(i915))
ggtt->vm.clear_range = gen6_ggtt_clear_range;
ggtt->vm.insert_page = gen6_ggtt_insert_page;
ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c9b0ee5e1d23..f3ae9afdee15 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -41,6 +41,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
#define PIN_HIGH BIT_ULL(5)
#define PIN_OFFSET_BIAS BIT_ULL(6)
#define PIN_OFFSET_FIXED BIT_ULL(7)
+#define PIN_OFFSET_GUARD BIT_ULL(8)
#define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
#define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 01e62edf4704..030b31262e66 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -552,6 +552,9 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
return true;
+ if (flags & PIN_OFFSET_GUARD && vma->guard < (flags & PIN_OFFSET_MASK))
+ return true;
+
return false;
}
@@ -629,6 +632,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND));
GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
+ GEM_BUG_ON(hweight64(flags & (PIN_OFFSET_GUARD | PIN_OFFSET_FIXED | PIN_OFFSET_BIAS)) > 1);
size = max(size, vma->size);
alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
@@ -643,6 +647,10 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(!is_power_of_2(alignment));
guard = vma->guard; /* retain guard across rebinds */
+ if (flags & PIN_OFFSET_GUARD) {
+ GEM_BUG_ON(overflows_type(flags & PIN_OFFSET_MASK, u32));
+ guard = max_t(u32, guard, flags & PIN_OFFSET_MASK);
+ }
guard = ALIGN(guard, alignment);
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround
2021-02-15 15:56 ` [Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround Chris Wilson
2021-02-15 18:07 ` Matthew Auld
2021-02-20 11:08 ` [Intel-gfx] [PATCH] " Chris Wilson
@ 2021-02-20 11:10 ` Chris Wilson
2 siblings, 0 replies; 25+ messages in thread
From: Chris Wilson @ 2021-02-20 11:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld, Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 168 PTE,
warning that the accesses will wrap around the ends of the GGTT.
Currently, we fill the entire GGTT with scratch pages when using VT-d to
always ensure there are valid entries around every vma, including
scanout. However, writing every PTE is slow as on recent devices we
perform 8MiB of uncached writes, incurring an extra 100ms during resume.
If instead we focus on only putting guard pages around scanout, we can
avoid touching the whole GGTT. To avoid having to introduce extra nodes
around each scanout vma, we adjust the scanout drm_mm_node to be smaller
than the allocated space, and fixup the extra PTE during dma binding.
v2: Move the guard from modifying drm_mm_node.start which is still used
by the drm_mm itself, into an adjustment of node.start at the point of
use.
v3: Pass the requested guard padding from the caller, so we can drop the
VT-d w/a knowledge from the i915_vma allocator.
v4: Bump minimum padding to 168 PTE and cautiously ensure that a full
tile row around the vma is included with the guard.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++++++++++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +---------------------
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/i915_vma.c | 8 +++++++
4 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 0478b069c202..32b13af0d3df 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -16,6 +16,8 @@
#include "i915_gem_lmem.h"
#include "i915_gem_mman.h"
+#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
+
static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
return !(obj->cache_level == I915_CACHE_NONE ||
@@ -345,6 +347,17 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
if (ret)
goto err;
+ /* VT-d may overfetch before/after the vma, so pad with scratch */
+ if (intel_scanout_needs_vtd_wa(i915)) {
+ unsigned int guard = VTD_GUARD;
+
+ if (i915_gem_object_is_tiled(obj))
+ guard = max(guard,
+ i915_gem_object_get_tile_row_size(obj));
+
+ flags |= PIN_OFFSET_GUARD | guard;
+ }
+
/*
* As the user may map the buffer once pinned in the display plane
* (e.g. libkms for the bootup splash), we have to ensure that we
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 6b326138e765..251b50884d1c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -319,27 +319,6 @@ static void nop_clear_range(struct i915_address_space *vm,
{
}
-static void gen8_ggtt_clear_range(struct i915_address_space *vm,
- u64 start, u64 length)
-{
- struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
- unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
- unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
- const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
- gen8_pte_t __iomem *gtt_base =
- (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
- const int max_entries = ggtt_total_entries(ggtt) - first_entry;
- int i;
-
- if (WARN(num_entries > max_entries,
- "First entry = %d; Num entries = %d (max=%d)\n",
- first_entry, num_entries, max_entries))
- num_entries = max_entries;
-
- for (i = 0; i < num_entries; i++)
- gen8_set_pte(>t_base[i], scratch_pte);
-}
-
static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
{
/*
@@ -907,8 +886,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.cleanup = gen6_gmch_remove;
ggtt->vm.insert_page = gen8_ggtt_insert_page;
ggtt->vm.clear_range = nop_clear_range;
- if (intel_scanout_needs_vtd_wa(i915))
- ggtt->vm.clear_range = gen8_ggtt_clear_range;
ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
@@ -1054,7 +1031,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
ggtt->vm.clear_range = nop_clear_range;
- if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
+ if (!HAS_FULL_PPGTT(i915))
ggtt->vm.clear_range = gen6_ggtt_clear_range;
ggtt->vm.insert_page = gen6_ggtt_insert_page;
ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c9b0ee5e1d23..f3ae9afdee15 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -41,6 +41,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
#define PIN_HIGH BIT_ULL(5)
#define PIN_OFFSET_BIAS BIT_ULL(6)
#define PIN_OFFSET_FIXED BIT_ULL(7)
+#define PIN_OFFSET_GUARD BIT_ULL(8)
#define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
#define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 01e62edf4704..030b31262e66 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -552,6 +552,9 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
return true;
+ if (flags & PIN_OFFSET_GUARD && vma->guard < (flags & PIN_OFFSET_MASK))
+ return true;
+
return false;
}
@@ -629,6 +632,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND));
GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
+ GEM_BUG_ON(hweight64(flags & (PIN_OFFSET_GUARD | PIN_OFFSET_FIXED | PIN_OFFSET_BIAS)) > 1);
size = max(size, vma->size);
alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
@@ -643,6 +647,10 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(!is_power_of_2(alignment));
guard = vma->guard; /* retain guard across rebinds */
+ if (flags & PIN_OFFSET_GUARD) {
+ GEM_BUG_ON(overflows_type(flags & PIN_OFFSET_MASK, u32));
+ guard = max_t(u32, guard, flags & PIN_OFFSET_MASK);
+ }
guard = ALIGN(guard, alignment);
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev5)
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
` (7 preceding siblings ...)
2021-02-17 16:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-02-20 13:04 ` Patchwork
2021-02-20 15:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-02-20 13:04 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4587 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev5)
URL : https://patchwork.freedesktop.org/series/87102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9791 -> Patchwork_19708
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/index.html
Known issues
------------
Here are the changes found in Patchwork_19708 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html
* igt@amdgpu/amd_basic@userptr:
- fi-byt-j1900: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/fi-byt-j1900/igt@amdgpu/amd_basic@userptr.html
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#1982] / [i915#402])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@gem_tiled_blits@basic:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/fi-tgl-y/igt@gem_tiled_blits@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/fi-tgl-y/igt@gem_tiled_blits@basic.html
#### Possible fixes ####
* igt@fbdev@read:
- fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/fi-tgl-y/igt@fbdev@read.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/fi-tgl-y/igt@fbdev@read.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [INCOMPLETE][9] ([i915#142] / [i915#2405]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [INCOMPLETE][11] ([i915#2940]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/fi-bsw-nick/igt@i915_selftest@live@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
[i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (45 -> 41)
------------------------------
Additional (1): fi-ehl-2
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9791 -> Patchwork_19708
CI-20190529: 20190529
CI_DRM_9791: c1991e1c98008d13d9773744a9f9da0884644917 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6009: a4dccf189b34a55338feec9927dac57c467c4100 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19708: 2cf0b46b2c988b75a357e85370df2ce4e8367684 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2cf0b46b2c98 drm/i915: Refine VT-d scanout workaround
cb68bc3ad306 drm/i915: Introduce guard pages to i915_vma
20e692ab64dc drm/i915: Wrap all access to i915_vma.node.start|size
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/index.html
[-- Attachment #1.2: Type: text/html, Size: 5178 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev5)
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
` (8 preceding siblings ...)
2021-02-20 13:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev5) Patchwork
@ 2021-02-20 15:13 ` Patchwork
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-02-20 15:13 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30310 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev5)
URL : https://patchwork.freedesktop.org/series/87102/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9791_full -> Patchwork_19708_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19708_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19708_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19708_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-snb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-snb7/igt@gem_mmap_gtt@fault-concurrent-y.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-snb5/igt@gem_mmap_gtt@fault-concurrent-y.html
#### Warnings ####
* igt@runner@aborted:
- shard-kbl: ([FAIL][3], [FAIL][4], [FAIL][5]) ([i915#1814] / [i915#2505] / [i915#92]) -> ([FAIL][6], [FAIL][7]) ([i915#1436])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-kbl1/igt@runner@aborted.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-kbl1/igt@runner@aborted.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-kbl6/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl1/igt@runner@aborted.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl1/igt@runner@aborted.html
- shard-apl: ([FAIL][8], [FAIL][9]) -> ([FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13]) ([i915#1814] / [i915#3002])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-apl8/igt@runner@aborted.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-apl8/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl7/igt@runner@aborted.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl6/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl8/igt@runner@aborted.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@runner@aborted.html
- shard-skl: ([FAIL][14], [FAIL][15]) ([i915#3002]) -> ([FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19]) ([i915#1436] / [i915#2426] / [i915#3002])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl7/igt@runner@aborted.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl8/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl1/igt@runner@aborted.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl3/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl6/igt@runner@aborted.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl10/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_19708_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][20] -> [SKIP][21] ([i915#658])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-iclb2/igt@feature_discovery@psr2.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-iclb4/igt@feature_discovery@psr2.html
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][22] ([i915#3002])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl7/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][23] ([i915#180]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#1099]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-snb2/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][25] -> [TIMEOUT][26] ([i915#3063])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-tglb8/igt@gem_eio@unwedge-stress.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-tglb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][27] -> [FAIL][28] ([i915#2842])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: NOTRUN -> [FAIL][29] ([i915#2842]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][30] ([i915#2842])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_reloc@basic-parallel:
- shard-kbl: NOTRUN -> [TIMEOUT][31] ([i915#1729])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl4/igt@gem_exec_reloc@basic-parallel.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-skl: NOTRUN -> [DMESG-WARN][32] ([i915#1610] / [i915#2803])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl6/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-glk: [PASS][33] -> [DMESG-WARN][34] ([i915#1610] / [i915#2803])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-glk7/igt@gem_exec_schedule@u-fairslice@vcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk9/igt@gem_exec_schedule@u-fairslice@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#2190])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@gem_huc_copy@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][36] ([i915#2658])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-snb: NOTRUN -> [WARN][37] ([i915#2658])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-snb2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@input-checking:
- shard-snb: NOTRUN -> [DMESG-WARN][38] ([i915#3002])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-snb7/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@process-exit-mmap-busy@wc:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#1699]) +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@gem_userptr_blits@process-exit-mmap-busy@wc.html
* igt@gem_userptr_blits@process-exit-mmap@wb:
- shard-glk: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#1699]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk9/igt@gem_userptr_blits@process-exit-mmap@wb.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][41] ([i915#2724])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-snb7/igt@gem_userptr_blits@vma-merge.html
- shard-apl: NOTRUN -> [INCOMPLETE][42] ([i915#2502] / [i915#2667])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl6/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@basic-offset:
- shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271]) +103 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][44] -> [DMESG-WARN][45] ([i915#1436] / [i915#716])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl4/igt@gen9_exec_parse@allowed-single.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl10/igt@gen9_exec_parse@allowed-single.html
* igt@i915_hangman@engine-error@vecs0:
- shard-kbl: NOTRUN -> [SKIP][46] ([fdo#109271]) +249 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl1/igt@i915_hangman@engine-error@vecs0.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#1937])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_suspend@forcewake:
- shard-apl: [PASS][48] -> [DMESG-WARN][49] ([i915#180])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-apl7/igt@i915_suspend@forcewake.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl8/igt@i915_suspend@forcewake.html
* igt@kms_big_joiner@basic:
- shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#2705])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl7/igt@kms_big_joiner@basic.html
* igt@kms_chamelium@hdmi-audio-edid:
- shard-glk: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk9/igt@kms_chamelium@hdmi-audio-edid.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +11 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +27 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl7/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-b-ctm-negative:
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl5/igt@kms_color_chamelium@pipe-b-ctm-negative.html
* igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-snb: NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +11 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-snb2/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][56] ([i915#1319]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl3/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][57] ([i915#1319])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl1/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
- shard-skl: NOTRUN -> [FAIL][58] ([i915#54]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen:
- shard-skl: [PASS][59] -> [FAIL][60] ([i915#54]) +11 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-snb: NOTRUN -> [SKIP][61] ([fdo#109271]) +210 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-snb6/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][62] -> [FAIL][63] ([i915#2346])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][64] -> [FAIL][65] ([i915#2346] / [i915#533])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled:
- shard-skl: NOTRUN -> [DMESG-WARN][66] ([i915#1982])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-iclb: [PASS][67] -> [FAIL][68] ([i915#79])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-iclb6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-iclb5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [PASS][69] -> [FAIL][70] ([i915#2598])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
- shard-glk: [PASS][71] -> [FAIL][72] ([i915#79])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [PASS][73] -> [FAIL][74] ([i915#2122])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2672])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2642])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-kbl: NOTRUN -> [FAIL][77] ([i915#2641])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2672])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
- shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271]) +43 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite:
- shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271]) +29 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#533]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-glk: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#533])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk9/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-apl: NOTRUN -> [DMESG-WARN][83] ([i915#180])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][84] ([fdo#108145] / [i915#265]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][85] ([fdo#108145] / [i915#265])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][86] ([fdo#108145] / [i915#265]) +4 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-glk: NOTRUN -> [FAIL][87] ([fdo#108145] / [i915#265])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk9/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][88] ([i915#265])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-skl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2733])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl5/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#658]) +5 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-skl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#658]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-glk: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#658])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk9/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658]) +2 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][94] -> [SKIP][95] ([fdo#109441]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][96] ([IGT#2])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-kbl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#533]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl1/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-kbl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#2437])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl7/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@short-reads:
- shard-skl: [PASS][99] -> [FAIL][100] ([i915#51])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl9/igt@perf@short-reads.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl8/igt@perf@short-reads.html
* igt@sysfs_clients@recycle:
- shard-kbl: [PASS][101] -> [FAIL][102] ([i915#3028]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-kbl2/igt@sysfs_clients@recycle.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl2/igt@sysfs_clients@recycle.html
* igt@sysfs_clients@sema-10@rcs0:
- shard-apl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#3026])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl1/igt@sysfs_clients@sema-10@rcs0.html
* igt@sysfs_clients@split-10@rcs0:
- shard-tglb: [PASS][104] -> [SKIP][105] ([i915#3026] / [i915#3061])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-tglb8/igt@sysfs_clients@split-10@rcs0.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-tglb8/igt@sysfs_clients@split-10@rcs0.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [TIMEOUT][106] ([i915#3063]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-tglb7/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-iclb: [TIMEOUT][108] ([i915#3070]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-iclb2/igt@gem_eio@in-flight-contexts-immediate.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-iclb2/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][110] ([i915#2842]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [FAIL][112] ([i915#2842]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-iclb6/igt@gem_exec_fair@basic-pace@vcs0.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-iclb5/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_schedule@u-fairslice@vecs0:
- shard-glk: [DMESG-WARN][114] ([i915#1610] / [i915#2803]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-glk7/igt@gem_exec_schedule@u-fairslice@vecs0.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk9/igt@gem_exec_schedule@u-fairslice@vecs0.html
* igt@gem_exec_whisper@basic-forked:
- shard-glk: [DMESG-WARN][116] ([i915#118] / [i915#95]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-glk2/igt@gem_exec_whisper@basic-forked.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-glk5/igt@gem_exec_whisper@basic-forked.html
* igt@i915_selftest@live@client:
- shard-apl: [DMESG-FAIL][118] ([i915#3047]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-apl1/igt@i915_selftest@live@client.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl6/igt@i915_selftest@live@client.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-skl: [INCOMPLETE][120] ([i915#198]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl7/igt@i915_suspend@fence-restore-tiled2untiled.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl6/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_color@pipe-a-ctm-max:
- shard-skl: [DMESG-WARN][122] ([i915#1982]) -> [PASS][123] +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl8/igt@kms_color@pipe-a-ctm-max.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl8/igt@kms_color@pipe-a-ctm-max.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-skl: [FAIL][124] ([i915#54]) -> [PASS][125] +3 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][126] ([i915#180]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge:
- shard-kbl: [FAIL][128] ([i915#70]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-kbl1/igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl6/igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][130] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][132] ([i915#79]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][134] ([i915#2122]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][136] ([i915#180]) -> [PASS][137] +1 similar issue
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][138] ([i915#1188]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][140] ([fdo#108145] / [i915#265]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][142] ([fdo#109441]) -> [PASS][143] +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-iclb4/igt@kms_psr@psr2_basic.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][144] ([i915#1542]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9791/shard-skl5/igt@perf@polling-parameterized.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/shard-skl6/igt@perf@polling-parameterized.html
* igt@sysfs_clients@recycle-many:
- shard-tglb: [FAIL][146] ([i915#3028]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19708/index.html
[-- Attachment #1.2: Type: text/html, Size: 33443 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size
2022-11-09 17:40 [PATCH 0/3] add guard padding around i915_vma Andi Shyti
@ 2022-11-09 17:40 ` Andi Shyti
0 siblings, 0 replies; 25+ messages in thread
From: Andi Shyti @ 2022-11-09 17:40 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, Chris Wilson, Matthew Auld
From: Chris Wilson <chris@chris-wilson.co.uk>
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_node
allocation. That is we will offset the vma->pages so that the first page
is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
All users must then not use i915_vma.node.start directly, but compute
the guard offset, thus all users are converted to use a
i915_vma_offset() wrapper.
The notable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 33 ++++++------
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 23 +++++----
.../drm/i915/gem/selftests/i915_gem_context.c | 15 +++---
.../drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
.../drm/i915/gem/selftests/igt_gem_utils.c | 7 +--
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 +++----
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 +++---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 16 +++---
.../drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 12 ++---
.../gpu/drm/i915/gt/selftest_workarounds.c | 8 +--
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 25 ++++-----
drivers/gpu/drm/i915/i915_vma.h | 51 +++++++++++++++++--
drivers/gpu/drm/i915/i915_vma_resource.h | 10 ++--
drivers/gpu/drm/i915/selftests/i915_request.c | 20 ++++----
drivers/gpu/drm/i915/selftests/igt_spinner.c | 8 +--
29 files changed, 180 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 5575d7abdc092..03ed4607a46d2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -286,7 +286,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
+ (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
info->fix.smem_len = vma->size;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 1160723c9d2d9..5f09d33f1c836 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -378,22 +378,25 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
const struct i915_vma *vma,
unsigned int flags)
{
- if (vma->node.size < entry->pad_to_size)
+ const u64 start = i915_vma_offset(vma);
+ const u64 size = i915_vma_size(vma);
+
+ if (size < entry->pad_to_size)
return true;
- if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
+ if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
return true;
if (flags & EXEC_OBJECT_PINNED &&
- vma->node.start != entry->offset)
+ start != entry->offset)
return true;
if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
- vma->node.start < BATCH_OFFSET_BIAS)
+ start < BATCH_OFFSET_BIAS)
return true;
if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
- (vma->node.start + vma->node.size + 4095) >> 32)
+ (start + size + 4095) >> 32)
return true;
if (flags & __EXEC_OBJECT_NEEDS_MAP &&
@@ -439,7 +442,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
int err;
if (vma->node.size)
- pin_flags = vma->node.start;
+ pin_flags = __i915_vma_offset(vma);
else
pin_flags = entry->offset & PIN_OFFSET_MASK;
@@ -662,8 +665,8 @@ static int eb_reserve_vma(struct i915_execbuffer *eb,
if (err)
return err;
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
@@ -983,8 +986,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
return err;
if (!err) {
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
} else {
@@ -1065,7 +1068,7 @@ static inline u64
relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
const struct i915_vma *target)
{
- return gen8_canonical_addr((int)reloc->delta + target->node.start);
+ return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target));
}
static void reloc_cache_init(struct reloc_cache *cache,
@@ -1274,7 +1277,7 @@ static void *reloc_iomap(struct i915_vma *batch,
if (err) /* no inactive aperture space, use cpu reloc */
return NULL;
} else {
- cache->node.start = vma->node.start;
+ cache->node.start = i915_ggtt_offset(vma);
cache->node.mm = (void *)vma;
}
}
@@ -1437,7 +1440,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
* more work needs to be done.
*/
if (!DBG_FORCE_RELOC &&
- gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
+ gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset)
return 0;
/* Check that the relocation address is valid... */
@@ -2365,7 +2368,7 @@ static int eb_request_submit(struct i915_execbuffer *eb,
}
err = rq->context->engine->emit_bb_start(rq,
- batch->node.start +
+ i915_vma_offset(batch) +
eb->batch_start_offset,
batch_len,
eb->batch_flags);
@@ -2376,7 +2379,7 @@ static int eb_request_submit(struct i915_execbuffer *eb,
GEM_BUG_ON(intel_context_is_parallel(rq->context));
GEM_BUG_ON(eb->batch_start_offset);
err = rq->context->engine->emit_bb_start(rq,
- eb->trampoline->node.start +
+ i915_vma_offset(eb->trampoline) +
batch_len, 0, 0);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index c29efdef8313a..d73ba0f5c4c52 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -395,7 +395,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
area->vm_start + (vma->gtt_view.partial.offset << PAGE_SHIFT),
- (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
+ (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
min_t(u64, vma->size, area->vm_end - area->vm_start),
&ggtt->iomap);
if (ret)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 8dc5c8874d8a2..b1672e054b21e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -400,7 +400,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
mutex_lock(&to_gt(i915)->ggtt->vm.mutex);
list_for_each_entry_safe(vma, next,
&to_gt(i915)->ggtt->vm.bound_list, vm_link) {
- unsigned long count = vma->node.size >> PAGE_SHIFT;
+ unsigned long count = i915_vma_size(vma) >> PAGE_SHIFT;
struct drm_i915_gem_object *obj = vma->obj;
if (!vma->iomap || i915_vma_is_active(vma))
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index fd42b89b7162b..04bb909acdec8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -168,11 +168,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma,
return true;
size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return false;
alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
- if (!IS_ALIGNED(vma->node.start, alignment))
+ if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment))
return false;
return true;
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index beaf27e09e8a9..e0c2ac9c8053a 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -400,7 +400,7 @@ static int igt_check_page_sizes(struct i915_vma *vma)
* Maintaining alignment is required to utilise huge pages in the ppGGT.
*/
if (i915_gem_object_is_lmem(obj) &&
- IS_ALIGNED(vma->node.start, SZ_2M) &&
+ IS_ALIGNED(i915_vma_offset(vma), SZ_2M) &&
vma->page_sizes.sg & SZ_2M &&
vma->resource->page_sizes_gtt < SZ_2M) {
pr_err("gtt pages mismatch for LMEM, expected 2M GTT pages, sg(%u), gtt(%u)\n",
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 9a6a6b5b722b6..0650137a1509c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -193,12 +193,12 @@ static int prepare_blit(const struct tiled_blits *t,
*cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;
*cs++ = 0;
*cs++ = t->height << 16 | t->width;
- *cs++ = lower_32_bits(dst->vma->node.start);
- *cs++ = upper_32_bits(dst->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(dst->vma));
+ *cs++ = upper_32_bits(i915_vma_offset(dst->vma));
*cs++ = 0;
*cs++ = src_pitch;
- *cs++ = lower_32_bits(src->vma->node.start);
- *cs++ = upper_32_bits(src->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(src->vma));
+ *cs++ = upper_32_bits(i915_vma_offset(src->vma));
} else {
if (ver >= 6) {
*cs++ = MI_LOAD_REGISTER_IMM(1);
@@ -239,14 +239,14 @@ static int prepare_blit(const struct tiled_blits *t,
*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
*cs++ = 0;
*cs++ = t->height << 16 | t->width;
- *cs++ = lower_32_bits(dst->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(dst->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(dst->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(dst->vma));
*cs++ = 0;
*cs++ = src_pitch;
- *cs++ = lower_32_bits(src->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(src->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(src->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(src->vma));
}
*cs++ = MI_BATCH_BUFFER_END;
@@ -476,7 +476,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
{
int err;
- if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) {
+ if (drm_mm_node_allocated(&vma->node) && i915_vma_offset(vma) != addr) {
err = i915_vma_unbind_unlocked(vma);
if (err)
return err;
@@ -486,6 +486,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
if (err)
return err;
+ GEM_BUG_ON(i915_vma_offset(vma) != addr);
return 0;
}
@@ -532,8 +533,8 @@ tiled_blit(struct tiled_blits *t,
err = move_to_active(dst->vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- t->batch->node.start,
- t->batch->node.size,
+ i915_vma_offset(t->batch),
+ i915_vma_size(t->batch),
0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index d8864444432b7..8affd535a0e82 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -914,8 +914,8 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs,
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
*cmd = MI_BATCH_BUFFER_END;
__i915_gem_object_flush_map(rpcs, 0, 64);
@@ -1003,7 +1003,8 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
}
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
if (err)
goto skip_request;
@@ -1566,7 +1567,8 @@ static int write_to_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma),
+ i915_vma_size(vma), 0);
if (err)
goto skip_request;
@@ -1671,7 +1673,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
*cmd++ = reg;
- *cmd++ = vma->node.start + result;
+ *cmd++ = i915_vma_offset(vma) + result;
*cmd = MI_BATCH_BUFFER_END;
i915_gem_object_flush_map(obj);
@@ -1702,7 +1704,8 @@ static int read_from_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, flags);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma),
+ i915_vma_size(vma), flags);
if (err)
goto skip_request;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 1cae24349a96f..472145182ece7 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -1612,7 +1612,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
if (err == 0)
err = i915_vma_move_to_active(vma, rq, 0);
- err = engine->emit_bb_start(rq, vma->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
index 3c55e77b0f1b0..c23899646b117 100644
--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
+++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
@@ -62,8 +62,8 @@ igt_emit_store_dw(struct i915_vma *vma,
goto err;
}
- GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size);
- offset += vma->node.start;
+ GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > i915_vma_size(vma));
+ offset += i915_vma_offset(vma);
for (n = 0; n < count; n++) {
if (ver >= 8) {
@@ -151,7 +151,8 @@ int igt_gpu_fill_dw(struct intel_context *ce,
flags |= I915_DISPATCH_SECURE;
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
flags);
skip_request:
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index 317efb145787e..d38b914d12069 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -106,7 +106,7 @@ static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)
static u32 batch_addr(const struct batch_chunk *bc)
{
- return bc->vma->node.start;
+ return i915_vma_offset(bc->vma);
}
static void batch_add(struct batch_chunk *bc, const u32 d)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index ea775e601686d..fe2b9a9fd7c18 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -220,7 +220,8 @@ static int fence_update(struct i915_fence_reg *fence,
return ret;
}
- fence->start = vma->node.start;
+ GEM_BUG_ON(vma->fence_size > i915_vma_size(vma));
+ fence->start = i915_ggtt_offset(vma);
fence->size = vma->fence_size;
fence->stride = i915_gem_object_get_stride(vma->obj);
fence->tiling = i915_gem_object_get_tiling(vma->obj);
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index 5121e6dc2fa53..e3af081c41342 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -63,7 +63,7 @@ static int render_state_setup(struct intel_renderstate *so,
u32 s = rodata->batch[i];
if (i * 4 == rodata->reloc[reloc_index]) {
- u64 r = s + so->vma->node.start;
+ u64 r = s + i915_vma_offset(so->vma);
s = lower_32_bits(r);
if (HAS_64BIT_RELOC(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index d5d6f1fadcae3..7d6db5fc92451 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -895,7 +895,7 @@ static int clear_residuals(struct i915_request *rq)
}
ret = engine->emit_bb_start(rq,
- engine->wa_ctx.vma->node.start, 0,
+ i915_vma_offset(engine->wa_ctx.vma), 0,
0);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 881b64f3e7b99..542ce6d2de192 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -178,7 +178,7 @@ static int perf_mi_bb_start(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- batch->node.start, 8,
+ i915_vma_offset(batch), 8,
0);
if (err)
goto out;
@@ -321,7 +321,7 @@ static int perf_mi_noop(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- base->node.start, 8,
+ i915_vma_offset(base), 8,
0);
if (err)
goto out;
@@ -331,8 +331,8 @@ static int perf_mi_noop(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- nop->node.start,
- nop->node.size,
+ i915_vma_offset(nop),
+ i915_vma_size(nop),
0);
if (err)
goto out;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 2c7c053a88081..667c49c20e719 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2737,11 +2737,11 @@ static int create_gang(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_EQ_SDD;
*cs++ = 0;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(vma));
+ *cs++ = upper_32_bits(i915_vma_offset(vma));
if (*prev) {
- u64 offset = (*prev)->batch->node.start;
+ u64 offset = i915_vma_offset((*prev)->batch);
/* Terminate the spinner in the next lower priority batch. */
*cs++ = MI_STORE_DWORD_IMM_GEN4;
@@ -2769,7 +2769,7 @@ static int create_gang(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
i915_request_add(rq);
@@ -3097,7 +3097,7 @@ create_gpr_user(struct intel_engine_cs *engine,
*cs++ = MI_MATH_ADD;
*cs++ = MI_MATH_STORE(MI_MATH_REG(i), MI_MATH_REG_ACCU);
- addr = result->node.start + offset + i * sizeof(*cs);
+ addr = i915_vma_offset(result) + offset + i * sizeof(*cs);
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = CS_GPR(engine, 2 * i);
*cs++ = lower_32_bits(addr);
@@ -3107,8 +3107,8 @@ create_gpr_user(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_GTE_SDD;
*cs++ = i;
- *cs++ = lower_32_bits(result->node.start);
- *cs++ = upper_32_bits(result->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(result));
+ *cs++ = upper_32_bits(i915_vma_offset(result));
}
*cs++ = MI_BATCH_BUFFER_END;
@@ -3192,7 +3192,7 @@ create_gpr_client(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(batch, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- batch->node.start,
+ i915_vma_offset(batch),
PAGE_SIZE, 0);
i915_vma_unlock(batch);
i915_vma_unpin(batch);
@@ -3526,7 +3526,7 @@ static int smoke_submit(struct preempt_smoke *smoke,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 71263058a7b05..74f740fda0c89 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -96,7 +96,8 @@ static int hang_init(struct hang *h, struct intel_gt *gt)
static u64 hws_address(const struct i915_vma *hws,
const struct i915_request *rq)
{
- return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
+ return i915_vma_offset(hws) +
+ offset_in_page(sizeof(u32) * rq->fence.context);
}
static int move_to_active(struct i915_vma *vma,
@@ -196,8 +197,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
} else if (GRAPHICS_VER(gt->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
@@ -210,7 +211,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else if (GRAPHICS_VER(gt->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
@@ -223,7 +224,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else {
*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -235,7 +236,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
}
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
intel_gt_chipset_flush(engine->gt);
@@ -250,7 +251,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
if (GRAPHICS_VER(gt->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = rq->engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
cancel_rq:
if (err) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 82d3f8058995a..735eb557ec8c0 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1034,8 +1034,8 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
while (len--) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = hw[dw];
- *cs++ = lower_32_bits(scratch->node.start + x);
- *cs++ = upper_32_bits(scratch->node.start + x);
+ *cs++ = lower_32_bits(i915_vma_offset(scratch) + x);
+ *cs++ = upper_32_bits(i915_vma_offset(scratch) + x);
dw += 2;
x += 4;
@@ -1117,8 +1117,8 @@ record_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(b_before->node.start);
- *cs++ = upper_32_bits(b_before->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(b_before));
+ *cs++ = upper_32_bits(i915_vma_offset(b_before));
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
*cs++ = MI_SEMAPHORE_WAIT |
@@ -1133,8 +1133,8 @@ record_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(b_after->node.start);
- *cs++ = upper_32_bits(b_after->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(b_after));
+ *cs++ = upper_32_bits(i915_vma_offset(b_after));
intel_ring_advance(rq, cs);
@@ -1255,8 +1255,8 @@ static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(batch->node.start);
- *cs++ = upper_32_bits(batch->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(batch));
+ *cs++ = upper_32_bits(i915_vma_offset(batch));
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
index 70f9ac1ec2c76..87ceb0f374b67 100644
--- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
@@ -50,7 +50,7 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
} else {
*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
}
- *cs++ = vma->node.start + 4000;
+ *cs++ = i915_vma_offset(vma) + 4000;
*cs++ = STACK_MAGIC;
*cs++ = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 99a372486fb7f..eb33ba0351443 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -122,14 +122,14 @@ create_spin_counter(struct intel_engine_cs *engine,
if (srm) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));
- *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
}
}
*cs++ = MI_BATCH_BUFFER_START_GEN8;
- *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
GEM_BUG_ON(cs - base > end);
i915_gem_object_flush_map(obj);
@@ -657,7 +657,7 @@ int live_rps_frequency_cs(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
@@ -798,7 +798,7 @@ int live_rps_frequency_srm(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 21b1edc052f88..1c949d32f10eb 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -523,7 +523,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
for (i = 0; i < engine->whitelist.count; i++) {
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
struct i915_gem_ww_ctx ww;
- u64 addr = scratch->node.start;
+ u64 addr = i915_vma_offset(scratch);
struct i915_request *rq;
u32 srm, lrm, rsvd;
u32 expect;
@@ -646,7 +646,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
goto err_request;
err = engine->emit_bb_start(rq,
- batch->node.start, PAGE_SIZE,
+ i915_vma_offset(batch), PAGE_SIZE,
0);
if (err)
goto err_request;
@@ -878,7 +878,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
}
for (i = 0; i < engine->whitelist.count; i++) {
- u64 offset = results->node.start + sizeof(u32) * i;
+ u64 offset = i915_vma_offset(results) + sizeof(u32) * i;
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
/* Clear non priv flags */
@@ -952,7 +952,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce)
goto err_request;
/* Perform the writes from an unprivileged "user" batch */
- err = engine->emit_bb_start(rq, batch->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0);
err_request:
err = request_add_sync(rq, err);
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index f93e6122f2478..ddf49c2dbb917 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1471,8 +1471,8 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
/* Defer failure until attempted use */
jump_whitelist = alloc_whitelist(batch_length);
- shadow_addr = gen8_canonical_addr(shadow->node.start);
- batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);
+ shadow_addr = gen8_canonical_addr(i915_vma_offset(shadow));
+ batch_addr = gen8_canonical_addr(i915_vma_offset(batch) + batch_offset);
/*
* We use the batch length as size because the shadow object is as
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ae987e92251dd..dcc2663d47064 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -183,7 +183,7 @@ i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
stringify_vma_type(vma),
- vma->node.start, vma->node.size,
+ i915_vma_offset(vma), i915_vma_size(vma),
stringify_page_sizes(vma->resource->page_sizes_gtt,
NULL, 0));
if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0dd597a7a11f5..e10d1723d8186 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2258,7 +2258,7 @@ emit_oa_config(struct i915_perf_stream *stream,
goto err_add_request;
err = rq->engine->emit_bb_start(rq,
- vma->node.start, 0,
+ i915_vma_offset(vma), 0,
I915_DISPATCH_SECURE);
if (err)
goto err_add_request;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index c39488eb9eeba..2be43885a2b5d 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -416,8 +416,8 @@ i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res,
i915_vma_resource_init(vma_res, vma->vm, vma->pages, &vma->page_sizes,
obj->mm.rsgt, i915_gem_object_is_readonly(obj),
i915_gem_object_is_lmem(obj), obj->mm.region,
- vma->ops, vma->private, vma->node.start,
- vma->node.size, vma->size);
+ vma->ops, vma->private, __i915_vma_offset(vma),
+ __i915_vma_size(vma), vma->size);
}
/**
@@ -445,7 +445,7 @@ int i915_vma_bind(struct i915_vma *vma,
lockdep_assert_held(&vma->vm->mutex);
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(vma->size > vma->node.size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start,
vma->node.size,
@@ -567,8 +567,8 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
vma->obj->base.size);
} else if (i915_vma_is_map_and_fenceable(vma)) {
ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
- vma->node.start,
- vma->node.size);
+ i915_vma_offset(vma),
+ i915_vma_size(vma));
} else {
ptr = (void __iomem *)
i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
@@ -657,22 +657,22 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
if (test_bit(I915_VMA_ERROR_BIT, __i915_vma_flags(vma)))
return true;
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return true;
GEM_BUG_ON(alignment && !is_power_of_2(alignment));
- if (alignment && !IS_ALIGNED(vma->node.start, alignment))
+ if (alignment && !IS_ALIGNED(i915_vma_offset(vma), alignment))
return true;
if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma))
return true;
if (flags & PIN_OFFSET_BIAS &&
- vma->node.start < (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) < (flags & PIN_OFFSET_MASK))
return true;
if (flags & PIN_OFFSET_FIXED &&
- vma->node.start != (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
return true;
return false;
@@ -685,10 +685,11 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- fenceable = (vma->node.size >= vma->fence_size &&
- IS_ALIGNED(vma->node.start, vma->fence_alignment));
+ fenceable = (i915_vma_size(vma) >= vma->fence_size &&
+ IS_ALIGNED(i915_vma_offset(vma), vma->fence_alignment));
- mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end;
+ mappable = i915_ggtt_offset(vma) + vma->fence_size <=
+ i915_vm_to_ggtt(vma->vm)->mappable_end;
if (mappable && fenceable)
set_bit(I915_VMA_CAN_FENCE_BIT, __i915_vma_flags(vma));
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index aecd9c64486b2..0954f8a933869 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -124,13 +124,58 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
return !list_empty(&vma->closed_link);
}
+/* Internal use only. */
+static inline u64 __i915_vma_size(const struct i915_vma *vma)
+{
+ return vma->node.size;
+}
+
+/**
+ * i915_vma_offset - Obtain the va range size of the vma
+ * @vma: The vma
+ *
+ * GPU virtual address space may be allocated with padding. This
+ * function returns the effective virtual address range size
+ * with padding subtracted.
+ *
+ * Return: The effective virtual address range size.
+ */
+static inline u64 i915_vma_size(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return __i915_vma_size(vma);
+}
+
+/* Internal use only. */
+static inline u64 __i915_vma_offset(const struct i915_vma *vma)
+{
+ return vma->node.start;
+}
+
+/**
+ * i915_vma_offset - Obtain the va offset of the vma
+ * @vma: The vma
+ *
+ * GPU virtual address space may be allocated with padding. This
+ * function returns the effective virtual address offset the gpu
+ * should use to access the bound data.
+ *
+ * Return: The effective virtual address offset.
+ */
+static inline u64 i915_vma_offset(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return __i915_vma_offset(vma);
+}
+
static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
{
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(upper_32_bits(vma->node.start));
- GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1));
- return lower_32_bits(vma->node.start);
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma)));
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) +
+ i915_vma_size(vma) - 1));
+ return lower_32_bits(i915_vma_offset(vma));
}
static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
diff --git a/drivers/gpu/drm/i915/i915_vma_resource.h b/drivers/gpu/drm/i915/i915_vma_resource.h
index 06923d1816e7e..54edf3739ca0b 100644
--- a/drivers/gpu/drm/i915/i915_vma_resource.h
+++ b/drivers/gpu/drm/i915/i915_vma_resource.h
@@ -52,8 +52,10 @@ struct i915_page_sizes {
* @mr: The memory region of the object pointed to by the vma.
* @ops: Pointer to the backend i915_vma_ops.
* @private: Bind backend private info.
- * @start: Offset into the address space of bind range start.
- * @node_size: Size of the allocated range manager node.
+ * @start: Offset into the address space of bind range start. Note that
+ * this is after any padding that might have been allocated.
+ * @node_size: Size of the allocated range manager node with padding
+ * subtracted.
* @vma_size: Bind size.
* @page_sizes_gtt: Resulting page sizes from the bind operation.
* @bound_flags: Flags indicating binding status.
@@ -174,8 +176,8 @@ static inline void i915_vma_resource_put(struct i915_vma_resource *vma_res)
* @mr: The memory region of the object the vma points to.
* @ops: The backend ops.
* @private: Bind backend private info.
- * @start: Offset into the address space of bind range start.
- * @node_size: Size of the allocated range manager node.
+ * @start: Offset into the address space of bind range start after padding.
+ * @node_size: Size of the allocated range manager node minus padding.
* @size: Bind size.
*
* Initializes a vma resource allocated using i915_vma_resource_alloc().
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index 4380473ceb986..3db386e6bafdf 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -1017,8 +1017,8 @@ empty_request(struct intel_engine_cs *engine,
return request;
err = engine->emit_bb_start(request,
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
I915_DISPATCH_SECURE);
if (err)
goto out_request;
@@ -1138,14 +1138,14 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
if (ver >= 8) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
} else if (ver >= 6) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
} else {
*cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
}
*cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
@@ -1229,8 +1229,8 @@ static int live_all_engines(void *arg)
GEM_BUG_ON(err);
err = engine->emit_bb_start(request[idx],
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
GEM_BUG_ON(err);
request[idx]->batch = batch;
@@ -1359,8 +1359,8 @@ static int live_sequential_engines(void *arg)
GEM_BUG_ON(err);
err = engine->emit_bb_start(request[idx],
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
GEM_BUG_ON(err);
request[idx]->batch = batch;
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 0c22594ae2746..4b8dc72d499f3 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -116,7 +116,7 @@ static unsigned int seqno_offset(u64 fence)
static u64 hws_address(const struct i915_vma *hws,
const struct i915_request *rq)
{
- return hws->node.start + seqno_offset(rq->fence.context);
+ return i915_vma_offset(hws) + seqno_offset(rq->fence.context);
}
static int move_to_active(struct i915_vma *vma,
@@ -203,8 +203,8 @@ igt_spinner_create_request(struct igt_spinner *spin,
*batch++ = MI_BATCH_BUFFER_START;
else
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
@@ -219,7 +219,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
flags = 0;
if (GRAPHICS_VER(rq->engine->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
cancel_rq:
if (err) {
--
2.37.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size
2022-11-09 16:49 [PATCH 0/3] add guard patting around i915_vma Andi Shyti
@ 2022-11-09 16:49 ` Andi Shyti
0 siblings, 0 replies; 25+ messages in thread
From: Andi Shyti @ 2022-11-09 16:49 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Chris Wilson, Matthew Auld, Tejas Upadhyay
From: Chris Wilson <chris@chris-wilson.co.uk>
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_node
allocation. That is we will offset the vma->pages so that the first page
is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
All users must then not use i915_vma.node.start directly, but compute
the guard offset, thus all users are converted to use a
i915_vma_offset() wrapper.
The notable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpt.c | 4 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 37 ++++++++++---------
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 15 ++++----
.../drm/i915/gem/selftests/i915_gem_context.c | 19 +++++++---
.../drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
.../drm/i915/gem/selftests/igt_gem_utils.c | 7 ++--
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 8 ++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 7 +++-
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 12 +++---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 ++++-----
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 17 +++++----
drivers/gpu/drm/i915/gt/selftest_lrc.c | 16 ++++----
.../drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 12 +++---
.../gpu/drm/i915/gt/selftest_workarounds.c | 8 ++--
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 21 ++++++-----
drivers/gpu/drm/i915/i915_vma.h | 23 ++++++++++--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 +++++-
drivers/gpu/drm/i915/selftests/i915_request.c | 20 +++++-----
drivers/gpu/drm/i915/selftests/igt_spinner.c | 11 ++++--
35 files changed, 178 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c
index de62bd77b15e6..eb32d7b0d25e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -64,7 +64,7 @@ static void dpt_insert_entries(struct i915_address_space *vm,
* not to allow the user to override access to a read only page.
*/
- i = vma->node.start / I915_GTT_PAGE_SIZE;
+ i = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, sgt_iter, vma->pages)
gen8_set_pte(&base[i++], pte_encode | addr);
}
@@ -104,7 +104,7 @@ static void dpt_bind_vma(struct i915_address_space *vm,
static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
{
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_vma_offset(vma), vma->size);
}
static void dpt_cleanup(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f72..dcd57421749ea 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -261,7 +261,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
+ (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
info->fix.smem_len = vma->node.size;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 78ac4ec9f285c..075d4afdd8a85 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -363,22 +363,23 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
const struct i915_vma *vma,
unsigned int flags)
{
- if (vma->node.size < entry->pad_to_size)
+ const u64 start = i915_vma_offset(vma);
+ const u64 size = i915_vma_size(vma);
+
+ if (size < entry->pad_to_size)
return true;
- if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
+ if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
return true;
- if (flags & EXEC_OBJECT_PINNED &&
- vma->node.start != entry->offset)
+ if (flags & EXEC_OBJECT_PINNED && start != entry->offset)
return true;
- if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
- vma->node.start < BATCH_OFFSET_BIAS)
+ if (flags & __EXEC_OBJECT_NEEDS_BIAS && start < BATCH_OFFSET_BIAS)
return true;
if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
- (vma->node.start + vma->node.size + 4095) >> 32)
+ (start + size + 4095) >> 32)
return true;
if (flags & __EXEC_OBJECT_NEEDS_MAP &&
@@ -424,7 +425,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
int err;
if (vma->node.size)
- pin_flags = vma->node.start;
+ pin_flags = __i915_vma_offset(vma);
else
pin_flags = entry->offset & PIN_OFFSET_MASK;
@@ -608,8 +609,8 @@ static int eb_reserve_vma(struct i915_execbuffer *eb,
if (err)
return err;
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
@@ -952,8 +953,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
return err;
if (!err) {
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
} else {
@@ -1034,7 +1035,7 @@ static inline u64
relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
const struct i915_vma *target)
{
- return gen8_canonical_addr((int)reloc->delta + target->node.start);
+ return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target));
}
static void reloc_cache_init(struct reloc_cache *cache,
@@ -1190,7 +1191,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
if (err) /* no inactive aperture space, use cpu reloc */
return NULL;
} else {
- cache->node.start = vma->node.start;
+ cache->node.start = i915_ggtt_offset(vma);
cache->node.mm = (void *)vma;
}
}
@@ -1284,7 +1285,7 @@ relocate_entry(struct i915_vma *vma,
goto repeat;
}
- return target->node.start | UPDATE;
+ return i915_vma_offset(target) | UPDATE;
}
static u64
@@ -1348,7 +1349,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
* more work needs to be done.
*/
if (!DBG_FORCE_RELOC &&
- gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
+ gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset)
return 0;
/* Check that the relocation address is valid... */
@@ -2191,7 +2192,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch)
}
err = eb->engine->emit_bb_start(eb->request,
- batch->node.start +
+ i915_vma_offset(batch) +
eb->batch_start_offset,
eb->batch_len,
eb->batch_flags);
@@ -2201,7 +2202,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch)
if (eb->trampoline) {
GEM_BUG_ON(eb->batch_start_offset);
err = eb->engine->emit_bb_start(eb->request,
- eb->trampoline->node.start +
+ i915_vma_offset(eb->trampoline) +
eb->batch_len,
0, 0);
if (err)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 165746db37a53..fe4e275b88f4b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -378,7 +378,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
- (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
+ (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
min_t(u64, vma->size, area->vm_end - area->vm_start),
&ggtt->iomap);
if (ret)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 7af6cbd9ede52..6af7baaf26f8c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -402,7 +402,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
mutex_lock(&i915->ggtt.vm.mutex);
list_for_each_entry_safe(vma, next,
&i915->ggtt.vm.bound_list, vm_link) {
- unsigned long count = vma->node.size >> PAGE_SHIFT;
+ unsigned long count = i915_vma_size(vma) >> PAGE_SHIFT;
if (!vma->iomap || i915_vma_is_active(vma))
continue;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index ef4d0f7dc1186..1e49c7c69d803 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -166,11 +166,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma,
return true;
size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return false;
alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
- if (!IS_ALIGNED(vma->node.start, alignment))
+ if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment))
return false;
return true;
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 149f62221a83c..c77932cb18ad5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -380,7 +380,7 @@ static int igt_check_page_sizes(struct i915_vma *vma)
* Maintaining alignment is required to utilise huge pages in the ppGGT.
*/
if (i915_gem_object_is_lmem(obj) &&
- IS_ALIGNED(vma->node.start, SZ_2M) &&
+ IS_ALIGNED(i915_vma_offset(vma), SZ_2M) &&
vma->page_sizes.sg & SZ_2M &&
vma->page_sizes.gtt < SZ_2M) {
pr_err("gtt pages mismatch for LMEM, expected 2M GTT pages, sg(%u), gtt(%u)\n",
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ecbcbb86ae1e5..2099641aa5151 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -87,14 +87,14 @@ static int prepare_blit(const struct tiled_blits *t,
*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
*cs++ = 0;
*cs++ = t->height << 16 | t->width;
- *cs++ = lower_32_bits(dst->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(dst->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(dst->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(dst->vma));
*cs++ = 0;
*cs++ = src_pitch;
- *cs++ = lower_32_bits(src->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(src->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(src->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(src->vma));
*cs++ = MI_BATCH_BUFFER_END;
@@ -310,7 +310,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
{
int err;
- if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) {
+ if (drm_mm_node_allocated(&vma->node) && i915_vma_offset(vma) != addr) {
err = i915_vma_unbind(vma);
if (err)
return err;
@@ -320,6 +320,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
if (err)
return err;
+ GEM_BUG_ON(i915_vma_offset(vma) != addr);
return 0;
}
@@ -366,8 +367,8 @@ tiled_blit(struct tiled_blits *t,
err = move_to_active(dst->vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- t->batch->node.start,
- t->batch->node.size,
+ i915_vma_offset(t->batch),
+ i915_vma_size(t->batch),
0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 8eb5050f8cb3e..b3c3c303f8db7 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -901,8 +901,8 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
*cmd = MI_BATCH_BUFFER_END;
__i915_gem_object_flush_map(rpcs, 0, 64);
@@ -990,7 +990,8 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
}
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
if (err)
goto skip_request;
@@ -1559,7 +1560,10 @@ static int write_to_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
+ 0);
if (err)
goto skip_request;
@@ -1666,7 +1670,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
*cmd++ = reg;
- *cmd++ = vma->node.start + result;
+ *cmd++ = i915_vma_offset(vma) + result;
*cmd = MI_BATCH_BUFFER_END;
i915_gem_object_flush_map(obj);
@@ -1697,7 +1701,10 @@ static int read_from_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, flags);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
+ flags);
if (err)
goto skip_request;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index bc7922cb41f97..ba135571cfea4 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -1194,7 +1194,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
if (err == 0)
err = i915_vma_move_to_active(vma, rq, 0);
- err = engine->emit_bb_start(rq, vma->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
index b35c1219c8521..548c5d6cd19d7 100644
--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
+++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
@@ -61,8 +61,8 @@ igt_emit_store_dw(struct i915_vma *vma,
goto err;
}
- GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size);
- offset += vma->node.start;
+ GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > i915_vma_size(vma));
+ offset += i915_vma_offset(vma);
for (n = 0; n < count; n++) {
if (ver >= 8) {
@@ -150,7 +150,8 @@ int igt_gpu_fill_dw(struct intel_context *ce,
flags |= I915_DISPATCH_SECURE;
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
flags);
skip_request:
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 890191f286e38..56085778645d4 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -110,7 +110,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
{
struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_directory * const pd = ppgtt->pd;
- unsigned int first_entry = vma->node.start / I915_GTT_PAGE_SIZE;
+ unsigned int first_entry = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
unsigned int act_pt = first_entry / GEN6_PTES;
unsigned int act_pte = first_entry % GEN6_PTES;
const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index 21f08e53889c3..a14f962aaa85c 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -105,7 +105,7 @@ static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)
static u32 batch_addr(const struct batch_chunk *bc)
{
- return bc->vma->node.start;
+ return i915_vma_offset(bc->vma);
}
static void batch_add(struct batch_chunk *bc, const u32 d)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index da4aa73f46a90..f74e13999402f 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -461,7 +461,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
{
const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
- u64 start = vma->node.start;
+ u64 start = i915_vma_offset(vma);
GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm));
@@ -543,8 +543,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
if (maybe_64K != -1 &&
(index == I915_PDES ||
(i915_vm_has_scratch_64K(vma->vm) &&
- !iter->sg && IS_ALIGNED(vma->node.start +
- vma->node.size,
+ !iter->sg && IS_ALIGNED(i915_vma_offset(vma) +
+ i915_vma_size(vma),
I915_GTT_PAGE_SIZE_2M)))) {
vaddr = px_vaddr(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
@@ -586,7 +586,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
gen8_ppgtt_insert_huge(vma, &iter, cache_level, flags);
} else {
- u64 idx = vma->node.start >> GEN8_PTE_SHIFT;
+ u64 idx = i915_vma_offset(vma) >> GEN8_PTE_SHIFT;
do {
struct i915_page_directory * const pdp =
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 71db07144f51a..6549b8e3adbfc 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -661,7 +661,7 @@ static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
struct i915_vma *vma)
{
if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_ggtt_offset(vma), vma->size);
if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND))
ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f8948de720360..b6fea674e6a5b 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -215,7 +215,8 @@ static int fence_update(struct i915_fence_reg *fence,
return ret;
}
- fence->start = vma->node.start;
+ GEM_BUG_ON(vma->fence_size > i915_vma_size(vma));
+ fence->start = i915_ggtt_offset(vma);
fence->size = vma->fence_size;
fence->stride = i915_gem_object_get_stride(vma->obj);
fence->tiling = i915_gem_object_get_tiling(vma->obj);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 4396bfd630d89..233e28eb74c36 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -186,7 +186,10 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
u32 pte_flags;
if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) {
- vm->allocate_va_range(vm, stash, vma->node.start, vma->size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
+ vm->allocate_va_range(vm, stash,
+ i915_vma_offset(vma),
+ vma->size);
set_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma));
}
@@ -204,7 +207,7 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
{
if (test_and_clear_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma)))
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_vma_offset(vma), vma->size);
}
static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index b575cd6e0b7a8..2630fe6c81428 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -61,7 +61,7 @@ static int render_state_setup(struct intel_renderstate *so,
u32 s = rodata->batch[i];
if (i * 4 == rodata->reloc[reloc_index]) {
- u64 r = s + so->vma->node.start;
+ u64 r = s + i915_vma_offset(so->vma);
s = lower_32_bits(r);
if (HAS_64BIT_RELOC(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index dc4d34dc12a26..e5b80b2b723ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -886,7 +886,7 @@ static int clear_residuals(struct i915_request *rq)
}
ret = engine->emit_bb_start(rq,
- engine->wa_ctx.vma->node.start, 0,
+ i915_vma_offset(engine->wa_ctx.vma), 0,
0);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 64abf5feabfaa..17ab003f905ec 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -165,8 +165,8 @@ static int perf_mi_bb_start(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- batch->node.start, 8,
- 0);
+ i915_vma_offset(batch),
+ 8, 0);
if (err)
goto out;
@@ -305,8 +305,8 @@ static int perf_mi_noop(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- base->node.start, 8,
- 0);
+ i915_vma_offset(base),
+ 8, 0);
if (err)
goto out;
@@ -315,8 +315,8 @@ static int perf_mi_noop(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- nop->node.start,
- nop->node.size,
+ i915_vma_offset(nop),
+ i915_vma_size(nop),
0);
if (err)
goto out;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index f12ffe7976394..fc23c9a1d7860 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2732,11 +2732,11 @@ static int create_gang(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_EQ_SDD;
*cs++ = 0;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(vma));
+ *cs++ = upper_32_bits(i915_vma_offset(vma));
if (*prev) {
- u64 offset = (*prev)->batch->node.start;
+ u64 offset = i915_vma_offset((*prev)->batch);
/* Terminate the spinner in the next lower priority batch. */
*cs++ = MI_STORE_DWORD_IMM_GEN4;
@@ -2764,7 +2764,7 @@ static int create_gang(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
i915_request_add(rq);
@@ -3092,7 +3092,7 @@ create_gpr_user(struct intel_engine_cs *engine,
*cs++ = MI_MATH_ADD;
*cs++ = MI_MATH_STORE(MI_MATH_REG(i), MI_MATH_REG_ACCU);
- addr = result->node.start + offset + i * sizeof(*cs);
+ addr = i915_vma_offset(result) + offset + i * sizeof(*cs);
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = CS_GPR(engine, 2 * i);
*cs++ = lower_32_bits(addr);
@@ -3102,8 +3102,8 @@ create_gpr_user(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_GTE_SDD;
*cs++ = i;
- *cs++ = lower_32_bits(result->node.start);
- *cs++ = upper_32_bits(result->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(result));
+ *cs++ = upper_32_bits(i915_vma_offset(result));
}
*cs++ = MI_BATCH_BUFFER_END;
@@ -3187,7 +3187,7 @@ create_gpr_client(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(batch, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- batch->node.start,
+ i915_vma_offset(batch),
PAGE_SIZE, 0);
i915_vma_unlock(batch);
i915_vma_unpin(batch);
@@ -3519,7 +3519,7 @@ static int smoke_submit(struct preempt_smoke *smoke,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 8af4f31e55e6f..13734a72e092a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -94,7 +94,8 @@ static int hang_init(struct hang *h, struct intel_gt *gt)
static u64 hws_address(const struct i915_vma *hws,
const struct i915_request *rq)
{
- return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
+ return (i915_vma_offset(hws) +
+ offset_in_page(sizeof(u32) * rq->fence.context));
}
static int move_to_active(struct i915_vma *vma,
@@ -194,8 +195,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
} else if (GRAPHICS_VER(gt->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
@@ -208,7 +209,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else if (GRAPHICS_VER(gt->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
@@ -221,7 +222,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else {
*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -233,7 +234,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
}
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
intel_gt_chipset_flush(engine->gt);
@@ -248,7 +249,9 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
if (GRAPHICS_VER(gt->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = rq->engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ PAGE_SIZE, flags);
cancel_rq:
if (err) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 88c9a02fbb720..b99e6dd0904a3 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -955,8 +955,8 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
while (len--) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = hw[dw];
- *cs++ = lower_32_bits(scratch->node.start + x);
- *cs++ = upper_32_bits(scratch->node.start + x);
+ *cs++ = lower_32_bits(i915_vma_offset(scratch) + x);
+ *cs++ = upper_32_bits(i915_vma_offset(scratch) + x);
dw += 2;
x += 4;
@@ -1038,8 +1038,8 @@ record_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(b_before->node.start);
- *cs++ = upper_32_bits(b_before->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(b_before));
+ *cs++ = upper_32_bits(i915_vma_offset(b_before));
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
*cs++ = MI_SEMAPHORE_WAIT |
@@ -1054,8 +1054,8 @@ record_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(b_after->node.start);
- *cs++ = upper_32_bits(b_after->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(b_after));
+ *cs++ = upper_32_bits(i915_vma_offset(b_after));
intel_ring_advance(rq, cs);
@@ -1163,8 +1163,8 @@ static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(batch->node.start);
- *cs++ = upper_32_bits(batch->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(batch));
+ *cs++ = upper_32_bits(i915_vma_offset(batch));
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
index 041954408d0fd..8d29f6b979bd6 100644
--- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
@@ -50,7 +50,7 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
} else {
*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
}
- *cs++ = vma->node.start + 4000;
+ *cs++ = i915_vma_offset(vma) + 4000;
*cs++ = STACK_MAGIC;
*cs++ = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index e2f8a7f12215a..b94587ae54f1f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -119,14 +119,14 @@ create_spin_counter(struct intel_engine_cs *engine,
if (srm) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));
- *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
}
}
*cs++ = MI_BATCH_BUFFER_START_GEN8;
- *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
GEM_BUG_ON(cs - base > end);
i915_gem_object_flush_map(obj);
@@ -654,7 +654,7 @@ int live_rps_frequency_cs(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
@@ -795,7 +795,7 @@ int live_rps_frequency_srm(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index e623ac45f4aa6..b67774f918c90 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -522,7 +522,6 @@ static int check_dirty_whitelist(struct intel_context *ce)
for (i = 0; i < engine->whitelist.count; i++) {
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
struct i915_gem_ww_ctx ww;
- u64 addr = scratch->node.start;
struct i915_request *rq;
u32 srm, lrm, rsvd;
u32 expect;
@@ -645,7 +644,8 @@ static int check_dirty_whitelist(struct intel_context *ce)
goto err_request;
err = engine->emit_bb_start(rq,
- batch->node.start, PAGE_SIZE,
+ i915_vma_offset(batch),
+ PAGE_SIZE,
0);
if (err)
goto err_request;
@@ -877,7 +877,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
}
for (i = 0; i < engine->whitelist.count; i++) {
- u64 offset = results->node.start + sizeof(u32) * i;
+ u64 offset = i915_vma_offset(results) + sizeof(u32) * i;
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
/* Clear non priv flags */
@@ -951,7 +951,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce)
goto err_request;
/* Perform the writes from an unprivileged "user" batch */
- err = engine->emit_bb_start(rq, batch->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0);
err_request:
err = request_add_sync(rq, err);
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 20191a32478ad..ff3f2d431cafb 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1463,8 +1463,8 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
/* Defer failure until attempted use */
jump_whitelist = alloc_whitelist(batch_length);
- shadow_addr = gen8_canonical_addr(shadow->node.start);
- batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);
+ shadow_addr = gen8_canonical_addr(i915_vma_offset(shadow));
+ batch_addr = gen8_canonical_addr(i915_vma_offset(batch) + batch_offset);
/*
* We use the batch length as size because the shadow object is as
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6bba248efdfc2..37083faa01870 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -168,7 +168,8 @@ i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
stringify_vma_type(vma),
- vma->node.start, vma->node.size,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
switch (vma->ggtt_view.type) {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index eb44056d71c9d..1159b8dc51868 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1015,8 +1015,8 @@ i915_vma_coredump_create(const struct intel_gt *gt,
strcpy(dst->name, name);
dst->next = NULL;
- dst->gtt_offset = vma->node.start;
- dst->gtt_size = vma->node.size;
+ dst->gtt_offset = i915_vma_offset(vma);
+ dst->gtt_size = i915_vma_size(vma);
dst->gtt_page_sizes = vma->page_sizes.gtt;
dst->num_pages = num_pages;
dst->page_count = 0;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f3c8f87d25ae0..80933688d2ec3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2015,7 +2015,7 @@ emit_oa_config(struct i915_perf_stream *stream,
goto err_add_request;
err = rq->engine->emit_bb_start(rq,
- vma->node.start, 0,
+ i915_vma_offset(vma), 0,
I915_DISPATCH_SECURE);
if (err)
goto err_add_request;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index dfd20060812bc..4b4a6dcdc676b 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -377,7 +377,7 @@ int i915_vma_bind(struct i915_vma *vma,
u32 vma_flags;
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(vma->size > vma->node.size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start,
vma->node.size,
@@ -469,8 +469,8 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
vma->obj->base.size);
else
ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
- vma->node.start,
- vma->node.size);
+ i915_vma_offset(vma),
+ i915_vma_size(vma));
if (ptr == NULL) {
err = -ENOMEM;
goto err;
@@ -544,22 +544,22 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
if (test_bit(I915_VMA_ERROR_BIT, __i915_vma_flags(vma)))
return true;
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return true;
GEM_BUG_ON(alignment && !is_power_of_2(alignment));
- if (alignment && !IS_ALIGNED(vma->node.start, alignment))
+ if (alignment && !IS_ALIGNED(i915_vma_offset(vma), alignment))
return true;
if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma))
return true;
if (flags & PIN_OFFSET_BIAS &&
- vma->node.start < (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) < (flags & PIN_OFFSET_MASK))
return true;
if (flags & PIN_OFFSET_FIXED &&
- vma->node.start != (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
return true;
return false;
@@ -572,10 +572,11 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- fenceable = (vma->node.size >= vma->fence_size &&
- IS_ALIGNED(vma->node.start, vma->fence_alignment));
+ fenceable = (i915_vma_size(vma) >= vma->fence_size &&
+ IS_ALIGNED(i915_vma_offset(vma), vma->fence_alignment));
- mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end;
+ mappable = (i915_ggtt_offset(vma) + vma->fence_size <=
+ i915_vm_to_ggtt(vma->vm)->mappable_end);
if (mappable && fenceable)
set_bit(I915_VMA_CAN_FENCE_BIT, __i915_vma_flags(vma));
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index ed69f66c7ab04..caf6e251782d8 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -118,13 +118,30 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
return !list_empty(&vma->closed_link);
}
+static inline u64 i915_vma_size(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return vma->node.size;
+}
+
+static inline u64 __i915_vma_offset(const struct i915_vma *vma)
+{
+ return vma->node.start;
+}
+
+static inline u64 i915_vma_offset(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return __i915_vma_offset(vma);
+}
+
static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
{
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(upper_32_bits(vma->node.start));
- GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1));
- return lower_32_bits(vma->node.start);
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma)));
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) + i915_vma_size(vma) - 1));
+ return lower_32_bits(i915_vma_offset(vma));
}
static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index f0645807518e9..288aadbca97f7 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -245,6 +245,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
if (!mock_vma)
return -ENOMEM;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &mock_vma->node.flags);
+ if (i915_is_ggtt(vm))
+ __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(mock_vma));
+
/* Keep creating larger objects until one cannot fit into the hole */
for (size = 12; (hole_end - hole_start) >> size; size++) {
I915_RND_SUBSTATE(prng, seed_prng);
@@ -1982,6 +1986,7 @@ static int igt_cs_tlb(void *arg)
goto end;
/* Prime the TLB with the dummy pages */
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
for (i = 0; i < count; i++) {
vma->node.start = offset + i * PAGE_SIZE;
vm->insert_entries(vm, vma, I915_CACHE_NONE, 0);
@@ -1993,8 +1998,9 @@ static int igt_cs_tlb(void *arg)
}
i915_request_put(rq);
}
-
vma->ops->clear_pages(vma);
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
+ &vma->node.flags);
err = context_sync(ce);
if (err) {
@@ -2014,6 +2020,7 @@ static int igt_cs_tlb(void *arg)
goto end;
/* Replace the TLB with target batches */
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
for (i = 0; i < count; i++) {
struct i915_request *rq;
u32 *cs = batch + i * 64 / sizeof(*cs);
@@ -2046,8 +2053,9 @@ static int igt_cs_tlb(void *arg)
i915_request_put(rq);
}
end_spin(batch, count - 1);
-
vma->ops->clear_pages(vma);
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
+ &vma->node.flags);
err = context_sync(ce);
if (err) {
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index d67710d10615d..4760cba852510 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -869,8 +869,8 @@ empty_request(struct intel_engine_cs *engine,
return request;
err = engine->emit_bb_start(request,
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
I915_DISPATCH_SECURE);
if (err)
goto out_request;
@@ -990,14 +990,14 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
if (ver >= 8) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
} else if (ver >= 6) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
} else {
*cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
}
*cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
@@ -1081,8 +1081,8 @@ static int live_all_engines(void *arg)
GEM_BUG_ON(err);
err = engine->emit_bb_start(request[idx],
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
GEM_BUG_ON(err);
request[idx]->batch = batch;
@@ -1211,8 +1211,8 @@ static int live_sequential_engines(void *arg)
GEM_BUG_ON(err);
err = engine->emit_bb_start(request[idx],
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
GEM_BUG_ON(err);
request[idx]->batch = batch;
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 24d87d0fc747e..6bf0b189d69a0 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -115,7 +115,7 @@ static unsigned int seqno_offset(u64 fence)
static u64 hws_address(const struct i915_vma *hws,
const struct i915_request *rq)
{
- return hws->node.start + seqno_offset(rq->fence.context);
+ return i915_vma_offset(hws) + seqno_offset(rq->fence.context);
}
static int move_to_active(struct i915_vma *vma,
@@ -202,8 +202,8 @@ igt_spinner_create_request(struct igt_spinner *spin,
*batch++ = MI_BATCH_BUFFER_START;
else
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
@@ -218,7 +218,10 @@ igt_spinner_create_request(struct igt_spinner *spin,
flags = 0;
if (GRAPHICS_VER(rq->engine->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ PAGE_SIZE,
+ flags);
cancel_rq:
if (err) {
--
2.37.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size
2021-12-02 8:31 ` [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Tejas Upadhyay
@ 2021-12-03 9:02 ` Ramalingam C
0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2021-12-03 9:02 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
On 2021-12-02 at 14:01:23 +0530, Tejas Upadhyay wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> We already wrap i915_vma.node.start for use with the GGTT, as there we
> can perform additional sanity checks that the node belongs to the GGTT
> and fits within the 32b registers. In the next couple of patches, we
> will introduce guard pages around the objects _inside_ the drm_mm_node
> allocation. That is we will offset the vma->pages so that the first page
> is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
> All users must then not use i915_vma.node.start directly, but compute
> the guard offset, thus all users are converted to use a
> i915_vma_offset() wrapper.
>
> The notable exceptions are the selftests that are testing exact
> behaviour of i915_vma_pin/i915_vma_insert.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Looks good to me too.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpt.c | 4 +--
> drivers/gpu/drm/i915/display/intel_fbdev.c | 6 ++--
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 34 ++++++++++---------
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +--
> .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> .../i915/gem/selftests/i915_gem_client_blt.c | 15 ++++----
> .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++++++----
> .../drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
> .../drm/i915/gem/selftests/igt_gem_utils.c | 6 ++--
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 8 ++---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 +--
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 5 +--
> drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 8 ++---
> drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 +++++-----
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 ++++----
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 16 ++++-----
> .../drm/i915/gt/selftest_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rps.c | 12 +++----
> .../gpu/drm/i915/gt/selftest_workarounds.c | 8 ++---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +--
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/i915_vma.c | 21 ++++++------
> drivers/gpu/drm/i915/i915_vma.h | 23 +++++++++++--
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 ++++++-
> drivers/gpu/drm/i915/selftests/i915_request.c | 20 +++++------
> drivers/gpu/drm/i915/selftests/igt_spinner.c | 8 ++---
> 34 files changed, 169 insertions(+), 127 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c
> index 963ca7155b06..1bb99ef4ce2d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
> @@ -64,7 +64,7 @@ static void dpt_insert_entries(struct i915_address_space *vm,
> * not to allow the user to override access to a read only page.
> */
>
> - i = vma->node.start / I915_GTT_PAGE_SIZE;
> + i = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
> for_each_sgt_daddr(addr, sgt_iter, vma->pages)
> gen8_set_pte(&base[i++], pte_encode | addr);
> }
> @@ -104,7 +104,7 @@ static void dpt_bind_vma(struct i915_address_space *vm,
>
> static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
> {
> - vm->clear_range(vm, vma->node.start, vma->size);
> + vm->clear_range(vm, i915_vma_offset(vma), vma->size);
> }
>
> static void dpt_cleanup(struct i915_address_space *vm)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
> index adc3a81be9f7..0583dcd538ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
> @@ -261,8 +261,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
>
> /* Our framebuffer is the entirety of fbdev's system memory */
> info->fix.smem_start =
> - (unsigned long)(ggtt->gmadr.start + vma->node.start);
> - info->fix.smem_len = vma->node.size;
> + (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
> + info->fix.smem_len = vma->size;
> }
>
> vaddr = i915_vma_pin_iomap(vma);
> @@ -273,7 +273,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
> goto out_unpin;
> }
> info->screen_base = vaddr;
> - info->screen_size = vma->node.size;
> + info->screen_size = vma->size;
>
> drm_fb_helper_fill_info(info, &ifbdev->helper, sizes);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 6a0ed537c199..d024b88da608 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -376,22 +376,24 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
> const struct i915_vma *vma,
> unsigned int flags)
> {
> - if (vma->node.size < entry->pad_to_size)
> + const u64 start = i915_vma_offset(vma);
> + const u64 size = i915_vma_size(vma);
> +
> + if (size < entry->pad_to_size)
> return true;
>
> - if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
> + if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
> return true;
>
> - if (flags & EXEC_OBJECT_PINNED &&
> - vma->node.start != entry->offset)
> + if (flags & EXEC_OBJECT_PINNED && start != entry->offset)
> return true;
>
> if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
> - vma->node.start < BATCH_OFFSET_BIAS)
> + start < BATCH_OFFSET_BIAS)
> return true;
>
> if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
> - (vma->node.start + vma->node.size + 4095) >> 32)
> + (start + size + 4095) >> 32)
> return true;
>
> if (flags & __EXEC_OBJECT_NEEDS_MAP &&
> @@ -437,7 +439,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
> int err;
>
> if (vma->node.size)
> - pin_flags = vma->node.start;
> + pin_flags = __i915_vma_offset(vma);
> else
> pin_flags = entry->offset & PIN_OFFSET_MASK;
>
> @@ -677,8 +679,8 @@ static int eb_reserve_vma(struct i915_execbuffer *eb,
> if (err)
> return err;
>
> - if (entry->offset != vma->node.start) {
> - entry->offset = vma->node.start | UPDATE;
> + if (entry->offset != i915_vma_offset(vma)) {
> + entry->offset = i915_vma_offset(vma) | UPDATE;
> eb->args->flags |= __EXEC_HAS_RELOC;
> }
>
> @@ -990,8 +992,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
> return err;
>
> if (!err) {
> - if (entry->offset != vma->node.start) {
> - entry->offset = vma->node.start | UPDATE;
> + if (entry->offset != i915_vma_offset(vma)) {
> + entry->offset = i915_vma_offset(vma) | UPDATE;
> eb->args->flags |= __EXEC_HAS_RELOC;
> }
> } else {
> @@ -1073,7 +1075,7 @@ static inline u64
> relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
> const struct i915_vma *target)
> {
> - return gen8_canonical_addr((int)reloc->delta + target->node.start);
> + return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target));
> }
>
> static void reloc_cache_init(struct reloc_cache *cache,
> @@ -1229,7 +1231,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
> if (err) /* no inactive aperture space, use cpu reloc */
> return NULL;
> } else {
> - cache->node.start = vma->node.start;
> + cache->node.start = i915_ggtt_offset(vma);
> cache->node.mm = (void *)vma;
> }
> }
> @@ -1387,7 +1389,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
> * more work needs to be done.
> */
> if (!DBG_FORCE_RELOC &&
> - gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
> + gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset)
> return 0;
>
> /* Check that the relocation address is valid... */
> @@ -2331,7 +2333,7 @@ static int eb_request_submit(struct i915_execbuffer *eb,
> }
>
> err = rq->context->engine->emit_bb_start(rq,
> - batch->node.start +
> + i915_vma_offset(batch) +
> eb->batch_start_offset,
> batch_len,
> eb->batch_flags);
> @@ -2342,7 +2344,7 @@ static int eb_request_submit(struct i915_execbuffer *eb,
> GEM_BUG_ON(intel_context_is_parallel(rq->context));
> GEM_BUG_ON(eb->batch_start_offset);
> err = rq->context->engine->emit_bb_start(rq,
> - eb->trampoline->node.start +
> + i915_vma_offset(eb->trampoline) +
> batch_len, 0, 0);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index 65fc6ff5f59d..5d3fa137389e 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -378,7 +378,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
> /* Finally, remap it using the new GTT offset */
> ret = remap_io_mapping(area,
> area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
> - (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
> + (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
> min_t(u64, vma->size, area->vm_end - area->vm_start),
> &ggtt->iomap);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> index 157a9765f483..7738e97d43b0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> @@ -406,7 +406,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
> mutex_lock(&i915->ggtt.vm.mutex);
> list_for_each_entry_safe(vma, next,
> &i915->ggtt.vm.bound_list, vm_link) {
> - unsigned long count = vma->node.size >> PAGE_SHIFT;
> + unsigned long count = i915_vma_size(vma) >> PAGE_SHIFT;
>
> if (!vma->iomap || i915_vma_is_active(vma))
> continue;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> index ef4d0f7dc118..1e49c7c69d80 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> @@ -166,11 +166,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma,
> return true;
>
> size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
> - if (vma->node.size < size)
> + if (i915_vma_size(vma) < size)
> return false;
>
> alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
> - if (!IS_ALIGNED(vma->node.start, alignment))
> + if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment))
> return false;
>
> return true;
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index c69c7d45aabc..c9361ffeb5d4 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> @@ -401,7 +401,7 @@ static int igt_check_page_sizes(struct i915_vma *vma)
> * Maintaining alignment is required to utilise huge pages in the ppGGT.
> */
> if (i915_gem_object_is_lmem(obj) &&
> - IS_ALIGNED(vma->node.start, SZ_2M) &&
> + IS_ALIGNED(i915_vma_offset(vma), SZ_2M) &&
> vma->page_sizes.sg & SZ_2M &&
> vma->page_sizes.gtt < SZ_2M) {
> pr_err("gtt pages mismatch for LMEM, expected 2M GTT pages, sg(%u), gtt(%u)\n",
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> index 8402ed925a69..d383b9f53a77 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> @@ -94,14 +94,14 @@ static int prepare_blit(const struct tiled_blits *t,
> *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
> *cs++ = 0;
> *cs++ = t->height << 16 | t->width;
> - *cs++ = lower_32_bits(dst->vma->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(dst->vma));
> if (use_64b_reloc)
> - *cs++ = upper_32_bits(dst->vma->node.start);
> + *cs++ = upper_32_bits(i915_vma_offset(dst->vma));
> *cs++ = 0;
> *cs++ = src_pitch;
> - *cs++ = lower_32_bits(src->vma->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(src->vma));
> if (use_64b_reloc)
> - *cs++ = upper_32_bits(src->vma->node.start);
> + *cs++ = upper_32_bits(i915_vma_offset(src->vma));
>
> *cs++ = MI_BATCH_BUFFER_END;
>
> @@ -317,7 +317,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
> {
> int err;
>
> - if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) {
> + if (drm_mm_node_allocated(&vma->node) && i915_vma_offset(vma) != addr) {
> err = i915_vma_unbind(vma);
> if (err)
> return err;
> @@ -327,6 +327,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
> if (err)
> return err;
>
> + GEM_BUG_ON(i915_vma_offset(vma) != addr);
> return 0;
> }
>
> @@ -373,8 +374,8 @@ tiled_blit(struct tiled_blits *t,
> err = move_to_active(dst->vma, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - t->batch->node.start,
> - t->batch->node.size,
> + i915_vma_offset(t->batch),
> + i915_vma_size(t->batch),
> 0);
> i915_request_get(rq);
> i915_request_add(rq);
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index b32f7fed2d9c..fe01a7d92362 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -895,8 +895,8 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
>
> *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
> *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
> - *cmd++ = lower_32_bits(vma->node.start);
> - *cmd++ = upper_32_bits(vma->node.start);
> + *cmd++ = lower_32_bits(i915_vma_offset(vma));
> + *cmd++ = upper_32_bits(i915_vma_offset(vma));
> *cmd = MI_BATCH_BUFFER_END;
>
> __i915_gem_object_flush_map(rpcs, 0, 64);
> @@ -984,7 +984,8 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
> }
>
> err = rq->engine->emit_bb_start(rq,
> - batch->node.start, batch->node.size,
> + i915_vma_offset(batch),
> + i915_vma_size(batch),
> 0);
> if (err)
> goto skip_request;
> @@ -1553,7 +1554,10 @@ static int write_to_scratch(struct i915_gem_context *ctx,
> goto skip_request;
> }
>
> - err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
> + err = engine->emit_bb_start(rq,
> + i915_vma_offset(vma),
> + i915_vma_size(vma),
> + 0);
> if (err)
> goto skip_request;
>
> @@ -1660,7 +1664,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
> *cmd++ = offset;
> *cmd++ = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> *cmd++ = reg;
> - *cmd++ = vma->node.start + result;
> + *cmd++ = i915_vma_offset(vma) + result;
> *cmd = MI_BATCH_BUFFER_END;
>
> i915_gem_object_flush_map(obj);
> @@ -1691,7 +1695,10 @@ static int read_from_scratch(struct i915_gem_context *ctx,
> goto skip_request;
> }
>
> - err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, flags);
> + err = engine->emit_bb_start(rq,
> + i915_vma_offset(vma),
> + i915_vma_size(vma),
> + flags);
> if (err)
> goto skip_request;
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> index 6d30cdfa80f3..762881791e25 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> @@ -1196,7 +1196,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
> if (err == 0)
> err = i915_vma_move_to_active(vma, rq, 0);
>
> - err = engine->emit_bb_start(rq, vma->node.start, 0, 0);
> + err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);
> i915_request_get(rq);
> i915_request_add(rq);
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
> index b35c1219c852..4390d69bd746 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
> @@ -61,8 +61,8 @@ igt_emit_store_dw(struct i915_vma *vma,
> goto err;
> }
>
> - GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size);
> - offset += vma->node.start;
> + GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > i915_vma_size(vma));
> + offset += i915_vma_offset(vma);
>
> for (n = 0; n < count; n++) {
> if (ver >= 8) {
> @@ -150,7 +150,7 @@ int igt_gpu_fill_dw(struct intel_context *ce,
> flags |= I915_DISPATCH_SECURE;
>
> err = rq->engine->emit_bb_start(rq,
> - batch->node.start, batch->node.size,
> + i915_vma_offset(batch), i915_vma_size(batch),
> flags);
>
> skip_request:
> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> index 4a166d25fe60..72a8725e6f8a 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> @@ -110,7 +110,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
> {
> struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> struct i915_page_directory * const pd = ppgtt->pd;
> - unsigned int first_entry = vma->node.start / I915_GTT_PAGE_SIZE;
> + unsigned int first_entry = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
> unsigned int act_pt = first_entry / GEN6_PTES;
> unsigned int act_pte = first_entry % GEN6_PTES;
> const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> index 21f08e53889c..a14f962aaa85 100644
> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> @@ -105,7 +105,7 @@ static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)
>
> static u32 batch_addr(const struct batch_chunk *bc)
> {
> - return bc->vma->node.start;
> + return i915_vma_offset(bc->vma);
> }
>
> static void batch_add(struct batch_chunk *bc, const u32 d)
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 9966e9dc5218..dd2ab23a123c 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -460,7 +460,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
> {
> const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
> unsigned int rem = sg_dma_len(iter->sg);
> - u64 start = vma->node.start;
> + u64 start = i915_vma_offset(vma);
>
> GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm));
>
> @@ -542,8 +542,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
> if (maybe_64K != -1 &&
> (index == I915_PDES ||
> (i915_vm_has_scratch_64K(vma->vm) &&
> - !iter->sg && IS_ALIGNED(vma->node.start +
> - vma->node.size,
> + !iter->sg && IS_ALIGNED(i915_vma_offset(vma) +
> + i915_vma_size(vma),
> I915_GTT_PAGE_SIZE_2M)))) {
> vaddr = px_vaddr(pd);
> vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
> @@ -587,7 +587,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
> if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
> gen8_ppgtt_insert_huge(vma, &iter, cache_level, flags);
> } else {
> - u64 idx = vma->node.start >> GEN8_PTE_SHIFT;
> + u64 idx = i915_vma_offset(vma) >> GEN8_PTE_SHIFT;
>
> do {
> struct i915_page_directory * const pdp =
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 110d3944f9a2..07133f0c529e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -458,7 +458,8 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
> unsigned int flags = (cache_level == I915_CACHE_NONE) ?
> AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>
> - intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
> + intel_gtt_insert_sg_entries(vma->pages,
> + i915_ggtt_offset(vma) >> PAGE_SHIFT,
> flags);
> }
>
> @@ -649,7 +650,7 @@ static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
> struct i915_vma *vma)
> {
> if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
> - vm->clear_range(vm, vma->node.start, vma->size);
> + vm->clear_range(vm, i915_ggtt_offset(vma), vma->size);
>
> if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND))
> ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index f8948de72036..b6fea674e6a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -215,7 +215,8 @@ static int fence_update(struct i915_fence_reg *fence,
> return ret;
> }
>
> - fence->start = vma->node.start;
> + GEM_BUG_ON(vma->fence_size > i915_vma_size(vma));
> + fence->start = i915_ggtt_offset(vma);
> fence->size = vma->fence_size;
> fence->stride = i915_gem_object_get_stride(vma->obj);
> fence->tiling = i915_gem_object_get_tiling(vma->obj);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 4396bfd630d8..4773c95db012 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -186,7 +186,8 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
> u32 pte_flags;
>
> if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) {
> - vm->allocate_va_range(vm, stash, vma->node.start, vma->size);
> + GEM_BUG_ON(vma->size > i915_vma_size(vma));
> + vm->allocate_va_range(vm, stash, i915_vma_offset(vma), vma->size);
> set_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma));
> }
>
> @@ -204,7 +205,7 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
> void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
> {
> if (test_and_clear_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma)))
> - vm->clear_range(vm, vma->node.start, vma->size);
> + vm->clear_range(vm, i915_vma_offset(vma), vma->size);
> }
>
> static unsigned long pd_count(u64 size, int shift)
> diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> index b575cd6e0b7a..2630fe6c8142 100644
> --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> @@ -61,7 +61,7 @@ static int render_state_setup(struct intel_renderstate *so,
> u32 s = rodata->batch[i];
>
> if (i * 4 == rodata->reloc[reloc_index]) {
> - u64 r = s + so->vma->node.start;
> + u64 r = s + i915_vma_offset(so->vma);
>
> s = lower_32_bits(r);
> if (HAS_64BIT_RELOC(i915)) {
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 3e6fac0340ef..2c4c5c095c56 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -886,7 +886,7 @@ static int clear_residuals(struct i915_request *rq)
> }
>
> ret = engine->emit_bb_start(rq,
> - engine->wa_ctx.vma->node.start, 0,
> + i915_vma_offset(engine->wa_ctx.vma), 0,
> 0);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> index 64abf5feabfa..9e28873a7e45 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> @@ -165,7 +165,7 @@ static int perf_mi_bb_start(void *arg)
> goto out;
>
> err = rq->engine->emit_bb_start(rq,
> - batch->node.start, 8,
> + i915_vma_offset(batch), 8,
> 0);
> if (err)
> goto out;
> @@ -305,7 +305,7 @@ static int perf_mi_noop(void *arg)
> goto out;
>
> err = rq->engine->emit_bb_start(rq,
> - base->node.start, 8,
> + i915_vma_offset(base), 8,
> 0);
> if (err)
> goto out;
> @@ -315,8 +315,8 @@ static int perf_mi_noop(void *arg)
> goto out;
>
> err = rq->engine->emit_bb_start(rq,
> - nop->node.start,
> - nop->node.size,
> + i915_vma_offset(nop),
> + i915_vma_size(nop),
> 0);
> if (err)
> goto out;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> index b367ecfa42de..b803123df073 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> @@ -2732,11 +2732,11 @@ static int create_gang(struct intel_engine_cs *engine,
> MI_SEMAPHORE_POLL |
> MI_SEMAPHORE_SAD_EQ_SDD;
> *cs++ = 0;
> - *cs++ = lower_32_bits(vma->node.start);
> - *cs++ = upper_32_bits(vma->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(vma));
> + *cs++ = upper_32_bits(i915_vma_offset(vma));
>
> if (*prev) {
> - u64 offset = (*prev)->batch->node.start;
> + u64 offset = i915_vma_offset((*prev)->batch);
>
> /* Terminate the spinner in the next lower priority batch. */
> *cs++ = MI_STORE_DWORD_IMM_GEN4;
> @@ -2764,7 +2764,7 @@ static int create_gang(struct intel_engine_cs *engine,
> err = i915_vma_move_to_active(vma, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - vma->node.start,
> + i915_vma_offset(vma),
> PAGE_SIZE, 0);
> i915_vma_unlock(vma);
> i915_request_add(rq);
> @@ -3092,7 +3092,7 @@ create_gpr_user(struct intel_engine_cs *engine,
> *cs++ = MI_MATH_ADD;
> *cs++ = MI_MATH_STORE(MI_MATH_REG(i), MI_MATH_REG_ACCU);
>
> - addr = result->node.start + offset + i * sizeof(*cs);
> + addr = i915_vma_offset(result) + offset + i * sizeof(*cs);
> *cs++ = MI_STORE_REGISTER_MEM_GEN8;
> *cs++ = CS_GPR(engine, 2 * i);
> *cs++ = lower_32_bits(addr);
> @@ -3102,8 +3102,8 @@ create_gpr_user(struct intel_engine_cs *engine,
> MI_SEMAPHORE_POLL |
> MI_SEMAPHORE_SAD_GTE_SDD;
> *cs++ = i;
> - *cs++ = lower_32_bits(result->node.start);
> - *cs++ = upper_32_bits(result->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(result));
> + *cs++ = upper_32_bits(i915_vma_offset(result));
> }
>
> *cs++ = MI_BATCH_BUFFER_END;
> @@ -3187,7 +3187,7 @@ create_gpr_client(struct intel_engine_cs *engine,
> err = i915_vma_move_to_active(batch, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - batch->node.start,
> + i915_vma_offset(batch),
> PAGE_SIZE, 0);
> i915_vma_unlock(batch);
> i915_vma_unpin(batch);
> @@ -3519,7 +3519,7 @@ static int smoke_submit(struct preempt_smoke *smoke,
> err = i915_vma_move_to_active(vma, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - vma->node.start,
> + i915_vma_offset(vma),
> PAGE_SIZE, 0);
> i915_vma_unlock(vma);
> }
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index e5ad4d5a91c0..b0236c4d615c 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -94,7 +94,8 @@ static int hang_init(struct hang *h, struct intel_gt *gt)
> static u64 hws_address(const struct i915_vma *hws,
> const struct i915_request *rq)
> {
> - return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
> + return i915_vma_offset(hws) +
> + offset_in_page(sizeof(u32) * rq->fence.context);
> }
>
> static int move_to_active(struct i915_vma *vma,
> @@ -194,8 +195,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>
> *batch++ = MI_NOOP;
> *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> - *batch++ = lower_32_bits(vma->node.start);
> - *batch++ = upper_32_bits(vma->node.start);
> + *batch++ = lower_32_bits(i915_vma_offset(vma));
> + *batch++ = upper_32_bits(i915_vma_offset(vma));
> } else if (GRAPHICS_VER(gt->i915) >= 6) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = 0;
> @@ -208,7 +209,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>
> *batch++ = MI_NOOP;
> *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
> - *batch++ = lower_32_bits(vma->node.start);
> + *batch++ = lower_32_bits(i915_vma_offset(vma));
> } else if (GRAPHICS_VER(gt->i915) >= 4) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *batch++ = 0;
> @@ -221,7 +222,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>
> *batch++ = MI_NOOP;
> *batch++ = MI_BATCH_BUFFER_START | 2 << 6;
> - *batch++ = lower_32_bits(vma->node.start);
> + *batch++ = lower_32_bits(i915_vma_offset(vma));
> } else {
> *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> *batch++ = lower_32_bits(hws_address(hws, rq));
> @@ -233,7 +234,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>
> *batch++ = MI_NOOP;
> *batch++ = MI_BATCH_BUFFER_START | 2 << 6;
> - *batch++ = lower_32_bits(vma->node.start);
> + *batch++ = lower_32_bits(i915_vma_offset(vma));
> }
> *batch++ = MI_BATCH_BUFFER_END; /* not reached */
> intel_gt_chipset_flush(engine->gt);
> @@ -248,7 +249,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> if (GRAPHICS_VER(gt->i915) <= 5)
> flags |= I915_DISPATCH_SECURE;
>
> - err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
> + err = rq->engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
>
> cancel_rq:
> if (err) {
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index b0977a3b699b..ca2f2dec7089 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -955,8 +955,8 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
> while (len--) {
> *cs++ = MI_STORE_REGISTER_MEM_GEN8;
> *cs++ = hw[dw];
> - *cs++ = lower_32_bits(scratch->node.start + x);
> - *cs++ = upper_32_bits(scratch->node.start + x);
> + *cs++ = lower_32_bits(i915_vma_offset(scratch) + x);
> + *cs++ = upper_32_bits(i915_vma_offset(scratch) + x);
>
> dw += 2;
> x += 4;
> @@ -1038,8 +1038,8 @@ record_registers(struct intel_context *ce,
>
> *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
> - *cs++ = lower_32_bits(b_before->node.start);
> - *cs++ = upper_32_bits(b_before->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(b_before));
> + *cs++ = upper_32_bits(i915_vma_offset(b_before));
>
> *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> *cs++ = MI_SEMAPHORE_WAIT |
> @@ -1054,8 +1054,8 @@ record_registers(struct intel_context *ce,
>
> *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
> - *cs++ = lower_32_bits(b_after->node.start);
> - *cs++ = upper_32_bits(b_after->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(b_after));
> + *cs++ = upper_32_bits(i915_vma_offset(b_after));
>
> intel_ring_advance(rq, cs);
>
> @@ -1163,8 +1163,8 @@ static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
>
> *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
> - *cs++ = lower_32_bits(batch->node.start);
> - *cs++ = upper_32_bits(batch->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(batch));
> + *cs++ = upper_32_bits(i915_vma_offset(batch));
>
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
> diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> index 041954408d0f..8d29f6b979bd 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> @@ -50,7 +50,7 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
> } else {
> *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> }
> - *cs++ = vma->node.start + 4000;
> + *cs++ = i915_vma_offset(vma) + 4000;
> *cs++ = STACK_MAGIC;
>
> *cs++ = MI_BATCH_BUFFER_END;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
> index 7ee2513e15f9..d242ed23e609 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
> @@ -119,14 +119,14 @@ create_spin_counter(struct intel_engine_cs *engine,
> if (srm) {
> *cs++ = MI_STORE_REGISTER_MEM_GEN8;
> *cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));
> - *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs));
> - *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs));
> + *cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
> + *cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
> }
> }
>
> *cs++ = MI_BATCH_BUFFER_START_GEN8;
> - *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs));
> - *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs));
> + *cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
> + *cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
> GEM_BUG_ON(cs - base > end);
>
> i915_gem_object_flush_map(obj);
> @@ -655,7 +655,7 @@ int live_rps_frequency_cs(void *arg)
> err = i915_vma_move_to_active(vma, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - vma->node.start,
> + i915_vma_offset(vma),
> PAGE_SIZE, 0);
> i915_request_add(rq);
> if (err)
> @@ -796,7 +796,7 @@ int live_rps_frequency_srm(void *arg)
> err = i915_vma_move_to_active(vma, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - vma->node.start,
> + i915_vma_offset(vma),
> PAGE_SIZE, 0);
> i915_request_add(rq);
> if (err)
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index 962e91ba3be4..cd027e98e409 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -521,8 +521,8 @@ static int check_dirty_whitelist(struct intel_context *ce)
>
> for (i = 0; i < engine->whitelist.count; i++) {
> u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
> + u64 addr = i915_vma_offset(scratch);
> struct i915_gem_ww_ctx ww;
> - u64 addr = scratch->node.start;
> struct i915_request *rq;
> u32 srm, lrm, rsvd;
> u32 expect;
> @@ -645,7 +645,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
> goto err_request;
>
> err = engine->emit_bb_start(rq,
> - batch->node.start, PAGE_SIZE,
> + i915_vma_offset(batch), PAGE_SIZE,
> 0);
> if (err)
> goto err_request;
> @@ -877,7 +877,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
> }
>
> for (i = 0; i < engine->whitelist.count; i++) {
> - u64 offset = results->node.start + sizeof(u32) * i;
> + u64 offset = i915_vma_offset(results) + sizeof(u32) * i;
> u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
>
> /* Clear non priv flags */
> @@ -951,7 +951,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce)
> goto err_request;
>
> /* Perform the writes from an unprivileged "user" batch */
> - err = engine->emit_bb_start(rq, batch->node.start, 0, 0);
> + err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0);
>
> err_request:
> err = request_add_sync(rq, err);
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index e0403ce9ce69..c2109006df8b 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1459,8 +1459,8 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
> /* Defer failure until attempted use */
> jump_whitelist = alloc_whitelist(batch_length);
>
> - shadow_addr = gen8_canonical_addr(shadow->node.start);
> - batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);
> + shadow_addr = gen8_canonical_addr(i915_vma_offset(shadow));
> + batch_addr = gen8_canonical_addr(i915_vma_offset(batch) + batch_offset);
>
> /*
> * We use the batch length as size because the shadow object is as
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 390d541f64ea..b082af695d4e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -170,7 +170,7 @@ i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
>
> seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
> stringify_vma_type(vma),
> - vma->node.start, vma->node.size,
> + i915_vma_offset(vma), i915_vma_size(vma),
> stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
> if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
> switch (vma->ggtt_view.type) {
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 2f01b8c0284c..d6c7d90ce5cc 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2015,7 +2015,7 @@ emit_oa_config(struct i915_perf_stream *stream,
> goto err_add_request;
>
> err = rq->engine->emit_bb_start(rq,
> - vma->node.start, 0,
> + i915_vma_offset(vma), 0,
> I915_DISPATCH_SECURE);
> if (err)
> goto err_add_request;
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 927f0d4f8e11..10473ce8a047 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -399,7 +399,7 @@ int i915_vma_bind(struct i915_vma *vma,
> u32 vma_flags;
>
> GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> - GEM_BUG_ON(vma->size > vma->node.size);
> + GEM_BUG_ON(vma->size > i915_vma_size(vma));
>
> if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start,
> vma->node.size,
> @@ -494,8 +494,8 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
> vma->obj->base.size);
> else
> ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
> - vma->node.start,
> - vma->node.size);
> + i915_vma_offset(vma),
> + i915_vma_size(vma));
> if (ptr == NULL) {
> err = -ENOMEM;
> goto err;
> @@ -569,22 +569,22 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
> if (test_bit(I915_VMA_ERROR_BIT, __i915_vma_flags(vma)))
> return true;
>
> - if (vma->node.size < size)
> + if (i915_vma_size(vma) < size)
> return true;
>
> GEM_BUG_ON(alignment && !is_power_of_2(alignment));
> - if (alignment && !IS_ALIGNED(vma->node.start, alignment))
> + if (alignment && !IS_ALIGNED(i915_vma_offset(vma), alignment))
> return true;
>
> if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma))
> return true;
>
> if (flags & PIN_OFFSET_BIAS &&
> - vma->node.start < (flags & PIN_OFFSET_MASK))
> + i915_vma_offset(vma) < (flags & PIN_OFFSET_MASK))
> return true;
>
> if (flags & PIN_OFFSET_FIXED &&
> - vma->node.start != (flags & PIN_OFFSET_MASK))
> + i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
> return true;
>
> return false;
> @@ -597,10 +597,11 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
> GEM_BUG_ON(!i915_vma_is_ggtt(vma));
> GEM_BUG_ON(!vma->fence_size);
>
> - fenceable = (vma->node.size >= vma->fence_size &&
> - IS_ALIGNED(vma->node.start, vma->fence_alignment));
> + fenceable = (i915_vma_size(vma) >= vma->fence_size &&
> + IS_ALIGNED(i915_vma_offset(vma), vma->fence_alignment));
>
> - mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end;
> + mappable = i915_ggtt_offset(vma) + vma->fence_size <=
> + i915_vm_to_ggtt(vma->vm)->mappable_end;
>
> if (mappable && fenceable)
> set_bit(I915_VMA_CAN_FENCE_BIT, __i915_vma_flags(vma));
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index 4033aa08d5e4..1d13d619ff86 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -125,13 +125,30 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
> return !list_empty(&vma->closed_link);
> }
>
> +static inline u64 i915_vma_size(const struct i915_vma *vma)
> +{
> + GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> + return vma->node.size;
> +}
> +
> +static inline u64 __i915_vma_offset(const struct i915_vma *vma)
> +{
> + return vma->node.start;
> +}
> +
> +static inline u64 i915_vma_offset(const struct i915_vma *vma)
> +{
> + GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> + return __i915_vma_offset(vma);
> +}
> +
> static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
> {
> GEM_BUG_ON(!i915_vma_is_ggtt(vma));
> GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> - GEM_BUG_ON(upper_32_bits(vma->node.start));
> - GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1));
> - return lower_32_bits(vma->node.start);
> + GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma)));
> + GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) + i915_vma_size(vma) - 1));
> + return lower_32_bits(i915_vma_offset(vma));
> }
>
> static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index 46f4236039a9..89528c0d19f4 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -245,6 +245,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
> if (!mock_vma)
> return -ENOMEM;
>
> + __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &mock_vma->node.flags);
> + if (i915_is_ggtt(vm))
> + __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(mock_vma));
> +
> /* Keep creating larger objects until one cannot fit into the hole */
> for (size = 12; (hole_end - hole_start) >> size; size++) {
> I915_RND_SUBSTATE(prng, seed_prng);
> @@ -1982,6 +1986,7 @@ static int igt_cs_tlb(void *arg)
> goto end;
>
> /* Prime the TLB with the dummy pages */
> + __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
> for (i = 0; i < count; i++) {
> vma->node.start = offset + i * PAGE_SIZE;
> vm->insert_entries(vm, vma, I915_CACHE_NONE, 0);
> @@ -1995,8 +2000,10 @@ static int igt_cs_tlb(void *arg)
> }
>
> vma->ops->clear_pages(vma);
> + __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
> + &vma->node.flags);
>
> - err = context_sync(ce);
> + err = context_sync(ce);
> if (err) {
> pr_err("%s: dummy setup timed out\n",
> ce->engine->name);
> @@ -2014,6 +2021,7 @@ static int igt_cs_tlb(void *arg)
> goto end;
>
> /* Replace the TLB with target batches */
> + __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
> for (i = 0; i < count; i++) {
> struct i915_request *rq;
> u32 *cs = batch + i * 64 / sizeof(*cs);
> @@ -2048,6 +2056,8 @@ static int igt_cs_tlb(void *arg)
> end_spin(batch, count - 1);
>
> vma->ops->clear_pages(vma);
> + __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
> + &vma->node.flags);
>
> err = context_sync(ce);
> if (err) {
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
> index 9979ef9197cd..737d29bbc3b5 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_request.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c
> @@ -879,8 +879,8 @@ empty_request(struct intel_engine_cs *engine,
> return request;
>
> err = engine->emit_bb_start(request,
> - batch->node.start,
> - batch->node.size,
> + i915_vma_offset(batch),
> + i915_vma_size(batch),
> I915_DISPATCH_SECURE);
> if (err)
> goto out_request;
> @@ -1000,14 +1000,14 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
>
> if (ver >= 8) {
> *cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> - *cmd++ = lower_32_bits(vma->node.start);
> - *cmd++ = upper_32_bits(vma->node.start);
> + *cmd++ = lower_32_bits(i915_vma_offset(vma));
> + *cmd++ = upper_32_bits(i915_vma_offset(vma));
> } else if (ver >= 6) {
> *cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
> - *cmd++ = lower_32_bits(vma->node.start);
> + *cmd++ = lower_32_bits(i915_vma_offset(vma));
> } else {
> *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
> - *cmd++ = lower_32_bits(vma->node.start);
> + *cmd++ = lower_32_bits(i915_vma_offset(vma));
> }
> *cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
>
> @@ -1091,8 +1091,8 @@ static int live_all_engines(void *arg)
> GEM_BUG_ON(err);
>
> err = engine->emit_bb_start(request[idx],
> - batch->node.start,
> - batch->node.size,
> + i915_vma_offset(batch),
> + i915_vma_size(batch),
> 0);
> GEM_BUG_ON(err);
> request[idx]->batch = batch;
> @@ -1221,8 +1221,8 @@ static int live_sequential_engines(void *arg)
> GEM_BUG_ON(err);
>
> err = engine->emit_bb_start(request[idx],
> - batch->node.start,
> - batch->node.size,
> + i915_vma_offset(batch),
> + i915_vma_size(batch),
> 0);
> GEM_BUG_ON(err);
> request[idx]->batch = batch;
> diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> index 24d87d0fc747..d5939f1f14e4 100644
> --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
> +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> @@ -115,7 +115,7 @@ static unsigned int seqno_offset(u64 fence)
> static u64 hws_address(const struct i915_vma *hws,
> const struct i915_request *rq)
> {
> - return hws->node.start + seqno_offset(rq->fence.context);
> + return i915_vma_offset(hws) + seqno_offset(rq->fence.context);
> }
>
> static int move_to_active(struct i915_vma *vma,
> @@ -202,8 +202,8 @@ igt_spinner_create_request(struct igt_spinner *spin,
> *batch++ = MI_BATCH_BUFFER_START;
> else
> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
> - *batch++ = lower_32_bits(vma->node.start);
> - *batch++ = upper_32_bits(vma->node.start);
> + *batch++ = lower_32_bits(i915_vma_offset(vma));
> + *batch++ = upper_32_bits(i915_vma_offset(vma));
>
> *batch++ = MI_BATCH_BUFFER_END; /* not reached */
>
> @@ -218,7 +218,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
> flags = 0;
> if (GRAPHICS_VER(rq->engine->i915) <= 5)
> flags |= I915_DISPATCH_SECURE;
> - err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
> + err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
>
> cancel_rq:
> if (err) {
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size
2021-12-02 8:31 [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Tejas Upadhyay
@ 2021-12-02 8:31 ` Tejas Upadhyay
2021-12-03 9:02 ` Ramalingam C
0 siblings, 1 reply; 25+ messages in thread
From: Tejas Upadhyay @ 2021-12-02 8:31 UTC (permalink / raw)
To: intel-gfx
From: Chris Wilson <chris@chris-wilson.co.uk>
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_node
allocation. That is we will offset the vma->pages so that the first page
is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
All users must then not use i915_vma.node.start directly, but compute
the guard offset, thus all users are converted to use a
i915_vma_offset() wrapper.
The notable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpt.c | 4 +--
drivers/gpu/drm/i915/display/intel_fbdev.c | 6 ++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 34 ++++++++++---------
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +--
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 15 ++++----
.../drm/i915/gem/selftests/i915_gem_context.c | 19 +++++++----
.../drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
.../drm/i915/gem/selftests/igt_gem_utils.c | 6 ++--
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 8 ++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 +--
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 5 +--
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 8 ++---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 +++++-----
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 ++++----
drivers/gpu/drm/i915/gt/selftest_lrc.c | 16 ++++-----
.../drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 12 +++----
.../gpu/drm/i915/gt/selftest_workarounds.c | 8 ++---
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +--
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 21 ++++++------
drivers/gpu/drm/i915/i915_vma.h | 23 +++++++++++--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 ++++++-
drivers/gpu/drm/i915/selftests/i915_request.c | 20 +++++------
drivers/gpu/drm/i915/selftests/igt_spinner.c | 8 ++---
34 files changed, 169 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c
index 963ca7155b06..1bb99ef4ce2d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -64,7 +64,7 @@ static void dpt_insert_entries(struct i915_address_space *vm,
* not to allow the user to override access to a read only page.
*/
- i = vma->node.start / I915_GTT_PAGE_SIZE;
+ i = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, sgt_iter, vma->pages)
gen8_set_pte(&base[i++], pte_encode | addr);
}
@@ -104,7 +104,7 @@ static void dpt_bind_vma(struct i915_address_space *vm,
static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
{
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_vma_offset(vma), vma->size);
}
static void dpt_cleanup(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..0583dcd538ae 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -261,8 +261,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
- info->fix.smem_len = vma->node.size;
+ (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
+ info->fix.smem_len = vma->size;
}
vaddr = i915_vma_pin_iomap(vma);
@@ -273,7 +273,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out_unpin;
}
info->screen_base = vaddr;
- info->screen_size = vma->node.size;
+ info->screen_size = vma->size;
drm_fb_helper_fill_info(info, &ifbdev->helper, sizes);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 6a0ed537c199..d024b88da608 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -376,22 +376,24 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
const struct i915_vma *vma,
unsigned int flags)
{
- if (vma->node.size < entry->pad_to_size)
+ const u64 start = i915_vma_offset(vma);
+ const u64 size = i915_vma_size(vma);
+
+ if (size < entry->pad_to_size)
return true;
- if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
+ if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
return true;
- if (flags & EXEC_OBJECT_PINNED &&
- vma->node.start != entry->offset)
+ if (flags & EXEC_OBJECT_PINNED && start != entry->offset)
return true;
if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
- vma->node.start < BATCH_OFFSET_BIAS)
+ start < BATCH_OFFSET_BIAS)
return true;
if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
- (vma->node.start + vma->node.size + 4095) >> 32)
+ (start + size + 4095) >> 32)
return true;
if (flags & __EXEC_OBJECT_NEEDS_MAP &&
@@ -437,7 +439,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
int err;
if (vma->node.size)
- pin_flags = vma->node.start;
+ pin_flags = __i915_vma_offset(vma);
else
pin_flags = entry->offset & PIN_OFFSET_MASK;
@@ -677,8 +679,8 @@ static int eb_reserve_vma(struct i915_execbuffer *eb,
if (err)
return err;
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
@@ -990,8 +992,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
return err;
if (!err) {
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
} else {
@@ -1073,7 +1075,7 @@ static inline u64
relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
const struct i915_vma *target)
{
- return gen8_canonical_addr((int)reloc->delta + target->node.start);
+ return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target));
}
static void reloc_cache_init(struct reloc_cache *cache,
@@ -1229,7 +1231,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
if (err) /* no inactive aperture space, use cpu reloc */
return NULL;
} else {
- cache->node.start = vma->node.start;
+ cache->node.start = i915_ggtt_offset(vma);
cache->node.mm = (void *)vma;
}
}
@@ -1387,7 +1389,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
* more work needs to be done.
*/
if (!DBG_FORCE_RELOC &&
- gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
+ gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset)
return 0;
/* Check that the relocation address is valid... */
@@ -2331,7 +2333,7 @@ static int eb_request_submit(struct i915_execbuffer *eb,
}
err = rq->context->engine->emit_bb_start(rq,
- batch->node.start +
+ i915_vma_offset(batch) +
eb->batch_start_offset,
batch_len,
eb->batch_flags);
@@ -2342,7 +2344,7 @@ static int eb_request_submit(struct i915_execbuffer *eb,
GEM_BUG_ON(intel_context_is_parallel(rq->context));
GEM_BUG_ON(eb->batch_start_offset);
err = rq->context->engine->emit_bb_start(rq,
- eb->trampoline->node.start +
+ i915_vma_offset(eb->trampoline) +
batch_len, 0, 0);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 65fc6ff5f59d..5d3fa137389e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -378,7 +378,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
- (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
+ (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
min_t(u64, vma->size, area->vm_end - area->vm_start),
&ggtt->iomap);
if (ret)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 157a9765f483..7738e97d43b0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -406,7 +406,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
mutex_lock(&i915->ggtt.vm.mutex);
list_for_each_entry_safe(vma, next,
&i915->ggtt.vm.bound_list, vm_link) {
- unsigned long count = vma->node.size >> PAGE_SHIFT;
+ unsigned long count = i915_vma_size(vma) >> PAGE_SHIFT;
if (!vma->iomap || i915_vma_is_active(vma))
continue;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index ef4d0f7dc118..1e49c7c69d80 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -166,11 +166,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma,
return true;
size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return false;
alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
- if (!IS_ALIGNED(vma->node.start, alignment))
+ if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment))
return false;
return true;
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index c69c7d45aabc..c9361ffeb5d4 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -401,7 +401,7 @@ static int igt_check_page_sizes(struct i915_vma *vma)
* Maintaining alignment is required to utilise huge pages in the ppGGT.
*/
if (i915_gem_object_is_lmem(obj) &&
- IS_ALIGNED(vma->node.start, SZ_2M) &&
+ IS_ALIGNED(i915_vma_offset(vma), SZ_2M) &&
vma->page_sizes.sg & SZ_2M &&
vma->page_sizes.gtt < SZ_2M) {
pr_err("gtt pages mismatch for LMEM, expected 2M GTT pages, sg(%u), gtt(%u)\n",
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 8402ed925a69..d383b9f53a77 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -94,14 +94,14 @@ static int prepare_blit(const struct tiled_blits *t,
*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
*cs++ = 0;
*cs++ = t->height << 16 | t->width;
- *cs++ = lower_32_bits(dst->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(dst->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(dst->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(dst->vma));
*cs++ = 0;
*cs++ = src_pitch;
- *cs++ = lower_32_bits(src->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(src->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(src->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(src->vma));
*cs++ = MI_BATCH_BUFFER_END;
@@ -317,7 +317,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
{
int err;
- if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) {
+ if (drm_mm_node_allocated(&vma->node) && i915_vma_offset(vma) != addr) {
err = i915_vma_unbind(vma);
if (err)
return err;
@@ -327,6 +327,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
if (err)
return err;
+ GEM_BUG_ON(i915_vma_offset(vma) != addr);
return 0;
}
@@ -373,8 +374,8 @@ tiled_blit(struct tiled_blits *t,
err = move_to_active(dst->vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- t->batch->node.start,
- t->batch->node.size,
+ i915_vma_offset(t->batch),
+ i915_vma_size(t->batch),
0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index b32f7fed2d9c..fe01a7d92362 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -895,8 +895,8 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
*cmd = MI_BATCH_BUFFER_END;
__i915_gem_object_flush_map(rpcs, 0, 64);
@@ -984,7 +984,8 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
}
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
if (err)
goto skip_request;
@@ -1553,7 +1554,10 @@ static int write_to_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
+ 0);
if (err)
goto skip_request;
@@ -1660,7 +1664,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
*cmd++ = reg;
- *cmd++ = vma->node.start + result;
+ *cmd++ = i915_vma_offset(vma) + result;
*cmd = MI_BATCH_BUFFER_END;
i915_gem_object_flush_map(obj);
@@ -1691,7 +1695,10 @@ static int read_from_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, flags);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
+ flags);
if (err)
goto skip_request;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 6d30cdfa80f3..762881791e25 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -1196,7 +1196,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
if (err == 0)
err = i915_vma_move_to_active(vma, rq, 0);
- err = engine->emit_bb_start(rq, vma->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
index b35c1219c852..4390d69bd746 100644
--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
+++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
@@ -61,8 +61,8 @@ igt_emit_store_dw(struct i915_vma *vma,
goto err;
}
- GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size);
- offset += vma->node.start;
+ GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > i915_vma_size(vma));
+ offset += i915_vma_offset(vma);
for (n = 0; n < count; n++) {
if (ver >= 8) {
@@ -150,7 +150,7 @@ int igt_gpu_fill_dw(struct intel_context *ce,
flags |= I915_DISPATCH_SECURE;
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch), i915_vma_size(batch),
flags);
skip_request:
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 4a166d25fe60..72a8725e6f8a 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -110,7 +110,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
{
struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_directory * const pd = ppgtt->pd;
- unsigned int first_entry = vma->node.start / I915_GTT_PAGE_SIZE;
+ unsigned int first_entry = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
unsigned int act_pt = first_entry / GEN6_PTES;
unsigned int act_pte = first_entry % GEN6_PTES;
const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index 21f08e53889c..a14f962aaa85 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -105,7 +105,7 @@ static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)
static u32 batch_addr(const struct batch_chunk *bc)
{
- return bc->vma->node.start;
+ return i915_vma_offset(bc->vma);
}
static void batch_add(struct batch_chunk *bc, const u32 d)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9966e9dc5218..dd2ab23a123c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -460,7 +460,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
{
const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
- u64 start = vma->node.start;
+ u64 start = i915_vma_offset(vma);
GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm));
@@ -542,8 +542,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
if (maybe_64K != -1 &&
(index == I915_PDES ||
(i915_vm_has_scratch_64K(vma->vm) &&
- !iter->sg && IS_ALIGNED(vma->node.start +
- vma->node.size,
+ !iter->sg && IS_ALIGNED(i915_vma_offset(vma) +
+ i915_vma_size(vma),
I915_GTT_PAGE_SIZE_2M)))) {
vaddr = px_vaddr(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
@@ -587,7 +587,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
gen8_ppgtt_insert_huge(vma, &iter, cache_level, flags);
} else {
- u64 idx = vma->node.start >> GEN8_PTE_SHIFT;
+ u64 idx = i915_vma_offset(vma) >> GEN8_PTE_SHIFT;
do {
struct i915_page_directory * const pdp =
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 110d3944f9a2..07133f0c529e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -458,7 +458,8 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
unsigned int flags = (cache_level == I915_CACHE_NONE) ?
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
- intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
+ intel_gtt_insert_sg_entries(vma->pages,
+ i915_ggtt_offset(vma) >> PAGE_SHIFT,
flags);
}
@@ -649,7 +650,7 @@ static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
struct i915_vma *vma)
{
if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_ggtt_offset(vma), vma->size);
if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND))
ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f8948de72036..b6fea674e6a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -215,7 +215,8 @@ static int fence_update(struct i915_fence_reg *fence,
return ret;
}
- fence->start = vma->node.start;
+ GEM_BUG_ON(vma->fence_size > i915_vma_size(vma));
+ fence->start = i915_ggtt_offset(vma);
fence->size = vma->fence_size;
fence->stride = i915_gem_object_get_stride(vma->obj);
fence->tiling = i915_gem_object_get_tiling(vma->obj);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 4396bfd630d8..4773c95db012 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -186,7 +186,8 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
u32 pte_flags;
if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) {
- vm->allocate_va_range(vm, stash, vma->node.start, vma->size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
+ vm->allocate_va_range(vm, stash, i915_vma_offset(vma), vma->size);
set_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma));
}
@@ -204,7 +205,7 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
{
if (test_and_clear_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma)))
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_vma_offset(vma), vma->size);
}
static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index b575cd6e0b7a..2630fe6c8142 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -61,7 +61,7 @@ static int render_state_setup(struct intel_renderstate *so,
u32 s = rodata->batch[i];
if (i * 4 == rodata->reloc[reloc_index]) {
- u64 r = s + so->vma->node.start;
+ u64 r = s + i915_vma_offset(so->vma);
s = lower_32_bits(r);
if (HAS_64BIT_RELOC(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3e6fac0340ef..2c4c5c095c56 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -886,7 +886,7 @@ static int clear_residuals(struct i915_request *rq)
}
ret = engine->emit_bb_start(rq,
- engine->wa_ctx.vma->node.start, 0,
+ i915_vma_offset(engine->wa_ctx.vma), 0,
0);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 64abf5feabfa..9e28873a7e45 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -165,7 +165,7 @@ static int perf_mi_bb_start(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- batch->node.start, 8,
+ i915_vma_offset(batch), 8,
0);
if (err)
goto out;
@@ -305,7 +305,7 @@ static int perf_mi_noop(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- base->node.start, 8,
+ i915_vma_offset(base), 8,
0);
if (err)
goto out;
@@ -315,8 +315,8 @@ static int perf_mi_noop(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- nop->node.start,
- nop->node.size,
+ i915_vma_offset(nop),
+ i915_vma_size(nop),
0);
if (err)
goto out;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index b367ecfa42de..b803123df073 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2732,11 +2732,11 @@ static int create_gang(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_EQ_SDD;
*cs++ = 0;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(vma));
+ *cs++ = upper_32_bits(i915_vma_offset(vma));
if (*prev) {
- u64 offset = (*prev)->batch->node.start;
+ u64 offset = i915_vma_offset((*prev)->batch);
/* Terminate the spinner in the next lower priority batch. */
*cs++ = MI_STORE_DWORD_IMM_GEN4;
@@ -2764,7 +2764,7 @@ static int create_gang(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
i915_request_add(rq);
@@ -3092,7 +3092,7 @@ create_gpr_user(struct intel_engine_cs *engine,
*cs++ = MI_MATH_ADD;
*cs++ = MI_MATH_STORE(MI_MATH_REG(i), MI_MATH_REG_ACCU);
- addr = result->node.start + offset + i * sizeof(*cs);
+ addr = i915_vma_offset(result) + offset + i * sizeof(*cs);
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = CS_GPR(engine, 2 * i);
*cs++ = lower_32_bits(addr);
@@ -3102,8 +3102,8 @@ create_gpr_user(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_GTE_SDD;
*cs++ = i;
- *cs++ = lower_32_bits(result->node.start);
- *cs++ = upper_32_bits(result->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(result));
+ *cs++ = upper_32_bits(i915_vma_offset(result));
}
*cs++ = MI_BATCH_BUFFER_END;
@@ -3187,7 +3187,7 @@ create_gpr_client(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(batch, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- batch->node.start,
+ i915_vma_offset(batch),
PAGE_SIZE, 0);
i915_vma_unlock(batch);
i915_vma_unpin(batch);
@@ -3519,7 +3519,7 @@ static int smoke_submit(struct preempt_smoke *smoke,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index e5ad4d5a91c0..b0236c4d615c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -94,7 +94,8 @@ static int hang_init(struct hang *h, struct intel_gt *gt)
static u64 hws_address(const struct i915_vma *hws,
const struct i915_request *rq)
{
- return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
+ return i915_vma_offset(hws) +
+ offset_in_page(sizeof(u32) * rq->fence.context);
}
static int move_to_active(struct i915_vma *vma,
@@ -194,8 +195,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
} else if (GRAPHICS_VER(gt->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
@@ -208,7 +209,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else if (GRAPHICS_VER(gt->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
@@ -221,7 +222,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else {
*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -233,7 +234,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
}
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
intel_gt_chipset_flush(engine->gt);
@@ -248,7 +249,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
if (GRAPHICS_VER(gt->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = rq->engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
cancel_rq:
if (err) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index b0977a3b699b..ca2f2dec7089 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -955,8 +955,8 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
while (len--) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = hw[dw];
- *cs++ = lower_32_bits(scratch->node.start + x);
- *cs++ = upper_32_bits(scratch->node.start + x);
+ *cs++ = lower_32_bits(i915_vma_offset(scratch) + x);
+ *cs++ = upper_32_bits(i915_vma_offset(scratch) + x);
dw += 2;
x += 4;
@@ -1038,8 +1038,8 @@ record_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(b_before->node.start);
- *cs++ = upper_32_bits(b_before->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(b_before));
+ *cs++ = upper_32_bits(i915_vma_offset(b_before));
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
*cs++ = MI_SEMAPHORE_WAIT |
@@ -1054,8 +1054,8 @@ record_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(b_after->node.start);
- *cs++ = upper_32_bits(b_after->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(b_after));
+ *cs++ = upper_32_bits(i915_vma_offset(b_after));
intel_ring_advance(rq, cs);
@@ -1163,8 +1163,8 @@ static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(batch->node.start);
- *cs++ = upper_32_bits(batch->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(batch));
+ *cs++ = upper_32_bits(i915_vma_offset(batch));
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
index 041954408d0f..8d29f6b979bd 100644
--- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
@@ -50,7 +50,7 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
} else {
*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
}
- *cs++ = vma->node.start + 4000;
+ *cs++ = i915_vma_offset(vma) + 4000;
*cs++ = STACK_MAGIC;
*cs++ = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 7ee2513e15f9..d242ed23e609 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -119,14 +119,14 @@ create_spin_counter(struct intel_engine_cs *engine,
if (srm) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));
- *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
}
}
*cs++ = MI_BATCH_BUFFER_START_GEN8;
- *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
GEM_BUG_ON(cs - base > end);
i915_gem_object_flush_map(obj);
@@ -655,7 +655,7 @@ int live_rps_frequency_cs(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
@@ -796,7 +796,7 @@ int live_rps_frequency_srm(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 962e91ba3be4..cd027e98e409 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -521,8 +521,8 @@ static int check_dirty_whitelist(struct intel_context *ce)
for (i = 0; i < engine->whitelist.count; i++) {
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
+ u64 addr = i915_vma_offset(scratch);
struct i915_gem_ww_ctx ww;
- u64 addr = scratch->node.start;
struct i915_request *rq;
u32 srm, lrm, rsvd;
u32 expect;
@@ -645,7 +645,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
goto err_request;
err = engine->emit_bb_start(rq,
- batch->node.start, PAGE_SIZE,
+ i915_vma_offset(batch), PAGE_SIZE,
0);
if (err)
goto err_request;
@@ -877,7 +877,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
}
for (i = 0; i < engine->whitelist.count; i++) {
- u64 offset = results->node.start + sizeof(u32) * i;
+ u64 offset = i915_vma_offset(results) + sizeof(u32) * i;
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
/* Clear non priv flags */
@@ -951,7 +951,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce)
goto err_request;
/* Perform the writes from an unprivileged "user" batch */
- err = engine->emit_bb_start(rq, batch->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0);
err_request:
err = request_add_sync(rq, err);
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index e0403ce9ce69..c2109006df8b 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1459,8 +1459,8 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
/* Defer failure until attempted use */
jump_whitelist = alloc_whitelist(batch_length);
- shadow_addr = gen8_canonical_addr(shadow->node.start);
- batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);
+ shadow_addr = gen8_canonical_addr(i915_vma_offset(shadow));
+ batch_addr = gen8_canonical_addr(i915_vma_offset(batch) + batch_offset);
/*
* We use the batch length as size because the shadow object is as
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 390d541f64ea..b082af695d4e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -170,7 +170,7 @@ i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
stringify_vma_type(vma),
- vma->node.start, vma->node.size,
+ i915_vma_offset(vma), i915_vma_size(vma),
stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
switch (vma->ggtt_view.type) {
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2f01b8c0284c..d6c7d90ce5cc 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2015,7 +2015,7 @@ emit_oa_config(struct i915_perf_stream *stream,
goto err_add_request;
err = rq->engine->emit_bb_start(rq,
- vma->node.start, 0,
+ i915_vma_offset(vma), 0,
I915_DISPATCH_SECURE);
if (err)
goto err_add_request;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 927f0d4f8e11..10473ce8a047 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -399,7 +399,7 @@ int i915_vma_bind(struct i915_vma *vma,
u32 vma_flags;
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(vma->size > vma->node.size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start,
vma->node.size,
@@ -494,8 +494,8 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
vma->obj->base.size);
else
ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
- vma->node.start,
- vma->node.size);
+ i915_vma_offset(vma),
+ i915_vma_size(vma));
if (ptr == NULL) {
err = -ENOMEM;
goto err;
@@ -569,22 +569,22 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
if (test_bit(I915_VMA_ERROR_BIT, __i915_vma_flags(vma)))
return true;
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return true;
GEM_BUG_ON(alignment && !is_power_of_2(alignment));
- if (alignment && !IS_ALIGNED(vma->node.start, alignment))
+ if (alignment && !IS_ALIGNED(i915_vma_offset(vma), alignment))
return true;
if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma))
return true;
if (flags & PIN_OFFSET_BIAS &&
- vma->node.start < (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) < (flags & PIN_OFFSET_MASK))
return true;
if (flags & PIN_OFFSET_FIXED &&
- vma->node.start != (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
return true;
return false;
@@ -597,10 +597,11 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- fenceable = (vma->node.size >= vma->fence_size &&
- IS_ALIGNED(vma->node.start, vma->fence_alignment));
+ fenceable = (i915_vma_size(vma) >= vma->fence_size &&
+ IS_ALIGNED(i915_vma_offset(vma), vma->fence_alignment));
- mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end;
+ mappable = i915_ggtt_offset(vma) + vma->fence_size <=
+ i915_vm_to_ggtt(vma->vm)->mappable_end;
if (mappable && fenceable)
set_bit(I915_VMA_CAN_FENCE_BIT, __i915_vma_flags(vma));
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 4033aa08d5e4..1d13d619ff86 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -125,13 +125,30 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
return !list_empty(&vma->closed_link);
}
+static inline u64 i915_vma_size(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return vma->node.size;
+}
+
+static inline u64 __i915_vma_offset(const struct i915_vma *vma)
+{
+ return vma->node.start;
+}
+
+static inline u64 i915_vma_offset(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return __i915_vma_offset(vma);
+}
+
static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
{
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(upper_32_bits(vma->node.start));
- GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1));
- return lower_32_bits(vma->node.start);
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma)));
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) + i915_vma_size(vma) - 1));
+ return lower_32_bits(i915_vma_offset(vma));
}
static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 46f4236039a9..89528c0d19f4 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -245,6 +245,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
if (!mock_vma)
return -ENOMEM;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &mock_vma->node.flags);
+ if (i915_is_ggtt(vm))
+ __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(mock_vma));
+
/* Keep creating larger objects until one cannot fit into the hole */
for (size = 12; (hole_end - hole_start) >> size; size++) {
I915_RND_SUBSTATE(prng, seed_prng);
@@ -1982,6 +1986,7 @@ static int igt_cs_tlb(void *arg)
goto end;
/* Prime the TLB with the dummy pages */
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
for (i = 0; i < count; i++) {
vma->node.start = offset + i * PAGE_SIZE;
vm->insert_entries(vm, vma, I915_CACHE_NONE, 0);
@@ -1995,8 +2000,10 @@ static int igt_cs_tlb(void *arg)
}
vma->ops->clear_pages(vma);
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
+ &vma->node.flags);
- err = context_sync(ce);
+ err = context_sync(ce);
if (err) {
pr_err("%s: dummy setup timed out\n",
ce->engine->name);
@@ -2014,6 +2021,7 @@ static int igt_cs_tlb(void *arg)
goto end;
/* Replace the TLB with target batches */
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
for (i = 0; i < count; i++) {
struct i915_request *rq;
u32 *cs = batch + i * 64 / sizeof(*cs);
@@ -2048,6 +2056,8 @@ static int igt_cs_tlb(void *arg)
end_spin(batch, count - 1);
vma->ops->clear_pages(vma);
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
+ &vma->node.flags);
err = context_sync(ce);
if (err) {
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index 9979ef9197cd..737d29bbc3b5 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -879,8 +879,8 @@ empty_request(struct intel_engine_cs *engine,
return request;
err = engine->emit_bb_start(request,
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
I915_DISPATCH_SECURE);
if (err)
goto out_request;
@@ -1000,14 +1000,14 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
if (ver >= 8) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
} else if (ver >= 6) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
} else {
*cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
}
*cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
@@ -1091,8 +1091,8 @@ static int live_all_engines(void *arg)
GEM_BUG_ON(err);
err = engine->emit_bb_start(request[idx],
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
GEM_BUG_ON(err);
request[idx]->batch = batch;
@@ -1221,8 +1221,8 @@ static int live_sequential_engines(void *arg)
GEM_BUG_ON(err);
err = engine->emit_bb_start(request[idx],
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
GEM_BUG_ON(err);
request[idx]->batch = batch;
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 24d87d0fc747..d5939f1f14e4 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -115,7 +115,7 @@ static unsigned int seqno_offset(u64 fence)
static u64 hws_address(const struct i915_vma *hws,
const struct i915_request *rq)
{
- return hws->node.start + seqno_offset(rq->fence.context);
+ return i915_vma_offset(hws) + seqno_offset(rq->fence.context);
}
static int move_to_active(struct i915_vma *vma,
@@ -202,8 +202,8 @@ igt_spinner_create_request(struct igt_spinner *spin,
*batch++ = MI_BATCH_BUFFER_START;
else
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
@@ -218,7 +218,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
flags = 0;
if (GRAPHICS_VER(rq->engine->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
cancel_rq:
if (err) {
--
2.31.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size
2021-02-12 10:22 Chris Wilson
@ 2021-02-12 12:55 ` Matthew Auld
0 siblings, 0 replies; 25+ messages in thread
From: Matthew Auld @ 2021-02-12 12:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development
On Fri, 12 Feb 2021 at 10:22, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> We already wrap i915_vma.node.start for use with the GGTT, as there we
> can perform additional sanity checks that the node belongs to the GGTT
> and fits within the 32b registers. In the next couple of patches, we
> will introduce guard pages around the objects _inside_ the drm_mm_node
> allocation. That is we will offset the vma->pages so that the first page
> is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
> All users must then not use i915_vma.node.start directly, but compute
> the guard offset, thus all users are converted to use a
> i915_vma_offset() wrapper.
>
> The notable exceptions are the selftests that are testing exact
> behaviour of i915_vma_pin/i915_vma_insert.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
<snip>
> @@ -562,10 +562,11 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
> GEM_BUG_ON(!i915_vma_is_ggtt(vma));
> GEM_BUG_ON(!vma->fence_size);
>
> - fenceable = (vma->node.size >= vma->fence_size &&
> - IS_ALIGNED(vma->node.start, vma->fence_alignment));
> + fenceable = (i915_vma_size(vma) >= vma->fence_size &&
> + IS_ALIGNED(i915_vma_offset(vma), vma->fence_alignment));
>
> - mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end;
> + mappable = (i915_vma_offset(vma) + vma->fence_size <=
> + i915_vm_to_ggtt(vma->vm)->mappable_end);
i915_ggtt_offset(vma) could be used here.
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size
@ 2021-02-12 10:22 Chris Wilson
2021-02-12 12:55 ` Matthew Auld
0 siblings, 1 reply; 25+ messages in thread
From: Chris Wilson @ 2021-02-12 10:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_node
allocation. That is we will offset the vma->pages so that the first page
is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
All users must then not use i915_vma.node.start directly, but compute
the guard offset, thus all users are converted to use a
i915_vma_offset() wrapper.
The notable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 6 ++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 29 ++++++++++---------
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_blt.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +--
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 11 +++----
.../drm/i915/gem/selftests/i915_gem_context.c | 16 ++++++----
.../drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
.../drm/i915/gem/selftests/igt_gem_utils.c | 4 +--
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 8 ++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 ++--
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 7 +++--
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 ++---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 +++++----
.../drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 12 ++++----
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +--
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 21 +++++++-------
drivers/gpu/drm/i915/i915_vma.h | 18 ++++++++++--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 ++++++--
drivers/gpu/drm/i915/selftests/i915_request.c | 8 ++---
.../gpu/drm/i915/selftests/i915_scheduler.c | 4 +--
drivers/gpu/drm/i915/selftests/igt_spinner.c | 9 ++++--
32 files changed, 134 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 07db8e83f98e..2a72fb3c8416 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -237,8 +237,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
- info->fix.smem_len = vma->node.size;
+ (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
+ info->fix.smem_len = vma->size;
vaddr = i915_vma_pin_iomap(vma);
if (IS_ERR(vaddr)) {
@@ -248,7 +248,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out_unpin;
}
info->screen_base = vaddr;
- info->screen_size = vma->node.size;
+ info->screen_size = vma->size;
drm_fb_helper_fill_info(info, &ifbdev->helper, sizes);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index fe170186dd42..f75f6751cf3f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -368,22 +368,23 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
const struct i915_vma *vma,
unsigned int flags)
{
- if (vma->node.size < entry->pad_to_size)
+ const u64 start = i915_vma_offset(vma);
+ const u64 size = i915_vma_size(vma);
+
+ if (size < entry->pad_to_size)
return true;
- if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
+ if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
return true;
- if (flags & EXEC_OBJECT_PINNED &&
- vma->node.start != entry->offset)
+ if (flags & EXEC_OBJECT_PINNED && start != entry->offset)
return true;
- if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
- vma->node.start < BATCH_OFFSET_BIAS)
+ if (flags & __EXEC_OBJECT_NEEDS_BIAS && start < BATCH_OFFSET_BIAS)
return true;
if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
- (vma->node.start + vma->node.size + 4095) >> 32)
+ (start + size + 4095) >> 32)
return true;
if (flags & __EXEC_OBJECT_NEEDS_MAP &&
@@ -607,8 +608,8 @@ static int eb_reserve_vma(struct i915_execbuffer *eb,
if (err)
return err;
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
@@ -899,8 +900,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
return err;
if (eb_pin_vma(eb, entry, ev)) {
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
} else {
@@ -1173,7 +1174,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
if (err) /* no inactive aperture space, use cpu reloc */
return NULL;
} else {
- cache->node.start = vma->node.start;
+ cache->node.start = i915_ggtt_offset(vma);
cache->node.mm = (void *)vma;
}
}
@@ -1458,7 +1459,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb,
else if (IS_ERR(batch))
return false;
- addr = gen8_canonical_addr(vma->node.start + offset);
+ addr = gen8_canonical_addr(i915_vma_offset(vma) + offset);
if (gen >= 8) {
if (offset & 7) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
@@ -1622,7 +1623,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
* more work needs to be done.
*/
if (!DBG_FORCE_RELOC &&
- gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
+ gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset)
return 0;
/* Check that the relocation address is valid... */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index ec28a6cde49b..02cb84285dbb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -365,7 +365,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
- (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
+ (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
min_t(u64, vma->size, area->vm_end - area->vm_start),
&ggtt->iomap);
if (ret)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index d6dac21fce0b..c6222a99d89b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -62,7 +62,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
}
rem = vma->size;
- offset = vma->node.start;
+ offset = i915_vma_offset(vma);
do {
u32 size = min_t(u64, rem, block_size);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index b64a0788381f..7a1a90cd8bcd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -376,7 +376,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
mutex_lock(&i915->ggtt.vm.mutex);
list_for_each_entry_safe(vma, next,
&i915->ggtt.vm.bound_list, vm_link) {
- unsigned long count = vma->node.size >> PAGE_SHIFT;
+ unsigned long count = i915_vma_size(vma) >> PAGE_SHIFT;
if (!vma->iomap || i915_vma_is_active(vma))
continue;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index d589d3d81085..b92bcb04f563 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -166,11 +166,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma,
return true;
size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return false;
alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
- if (!IS_ALIGNED(vma->node.start, alignment))
+ if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment))
return false;
return true;
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 10ee24b252dd..4b50af149cfc 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -377,7 +377,7 @@ static int igt_check_page_sizes(struct i915_vma *vma)
* Maintaining alignment is required to utilise huge pages in the ppGGT.
*/
if (i915_gem_object_is_lmem(obj) &&
- IS_ALIGNED(vma->node.start, SZ_2M) &&
+ IS_ALIGNED(i915_vma_offset(vma), SZ_2M) &&
vma->page_sizes.sg & SZ_2M &&
vma->page_sizes.gtt < SZ_2M) {
pr_err("gtt pages mismatch for LMEM, expected 2M GTT pages, sg(%u), gtt(%u)\n",
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 175581724d44..586b57b8d957 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -212,14 +212,14 @@ static int prepare_blit(const struct tiled_blits *t,
*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
*cs++ = 0;
*cs++ = t->height << 16 | t->width;
- *cs++ = lower_32_bits(dst->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(dst->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(dst->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(dst->vma));
*cs++ = 0;
*cs++ = src_pitch;
- *cs++ = lower_32_bits(src->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(src->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(src->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(src->vma));
*cs++ = MI_BATCH_BUFFER_END;
@@ -435,7 +435,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
{
int err;
- if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) {
+ if (drm_mm_node_allocated(&vma->node) && i915_vma_offset(vma) != addr) {
err = i915_vma_unbind(vma);
if (err)
return err;
@@ -445,6 +445,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
if (err)
return err;
+ GEM_BUG_ON(i915_vma_offset(vma) != addr);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index df949320f2b5..39fc548d927a 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -905,8 +905,8 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
*cmd = MI_BATCH_BUFFER_END;
__i915_gem_object_flush_map(rpcs, 0, 64);
@@ -1561,7 +1561,10 @@ static int write_to_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
+ 0);
if (err)
goto skip_request;
@@ -1668,7 +1671,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
*cmd++ = reg;
- *cmd++ = vma->node.start + result;
+ *cmd++ = i915_vma_offset(vma) + result;
*cmd = MI_BATCH_BUFFER_END;
i915_gem_object_flush_map(obj);
@@ -1699,7 +1702,10 @@ static int read_from_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, flags);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
+ flags);
if (err)
goto skip_request;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 39293d98f34d..d37706807703 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -1145,7 +1145,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
if (err == 0)
err = i915_vma_move_to_active(vma, rq, 0);
- err = engine->emit_bb_start(rq, vma->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
index b7e064667d39..e967e0fb79c5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
+++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
@@ -62,8 +62,8 @@ igt_emit_store_dw(struct i915_vma *vma,
goto err;
}
- GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size);
- offset += vma->node.start;
+ GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > i915_vma_size(vma));
+ offset += i915_vma_offset(vma);
for (n = 0; n < count; n++) {
if (gen >= 8) {
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index e08dff376339..d16cfa75c03a 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -111,7 +111,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
{
struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_directory * const pd = ppgtt->pd;
- unsigned int first_entry = vma->node.start / I915_GTT_PAGE_SIZE;
+ unsigned int first_entry = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
unsigned int act_pt = first_entry / GEN6_PTES;
unsigned int act_pte = first_entry % GEN6_PTES;
const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index de575fdb033f..52e6f08d0ced 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -105,7 +105,7 @@ static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)
static u32 batch_addr(const struct batch_chunk *bc)
{
- return bc->vma->node.start;
+ return i915_vma_offset(bc->vma);
}
static void batch_add(struct batch_chunk *bc, const u32 d)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 176c19633412..9d88d81c30d2 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -419,7 +419,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
{
const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
- u64 start = vma->node.start;
+ u64 start = i915_vma_offset(vma);
GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm));
@@ -502,8 +502,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
if (maybe_64K != -1 &&
(index == I915_PDES ||
(i915_vm_has_scratch_64K(vma->vm) &&
- !iter->sg && IS_ALIGNED(vma->node.start +
- vma->node.size,
+ !iter->sg && IS_ALIGNED(i915_vma_offset(vma) +
+ i915_vma_size(vma),
I915_GTT_PAGE_SIZE_2M)))) {
vaddr = kmap_atomic_px(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
@@ -547,7 +547,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
gen8_ppgtt_insert_huge(vma, &iter, cache_level, flags);
} else {
- u64 idx = vma->node.start >> GEN8_PTE_SHIFT;
+ u64 idx = i915_vma_offset(vma) >> GEN8_PTE_SHIFT;
do {
struct i915_page_directory * const pdp =
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index b0b8ded834f0..c5803c434d33 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -440,7 +440,8 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
unsigned int flags = (cache_level == I915_CACHE_NONE) ?
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
- intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
+ intel_gtt_insert_sg_entries(vma->pages,
+ i915_ggtt_offset(vma) >> PAGE_SHIFT,
flags);
}
@@ -631,7 +632,7 @@ static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
struct i915_vma *vma)
{
if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_ggtt_offset(vma), vma->size);
if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND))
ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index e891552611d5..87160e3fed37 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -215,7 +215,8 @@ static int fence_update(struct i915_fence_reg *fence,
return ret;
}
- fence->start = vma->node.start;
+ GEM_BUG_ON(vma->fence_size > i915_vma_size(vma));
+ fence->start = i915_ggtt_offset(vma);
fence->size = vma->fence_size;
fence->stride = i915_gem_object_get_stride(vma->obj);
fence->tiling = i915_gem_object_get_tiling(vma->obj);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index a91955af50a6..0d11894aa848 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -186,7 +186,10 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
u32 pte_flags;
if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) {
- vm->allocate_va_range(vm, stash, vma->node.start, vma->size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
+ vm->allocate_va_range(vm, stash,
+ i915_vma_offset(vma),
+ vma->size);
set_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma));
}
@@ -204,7 +207,7 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
{
if (test_and_clear_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma)))
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_vma_offset(vma), vma->size);
}
static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index 0f7c0a148b80..214a154665b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -61,7 +61,7 @@ static int render_state_setup(struct intel_renderstate *so,
u32 s = rodata->batch[i];
if (i * 4 == rodata->reloc[reloc_index]) {
- u64 r = s + so->vma->node.start;
+ u64 r = s + i915_vma_offset(so->vma);
s = lower_32_bits(r);
if (HAS_64BIT_RELOC(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 282089d64789..2c75e3fa6350 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -824,7 +824,7 @@ static int clear_residuals(struct i915_request *rq)
}
ret = engine->emit_bb_start(rq,
- engine->wa_ctx.vma->node.start, 0,
+ i915_vma_offset(engine->wa_ctx.vma), 0,
0);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index f625c29023ea..5c8a6ccdf024 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2704,8 +2704,8 @@ static int create_gang(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_EQ_SDD;
*cs++ = 0;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(vma));
+ *cs++ = upper_32_bits(i915_vma_offset(vma));
if (*prev) {
u64 offset = (*prev)->batch->node.start;
@@ -2736,7 +2736,7 @@ static int create_gang(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
i915_request_add(rq);
@@ -3486,7 +3486,7 @@ static int smoke_submit(struct preempt_smoke *smoke,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index cdb0ceff3be1..8540011c39cc 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -192,8 +192,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
} else if (INTEL_GEN(gt->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
@@ -206,7 +206,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else if (INTEL_GEN(gt->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
@@ -219,7 +219,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else {
*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -231,7 +231,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
}
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
intel_gt_chipset_flush(engine->gt);
@@ -246,7 +246,9 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
if (INTEL_GEN(gt->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = rq->engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ PAGE_SIZE, flags);
cancel_rq:
if (err) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
index 6cd9f6bc240c..92d0dc0ab68b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
@@ -50,7 +50,7 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
} else {
*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
}
- *cs++ = vma->node.start + 4000;
+ *cs++ = i915_vma_offset(vma) + 4000;
*cs++ = STACK_MAGIC;
*cs++ = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 967641fee42a..1f58db52670c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -119,14 +119,14 @@ create_spin_counter(struct intel_engine_cs *engine,
if (srm) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));
- *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
}
}
*cs++ = MI_BATCH_BUFFER_START_GEN8;
- *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
GEM_BUG_ON(cs - base > end);
i915_gem_object_flush_map(obj);
@@ -655,7 +655,7 @@ int live_rps_frequency_cs(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
@@ -796,7 +796,7 @@ int live_rps_frequency_srm(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 51133b8fabb4..a65a99fa5331 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -158,7 +158,8 @@ i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
i915_vma_is_ggtt(vma) ? "g" : "pp",
- vma->node.start, vma->node.size,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
if (i915_vma_is_ggtt(vma)) {
switch (vma->ggtt_view.type) {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 291f5b818925..c7abe4ee61be 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1011,8 +1011,8 @@ i915_vma_coredump_create(const struct intel_gt *gt,
strcpy(dst->name, name);
dst->next = NULL;
- dst->gtt_offset = vma->node.start;
- dst->gtt_size = vma->node.size;
+ dst->gtt_offset = i915_vma_offset(vma);
+ dst->gtt_size = i915_vma_size(vma);
dst->gtt_page_sizes = vma->page_sizes.gtt;
dst->num_pages = num_pages;
dst->page_count = 0;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 93f3e2c5c89a..3e1421755aa6 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1985,7 +1985,7 @@ emit_oa_config(struct i915_perf_stream *stream,
goto err_add_request;
err = rq->engine->emit_bb_start(rq,
- vma->node.start, 0,
+ i915_vma_offset(vma), 0,
I915_DISPATCH_SECURE);
if (err)
goto err_add_request;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index caa9b041616b..17fe455bd770 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -382,7 +382,7 @@ int i915_vma_bind(struct i915_vma *vma,
u32 vma_flags;
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(vma->size > vma->node.size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start,
vma->node.size,
@@ -459,8 +459,8 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
ptr = READ_ONCE(vma->iomap);
if (ptr == NULL) {
ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
- vma->node.start,
- vma->node.size);
+ i915_vma_offset(vma),
+ i915_vma_size(vma));
if (ptr == NULL) {
err = -ENOMEM;
goto err;
@@ -534,22 +534,22 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
if (test_bit(I915_VMA_ERROR_BIT, __i915_vma_flags(vma)))
return true;
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return true;
GEM_BUG_ON(alignment && !is_power_of_2(alignment));
- if (alignment && !IS_ALIGNED(vma->node.start, alignment))
+ if (alignment && !IS_ALIGNED(i915_vma_offset(vma), alignment))
return true;
if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma))
return true;
if (flags & PIN_OFFSET_BIAS &&
- vma->node.start < (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) < (flags & PIN_OFFSET_MASK))
return true;
if (flags & PIN_OFFSET_FIXED &&
- vma->node.start != (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
return true;
return false;
@@ -562,10 +562,11 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- fenceable = (vma->node.size >= vma->fence_size &&
- IS_ALIGNED(vma->node.start, vma->fence_alignment));
+ fenceable = (i915_vma_size(vma) >= vma->fence_size &&
+ IS_ALIGNED(i915_vma_offset(vma), vma->fence_alignment));
- mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end;
+ mappable = (i915_vma_offset(vma) + vma->fence_size <=
+ i915_vm_to_ggtt(vma->vm)->mappable_end);
if (mappable && fenceable)
set_bit(I915_VMA_CAN_FENCE_BIT, __i915_vma_flags(vma));
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index a64adc8c883b..5049655a24c1 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -110,13 +110,25 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
return !list_empty(&vma->closed_link);
}
+static inline u64 i915_vma_size(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return vma->node.size;
+}
+
+static inline u64 i915_vma_offset(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return vma->node.start;
+}
+
static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
{
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(upper_32_bits(vma->node.start));
- GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1));
- return lower_32_bits(vma->node.start);
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma)));
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) + i915_vma_size(vma) - 1));
+ return lower_32_bits(i915_vma_offset(vma));
}
static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index c1adea8765a9..d33ef0cc02ea 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -231,6 +231,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
if (!mock_vma)
return -ENOMEM;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &mock_vma->node.flags);
+ if (i915_is_ggtt(vm))
+ __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(mock_vma));
+
/* Keep creating larger objects until one cannot fit into the hole */
for (size = 12; (hole_end - hole_start) >> size; size++) {
I915_RND_SUBSTATE(prng, seed_prng);
@@ -1941,6 +1945,7 @@ static int igt_cs_tlb(void *arg)
i915_vm_free_pt_stash(vm, &stash);
/* Prime the TLB with the dummy pages */
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
for (i = 0; i < count; i++) {
vma->node.start = offset + i * PAGE_SIZE;
vm->insert_entries(vm, vma, I915_CACHE_NONE, 0);
@@ -1952,8 +1957,9 @@ static int igt_cs_tlb(void *arg)
}
i915_request_put(rq);
}
-
vma->ops->clear_pages(vma);
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
+ &vma->node.flags);
err = context_sync(ce);
if (err) {
@@ -1973,6 +1979,7 @@ static int igt_cs_tlb(void *arg)
goto end;
/* Replace the TLB with target batches */
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
for (i = 0; i < count; i++) {
struct i915_request *rq;
u32 *cs = batch + i * 64 / sizeof(*cs);
@@ -2005,8 +2012,9 @@ static int igt_cs_tlb(void *arg)
i915_request_put(rq);
}
end_spin(batch, count - 1);
-
vma->ops->clear_pages(vma);
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
+ &vma->node.flags);
err = context_sync(ce);
if (err) {
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index 8035ea7565ed..70278be5711b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -789,14 +789,14 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
if (gen >= 8) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
} else if (gen >= 6) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
} else {
*cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
}
*cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
index f54bdbeaa48b..6ed27896391b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -568,8 +568,8 @@ __write_timestamp(struct intel_engine_cs *engine,
*cs++ = MI_STORE_REGISTER_MEM + use_64b;
*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base));
- *cs++ = lower_32_bits(vma->node.start) + sizeof(u32) * slot;
- *cs++ = upper_32_bits(vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(vma)) + sizeof(u32) * slot;
+ *cs++ = upper_32_bits(i915_vma_offset(vma));
intel_ring_advance(rq, cs);
i915_request_get(rq);
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 0e6c1ea0082a..28469743de1c 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -163,8 +163,8 @@ igt_spinner_create_request(struct igt_spinner *spin,
*batch++ = MI_BATCH_BUFFER_START;
else
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
@@ -179,7 +179,10 @@ igt_spinner_create_request(struct igt_spinner *spin,
flags = 0;
if (INTEL_GEN(rq->engine->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ PAGE_SIZE,
+ flags);
cancel_rq:
if (err) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
end of thread, other threads:[~2022-11-09 17:42 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-15 15:56 [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Chris Wilson
2021-02-15 15:56 ` [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma Chris Wilson
2021-02-15 18:04 ` Matthew Auld
2021-02-15 18:15 ` Chris Wilson
2021-02-15 19:31 ` Matthew Auld
2021-02-15 20:29 ` Chris Wilson
2021-02-15 20:33 ` [Intel-gfx] [PATCH] " Chris Wilson
2021-02-15 15:56 ` [Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround Chris Wilson
2021-02-15 18:07 ` Matthew Auld
2021-02-20 11:08 ` [Intel-gfx] [PATCH] " Chris Wilson
2021-02-20 11:10 ` Chris Wilson
2021-02-15 17:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size Patchwork
2021-02-15 19:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-02-15 21:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev2) Patchwork
2021-02-15 22:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-02-17 14:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev3) Patchwork
2021-02-17 16:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-02-20 13:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Wrap all access to i915_vma.node.start|size (rev5) Patchwork
2021-02-20 15:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-11-09 17:40 [PATCH 0/3] add guard padding around i915_vma Andi Shyti
2022-11-09 17:40 ` [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Andi Shyti
2022-11-09 16:49 [PATCH 0/3] add guard patting around i915_vma Andi Shyti
2022-11-09 16:49 ` [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Andi Shyti
2021-12-02 8:31 [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Tejas Upadhyay
2021-12-02 8:31 ` [Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Tejas Upadhyay
2021-12-03 9:02 ` Ramalingam C
2021-02-12 10:22 Chris Wilson
2021-02-12 12:55 ` Matthew Auld
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