* [PATCH v4 00/71] TCI fixes and cleanups
@ 2021-02-17 20:19 Richard Henderson
2021-02-17 20:19 ` [PATCH v4 01/71] tcg/tci: Use exec/cpu_ldst.h interfaces Richard Henderson
` (71 more replies)
0 siblings, 72 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Changes since v3:
* First patch fixes g2h() breakage. This shows a hole in our CI,
in that we only build softmmu with TCI, not linux-user.
* Tidy-up for the magic qemu_ld/st macros.
* Fix libffi return value case with ffi_arg.
Changes since v2:
* 20-something patches are now upstream.
* Increase testing timeout for tci.
* Gitlab testing for tci w/ 32-bit host.
r~
Richard Henderson (71):
tcg/tci: Use exec/cpu_ldst.h interfaces
tcg: Split out tcg_raise_tb_overflow
tcg: Manage splitwx in tc_ptr_to_region_tree by hand
tcg/tci: Merge identical cases in generation
tcg/tci: Remove tci_read_r8
tcg/tci: Remove tci_read_r8s
tcg/tci: Remove tci_read_r16
tcg/tci: Remove tci_read_r16s
tcg/tci: Remove tci_read_r32
tcg/tci: Remove tci_read_r32s
tcg/tci: Reduce use of tci_read_r64
tcg/tci: Merge basic arithmetic operations
tcg/tci: Merge extension operations
tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64
tcg/tci: Merge bswap operations
tcg/tci: Merge mov, not and neg operations
tcg/tci: Rename tci_read_r to tci_read_rval
tcg/tci: Split out tci_args_rrs
tcg/tci: Split out tci_args_rr
tcg/tci: Split out tci_args_rrr
tcg/tci: Split out tci_args_rrrc
tcg/tci: Split out tci_args_l
tcg/tci: Split out tci_args_rrrrrc
tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl
tcg/tci: Split out tci_args_ri and tci_args_rI
tcg/tci: Reuse tci_args_l for calls.
tcg/tci: Reuse tci_args_l for exit_tb
tcg/tci: Reuse tci_args_l for goto_tb
tcg/tci: Split out tci_args_rrrrrr
tcg/tci: Split out tci_args_rrrr
tcg/tci: Clean up deposit operations
tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits
tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm}
tcg/tci: Hoist op_size checking into tci_args_*
tcg/tci: Remove tci_disas
tcg/tci: Implement the disassembler properly
tcg: Build ffi data structures for helpers
tcg/tci: Use ffi for calls
tcg/tci: Improve tcg_target_call_clobber_regs
tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order
tcg/tci: Push opcode emit into each case
tcg/tci: Split out tcg_out_op_rrs
tcg/tci: Split out tcg_out_op_l
tcg/tci: Split out tcg_out_op_p
tcg/tci: Split out tcg_out_op_rr
tcg/tci: Split out tcg_out_op_rrr
tcg/tci: Split out tcg_out_op_rrrc
tcg/tci: Split out tcg_out_op_rrrrrc
tcg/tci: Split out tcg_out_op_rrrbb
tcg/tci: Split out tcg_out_op_rrcl
tcg/tci: Split out tcg_out_op_rrrrrr
tcg/tci: Split out tcg_out_op_rrrr
tcg/tci: Split out tcg_out_op_rrrrcl
tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm}
tcg/tci: Split out tcg_out_op_v
tcg/tci: Split out tcg_out_op_np
tcg/tci: Split out tcg_out_op_r[iI]
tcg/tci: Reserve r13 for a temporary
tcg/tci: Emit setcond before brcond
tcg/tci: Remove tci_write_reg
tcg/tci: Change encoding to uint32_t units
tcg/tci: Implement goto_ptr
tcg/tci: Implement movcond
tcg/tci: Implement andc, orc, eqv, nand, nor
tcg/tci: Implement extract, sextract
tcg/tci: Implement clz, ctz, ctpop
tcg/tci: Implement mulu2, muls2
tcg/tci: Implement add2, sub2
tcg/tci: Split out tci_qemu_ld, tci_qemu_st
tests/tcg: Increase timeout for TCI
gitlab: Enable cross-i386 builds of TCI
configure | 3 +
meson.build | 9 +-
include/exec/helper-ffi.h | 115 ++
include/exec/helper-tcg.h | 24 +-
include/tcg/tcg-opc.h | 6 +-
include/tcg/tcg.h | 1 +
target/hppa/helper.h | 2 +
target/i386/ops_sse_header.h | 6 +
target/m68k/helper.h | 1 +
target/ppc/helper.h | 3 +
tcg/tci/tcg-target-con-set.h | 2 +-
tcg/tci/tcg-target.h | 81 +-
disas/tci.c | 61 -
tcg/tcg.c | 117 +-
tcg/tci.c | 1759 +++++++++--------
tcg/tci/tcg-target.c.inc | 926 +++++----
.gitlab-ci.d/crossbuilds.yml | 17 +-
tcg/tci/README | 20 +-
.../dockerfiles/fedora-i386-cross.docker | 1 +
tests/docker/dockerfiles/fedora.docker | 1 +
tests/tcg/Makefile.target | 6 +-
21 files changed, 1789 insertions(+), 1372 deletions(-)
create mode 100644 include/exec/helper-ffi.h
delete mode 100644 disas/tci.c
--
2.25.1
^ permalink raw reply [flat|nested] 92+ messages in thread
* [PATCH v4 01/71] tcg/tci: Use exec/cpu_ldst.h interfaces
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-21 23:00 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 02/71] tcg: Split out tcg_raise_tb_overflow Richard Henderson
` (70 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Use the provided cpu_ldst.h interfaces. This fixes the build vs
the unconverted uses of g2h(), adds missed memory trace events,
and correctly recognizes when a SIGSEGV belongs to the guest via
set_helper_retaddr().
Fixes: 3e8f1628e864
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 73 +++++++++++++++++++++----------------------------------
1 file changed, 28 insertions(+), 45 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index fb3c97aaf1..1c667537fe 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -346,51 +346,34 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
return result;
}
-#ifdef CONFIG_SOFTMMU
-# define qemu_ld_ub \
- helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_leuw \
- helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_leul \
- helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_leq \
- helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_beuw \
- helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_beul \
- helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_beq \
- helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_st_b(X) \
- helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_lew(X) \
- helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_lel(X) \
- helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_leq(X) \
- helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_bew(X) \
- helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_bel(X) \
- helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_beq(X) \
- helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-#else
-# define qemu_ld_ub ldub_p(g2h(taddr))
-# define qemu_ld_leuw lduw_le_p(g2h(taddr))
-# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
-# define qemu_ld_leq ldq_le_p(g2h(taddr))
-# define qemu_ld_beuw lduw_be_p(g2h(taddr))
-# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
-# define qemu_ld_beq ldq_be_p(g2h(taddr))
-# define qemu_st_b(X) stb_p(g2h(taddr), X)
-# define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
-# define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
-# define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
-# define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
-# define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
-# define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
-#endif
+#define qemu_ld_ub \
+ cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_ld_leuw \
+ cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_ld_leul \
+ cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_ld_leq \
+ cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_ld_beuw \
+ cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_ld_beul \
+ cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_ld_beq \
+ cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_st_b(X) \
+ cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_st_lew(X) \
+ cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_st_lel(X) \
+ cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_st_leq(X) \
+ cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_st_bew(X) \
+ cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_st_bel(X) \
+ cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#define qemu_st_beq(X) \
+ cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
#if TCG_TARGET_REG_BITS == 64
# define CASE_32_64(x) \
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 02/71] tcg: Split out tcg_raise_tb_overflow
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
2021-02-17 20:19 ` [PATCH v4 01/71] tcg/tci: Use exec/cpu_ldst.h interfaces Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-18 22:22 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 03/71] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Richard Henderson
` (69 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Allow other places in tcg to restart with a smaller tb.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 63a12b197b..bbe3dcee03 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -346,6 +346,12 @@ static void set_jmp_reset_offset(TCGContext *s, int which)
s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
}
+/* Signal overflow, starting over with fewer guest insns. */
+static void QEMU_NORETURN tcg_raise_tb_overflow(TCGContext *s)
+{
+ siglongjmp(s->jmp_trans, -2);
+}
+
#define C_PFX1(P, A) P##A
#define C_PFX2(P, A, B) P##A##_##B
#define C_PFX3(P, A, B, C) P##A##_##B##_##C
@@ -1310,8 +1316,7 @@ static TCGTemp *tcg_temp_alloc(TCGContext *s)
int n = s->nb_temps++;
if (n >= TCG_MAX_TEMPS) {
- /* Signal overflow, starting over with fewer guest insns. */
- siglongjmp(s->jmp_trans, -2);
+ tcg_raise_tb_overflow(s);
}
return memset(&s->temps[n], 0, sizeof(TCGTemp));
}
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 03/71] tcg: Manage splitwx in tc_ptr_to_region_tree by hand
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
2021-02-17 20:19 ` [PATCH v4 01/71] tcg/tci: Use exec/cpu_ldst.h interfaces Richard Henderson
2021-02-17 20:19 ` [PATCH v4 02/71] tcg: Split out tcg_raise_tb_overflow Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 04/71] tcg/tci: Merge identical cases in generation Richard Henderson
` (68 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
The use in tcg_tb_lookup is given a random pc that comes from the pc
of a signal handler. Do not assert that the pointer is already within
the code gen buffer at all, much less the writable mirror of it.
Fixes: db0c51a3803
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
For TCI, this indicates a bug in handle_cpu_signal, in that we
are taking PC from the host signal frame. Which is, nearly,
unrelated to TCI at all.
The TCI "pc" is tci_tb_ptr (fixed in the next patch to at least
be thread-local). We update this only on calls, since we don't
expect SEGV during the interpretation loop. Which works ok for
softmmu, in which we pass down pc by hand to the helpers, but
is not ok for user-only, where we simply perform the raw memory
operation.
I don't know how to fix this, exactly. Probably by storing to
tci_tb_ptr before each qemu_ld/qemu_st operation, with barriers.
Then Doing the Right Thing in handle_cpu_signal. And perhaps
by clearing tci_tb_ptr whenever we're not expecting a SEGV on
behalf of the guest (and thus anything left is a qemu host bug).
---
v2: Retain full struct initialization
---
tcg/tcg.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index bbe3dcee03..2991112829 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -513,11 +513,21 @@ static void tcg_region_trees_init(void)
}
}
-static struct tcg_region_tree *tc_ptr_to_region_tree(const void *cp)
+static struct tcg_region_tree *tc_ptr_to_region_tree(const void *p)
{
- void *p = tcg_splitwx_to_rw(cp);
size_t region_idx;
+ /*
+ * Like tcg_splitwx_to_rw, with no assert. The pc may come from
+ * a signal handler over which the caller has no control.
+ */
+ if (!in_code_gen_buffer(p)) {
+ p -= tcg_splitwx_diff;
+ if (!in_code_gen_buffer(p)) {
+ return NULL;
+ }
+ }
+
if (p < region.start_aligned) {
region_idx = 0;
} else {
@@ -536,6 +546,7 @@ void tcg_tb_insert(TranslationBlock *tb)
{
struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr);
+ g_assert(rt != NULL);
qemu_mutex_lock(&rt->lock);
g_tree_insert(rt->tree, &tb->tc, tb);
qemu_mutex_unlock(&rt->lock);
@@ -545,6 +556,7 @@ void tcg_tb_remove(TranslationBlock *tb)
{
struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr);
+ g_assert(rt != NULL);
qemu_mutex_lock(&rt->lock);
g_tree_remove(rt->tree, &tb->tc);
qemu_mutex_unlock(&rt->lock);
@@ -561,6 +573,10 @@ TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr)
TranslationBlock *tb;
struct tb_tc s = { .ptr = (void *)tc_ptr };
+ if (rt == NULL) {
+ return NULL;
+ }
+
qemu_mutex_lock(&rt->lock);
tb = g_tree_lookup(rt->tree, &s);
qemu_mutex_unlock(&rt->lock);
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 04/71] tcg/tci: Merge identical cases in generation
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (2 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 03/71] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-18 23:24 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 05/71] tcg/tci: Remove tci_read_r8 Richard Henderson
` (67 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
cases that are identical between 32-bit and 64-bit hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 204 ++++++++++++++-------------------------
1 file changed, 73 insertions(+), 131 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index feac4659cc..c79f9c32d8 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -380,6 +380,18 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+#if TCG_TARGET_REG_BITS == 64
+# define CASE_32_64(x) \
+ case glue(glue(INDEX_op_, x), _i64): \
+ case glue(glue(INDEX_op_, x), _i32):
+# define CASE_64(x) \
+ case glue(glue(INDEX_op_, x), _i64):
+#else
+# define CASE_32_64(x) \
+ case glue(glue(INDEX_op_, x), _i32):
+# define CASE_64(x)
+#endif
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args)
{
@@ -391,6 +403,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_exit_tb:
tcg_out64(s, args[0]);
break;
+
case INDEX_op_goto_tb:
if (s->tb_jmp_insn_offset) {
/* Direct jump method. */
@@ -404,15 +417,18 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
}
set_jmp_reset_offset(s, args[0]);
break;
+
case INDEX_op_br:
tci_out_label(s, arg_label(args[0]));
break;
- case INDEX_op_setcond_i32:
+
+ CASE_32_64(setcond)
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out_r(s, args[2]);
tcg_out8(s, args[3]); /* condition */
break;
+
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
/* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
@@ -423,60 +439,54 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_r(s, args[4]);
tcg_out8(s, args[5]); /* condition */
break;
-#elif TCG_TARGET_REG_BITS == 64
- case INDEX_op_setcond_i64:
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_out8(s, args[3]); /* condition */
- break;
#endif
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16s_i32:
+
+ CASE_32_64(ld8u)
+ CASE_32_64(ld8s)
+ CASE_32_64(ld16u)
+ CASE_32_64(ld16s)
case INDEX_op_ld_i32:
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
+ CASE_64(ld32u)
+ CASE_64(ld32s)
+ CASE_64(ld)
+ CASE_32_64(st8)
+ CASE_32_64(st16)
case INDEX_op_st_i32:
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld_i64:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
+ CASE_64(st32)
+ CASE_64(st)
stack_bounds_check(args[1], args[2]);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_debug_assert(args[2] == (int32_t)args[2]);
tcg_out32(s, args[2]);
break;
- case INDEX_op_add_i32:
- case INDEX_op_sub_i32:
- case INDEX_op_mul_i32:
- case INDEX_op_and_i32:
- case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */
- case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */
- case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */
- case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */
- case INDEX_op_or_i32:
- case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */
- case INDEX_op_xor_i32:
- case INDEX_op_shl_i32:
- case INDEX_op_shr_i32:
- case INDEX_op_sar_i32:
- case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
- case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
+
+ CASE_32_64(add)
+ CASE_32_64(sub)
+ CASE_32_64(mul)
+ CASE_32_64(and)
+ CASE_32_64(or)
+ CASE_32_64(xor)
+ CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */
+ CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */
+ CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */
+ CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */
+ CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */
+ CASE_32_64(shl)
+ CASE_32_64(shr)
+ CASE_32_64(sar)
+ CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */
+ CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */
+ CASE_32_64(div) /* Optional (TCG_TARGET_HAS_div_*). */
+ CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */
+ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */
+ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out_r(s, args[2]);
break;
- case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */
+
+ CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out_r(s, args[2]);
@@ -486,79 +496,30 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out8(s, args[4]);
break;
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_add_i64:
- case INDEX_op_sub_i64:
- case INDEX_op_mul_i64:
- case INDEX_op_and_i64:
- case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */
- case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */
- case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */
- case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */
- case INDEX_op_or_i64:
- case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */
- case INDEX_op_xor_i64:
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
- case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
- case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- break;
- case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_debug_assert(args[3] <= UINT8_MAX);
- tcg_out8(s, args[3]);
- tcg_debug_assert(args[4] <= UINT8_MAX);
- tcg_out8(s, args[4]);
- break;
- case INDEX_op_brcond_i64:
+ CASE_32_64(brcond)
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out8(s, args[2]); /* condition */
tci_out_label(s, arg_label(args[3]));
break;
- case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
- case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
- case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
- case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */
- case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */
- case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */
- case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */
- case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */
- case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
- case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
- case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
-#endif /* TCG_TARGET_REG_BITS == 64 */
- case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */
- case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */
- case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */
- case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */
- case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */
- case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */
- case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
- case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
+
+ CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
+ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */
+ CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */
+ CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */
+ CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */
+ CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */
+ CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */
+ CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */
+ CASE_64(ext_i32)
+ CASE_64(extu_i32)
+ CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */
+ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */
+ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
break;
- case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
- case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
- case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
- case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- break;
+
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
@@ -584,31 +545,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_r(s, args[3]);
break;
#endif
- case INDEX_op_brcond_i32:
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out8(s, args[2]); /* condition */
- tci_out_label(s, arg_label(args[3]));
- break;
+
case INDEX_op_qemu_ld_i32:
- tcg_out_r(s, *args++);
- tcg_out_r(s, *args++);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_out_r(s, *args++);
- }
- tcg_out_i(s, *args++);
- break;
- case INDEX_op_qemu_ld_i64:
- tcg_out_r(s, *args++);
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out_r(s, *args++);
- }
- tcg_out_r(s, *args++);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_out_r(s, *args++);
- }
- tcg_out_i(s, *args++);
- break;
case INDEX_op_qemu_st_i32:
tcg_out_r(s, *args++);
tcg_out_r(s, *args++);
@@ -617,6 +555,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
}
tcg_out_i(s, *args++);
break;
+
+ case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
tcg_out_r(s, *args++);
if (TCG_TARGET_REG_BITS == 32) {
@@ -628,8 +568,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
}
tcg_out_i(s, *args++);
break;
+
case INDEX_op_mb:
break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 05/71] tcg/tci: Remove tci_read_r8
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (3 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 04/71] tcg/tci: Merge identical cases in generation Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-18 23:11 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 06/71] tcg/tci: Remove tci_read_r8s Richard Henderson
` (66 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Use explicit casts for ext8u opcodes, and allow truncation
to happen with the store for st8 opcodes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 23 +++++------------------
1 file changed, 5 insertions(+), 18 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 1c667537fe..4ade0ccaf9 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -78,11 +78,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
}
#endif
-static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index)
-{
- return (uint8_t)tci_read_reg(regs, index);
-}
-
static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index)
{
return (uint16_t)tci_read_reg(regs, index);
@@ -169,14 +164,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
return value;
}
-/* Read indexed register (8 bit) from bytecode. */
-static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
-{
- uint8_t value = tci_read_reg8(regs, **tb_ptr);
- *tb_ptr += 1;
- return value;
-}
-
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
/* Read indexed register (8 bit signed) from bytecode. */
static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
@@ -533,7 +520,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
break;
CASE_32_64(st8)
- t0 = tci_read_r8(regs, &tb_ptr);
+ t0 = tci_read_r(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0;
@@ -722,8 +709,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_ext8u_i32
case INDEX_op_ext8u_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r8(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ t1 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint8_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i32
@@ -916,8 +903,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_ext8u_i64
case INDEX_op_ext8u_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r8(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ t1 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint8_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext8s_i64
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 06/71] tcg/tci: Remove tci_read_r8s
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (4 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 05/71] tcg/tci: Remove tci_read_r8 Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-18 23:12 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 07/71] tcg/tci: Remove tci_read_r16 Richard Henderson
` (65 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Use explicit casts for ext8s opcodes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 25 ++++---------------------
1 file changed, 4 insertions(+), 21 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 4ade0ccaf9..7325c8bfd0 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
return regs[index];
}
-#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
-static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index)
-{
- return (int8_t)tci_read_reg(regs, index);
-}
-#endif
-
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index)
{
@@ -164,16 +157,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
return value;
}
-#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
-/* Read indexed register (8 bit signed) from bytecode. */
-static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
-{
- int8_t value = tci_read_reg8s(regs, **tb_ptr);
- *tb_ptr += 1;
- return value;
-}
-#endif
-
/* Read indexed register (16 bit) from bytecode. */
static uint16_t tci_read_r16(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
@@ -695,8 +678,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_ext8s_i32
case INDEX_op_ext8s_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r8s(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ t1 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (int8_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i32
@@ -910,8 +893,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_ext8s_i64
case INDEX_op_ext8s_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r8s(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ t1 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (int8_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i64
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 07/71] tcg/tci: Remove tci_read_r16
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (5 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 06/71] tcg/tci: Remove tci_read_r8s Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-19 0:03 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 08/71] tcg/tci: Remove tci_read_r16s Richard Henderson
` (64 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Use explicit casts for ext16u opcodes, and allow truncation
to happen with the store for st16 opcodes, and with the call
for bswap16 opcodes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 28 +++++++---------------------
1 file changed, 7 insertions(+), 21 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 7325c8bfd0..2440da1746 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -71,11 +71,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
}
#endif
-static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index)
-{
- return (uint16_t)tci_read_reg(regs, index);
-}
-
static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index)
{
return (uint32_t)tci_read_reg(regs, index);
@@ -157,15 +152,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
return value;
}
-/* Read indexed register (16 bit) from bytecode. */
-static uint16_t tci_read_r16(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- uint16_t value = tci_read_reg16(regs, **tb_ptr);
- *tb_ptr += 1;
- return value;
-}
-
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
/* Read indexed register (16 bit signed) from bytecode. */
static int16_t tci_read_r16s(const tcg_target_ulong *regs,
@@ -509,7 +495,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
*(uint8_t *)(t1 + t2) = t0;
break;
CASE_32_64(st16)
- t0 = tci_read_r16(regs, &tb_ptr);
+ t0 = tci_read_r(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint16_t *)(t1 + t2) = t0;
@@ -699,14 +685,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_ext16u_i32
case INDEX_op_ext16u_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r16(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ t1 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint16_t)t1);
break;
#endif
#if TCG_TARGET_HAS_bswap16_i32
case INDEX_op_bswap16_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r16(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap16(t1));
break;
#endif
@@ -907,8 +893,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_ext16u_i64
case INDEX_op_ext16u_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r16(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ t1 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint16_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext32s_i64
@@ -930,7 +916,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_bswap16_i64
case INDEX_op_bswap16_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r16(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap16(t1));
break;
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 08/71] tcg/tci: Remove tci_read_r16s
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (6 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 07/71] tcg/tci: Remove tci_read_r16 Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-18 23:15 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 09/71] tcg/tci: Remove tci_read_r32 Richard Henderson
` (63 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Use explicit casts for ext16s opcodes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 26 ++++----------------------
1 file changed, 4 insertions(+), 22 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 2440da1746..8b91e6efc3 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
return regs[index];
}
-#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
-static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index)
-{
- return (int16_t)tci_read_reg(regs, index);
-}
-#endif
-
#if TCG_TARGET_REG_BITS == 64
static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
{
@@ -152,17 +145,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
return value;
}
-#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
-/* Read indexed register (16 bit signed) from bytecode. */
-static int16_t tci_read_r16s(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- int16_t value = tci_read_reg16s(regs, **tb_ptr);
- *tb_ptr += 1;
- return value;
-}
-#endif
-
/* Read indexed register (32 bit) from bytecode. */
static uint32_t tci_read_r32(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
@@ -671,8 +653,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_ext16s_i32
case INDEX_op_ext16s_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r16s(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ t1 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (int16_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext8u_i32
@@ -886,8 +868,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_ext16s_i64
case INDEX_op_ext16s_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r16s(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ t1 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (int16_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i64
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 09/71] tcg/tci: Remove tci_read_r32
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (7 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 08/71] tcg/tci: Remove tci_read_r16s Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-19 0:06 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 10/71] tcg/tci: Remove tci_read_r32s Richard Henderson
` (62 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Use explicit casts for ext32u opcodes, and allow truncation
to happen for other users.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 122 ++++++++++++++++++++++++------------------------------
1 file changed, 54 insertions(+), 68 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 8b91e6efc3..a5aaa763f8 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -64,11 +64,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
}
#endif
-static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index)
-{
- return (uint32_t)tci_read_reg(regs, index);
-}
-
#if TCG_TARGET_REG_BITS == 64
static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
{
@@ -145,22 +140,13 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
return value;
}
-/* Read indexed register (32 bit) from bytecode. */
-static uint32_t tci_read_r32(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- uint32_t value = tci_read_reg32(regs, **tb_ptr);
- *tb_ptr += 1;
- return value;
-}
-
#if TCG_TARGET_REG_BITS == 32
/* Read two indexed registers (2 * 32 bit) from bytecode. */
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
{
- uint32_t low = tci_read_r32(regs, tb_ptr);
- return tci_uint64(tci_read_r32(regs, tb_ptr), low);
+ uint32_t low = tci_read_r(regs, tb_ptr);
+ return tci_uint64(tci_read_r(regs, tb_ptr), low);
}
#elif TCG_TARGET_REG_BITS == 64
/* Read indexed register (32 bit signed) from bytecode. */
@@ -404,8 +390,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
continue;
case INDEX_op_setcond_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
break;
@@ -428,7 +414,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
case INDEX_op_mov_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1);
break;
case INDEX_op_tci_movi_i32:
@@ -484,7 +470,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
case INDEX_op_st_i32:
CASE_64(st32)
- t0 = tci_read_r32(regs, &tb_ptr);
+ t0 = tci_read_r(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint32_t *)(t1 + t2) = t0;
@@ -494,62 +480,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_add_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2);
break;
case INDEX_op_sub_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2);
break;
case INDEX_op_mul_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
case INDEX_op_div_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
break;
case INDEX_op_divu_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 / t2);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
break;
case INDEX_op_rem_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
break;
case INDEX_op_remu_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 % t2);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
break;
case INDEX_op_and_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 & t2);
break;
case INDEX_op_or_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 | t2);
break;
case INDEX_op_xor_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 ^ t2);
break;
@@ -557,41 +543,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 << (t2 & 31));
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
break;
case INDEX_op_shr_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 >> (t2 & 31));
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
break;
case INDEX_op_sar_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31)));
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, rol32(t1, t2 & 31));
break;
case INDEX_op_rotr_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ror32(t1, t2 & 31));
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
case INDEX_op_deposit_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp32 = (((1 << tmp8) - 1) << tmp16);
@@ -599,8 +585,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i32:
- t0 = tci_read_r32(regs, &tb_ptr);
- t1 = tci_read_r32(regs, &tb_ptr);
+ t0 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare32(t0, t1, condition)) {
@@ -638,9 +624,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_mulu2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
- t2 = tci_read_r32(regs, &tb_ptr);
- tmp64 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg64(regs, t1, t0, t2 * tmp64);
+ t2 = tci_read_r(regs, &tb_ptr);
+ tmp64 = (uint32_t)tci_read_r(regs, &tb_ptr);
+ tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32
@@ -681,21 +667,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_bswap32_i32
case INDEX_op_bswap32_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap32(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i32
case INDEX_op_not_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i32
case INDEX_op_neg_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, -t1);
break;
#endif
@@ -892,8 +878,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
case INDEX_op_extu_i32_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ t1 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint32_t)t1);
break;
#if TCG_TARGET_HAS_bswap16_i64
case INDEX_op_bswap16_i64:
@@ -905,7 +891,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_bswap32_i64
case INDEX_op_bswap32_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r32(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap32(t1));
break;
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 10/71] tcg/tci: Remove tci_read_r32s
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (8 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 09/71] tcg/tci: Remove tci_read_r32 Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-18 23:16 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 11/71] tcg/tci: Reduce use of tci_read_r64 Richard Henderson
` (61 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Use explicit casts for ext32s opcodes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 20 ++------------------
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index a5aaa763f8..cef12f263d 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
return regs[index];
}
-#if TCG_TARGET_REG_BITS == 64
-static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
-{
- return (int32_t)tci_read_reg(regs, index);
-}
-#endif
-
#if TCG_TARGET_REG_BITS == 64
static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
{
@@ -149,15 +142,6 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
return tci_uint64(tci_read_r(regs, tb_ptr), low);
}
#elif TCG_TARGET_REG_BITS == 64
-/* Read indexed register (32 bit signed) from bytecode. */
-static int32_t tci_read_r32s(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- int32_t value = tci_read_reg32s(regs, **tb_ptr);
- *tb_ptr += 1;
- return value;
-}
-
/* Read indexed register (64 bit) from bytecode. */
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
@@ -870,8 +854,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
case INDEX_op_ext_i32_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r32s(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ t1 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (int32_t)t1);
break;
#if TCG_TARGET_HAS_ext32u_i64
case INDEX_op_ext32u_i64:
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 11/71] tcg/tci: Reduce use of tci_read_r64
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (9 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 10/71] tcg/tci: Remove tci_read_r32s Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-19 0:05 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 12/71] tcg/tci: Merge basic arithmetic operations Richard Henderson
` (60 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
In all cases restricted to 64-bit hosts, tcg_read_r is
identical. We retain the 64-bit symbol for the single
case of INDEX_op_qemu_st_i64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------
1 file changed, 42 insertions(+), 51 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index cef12f263d..9efe69d05f 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
return regs[index];
}
-#if TCG_TARGET_REG_BITS == 64
-static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
-{
- return tci_read_reg(regs, index);
-}
-#endif
-
static void
tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
{
@@ -146,9 +139,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
{
- uint64_t value = tci_read_reg64(regs, **tb_ptr);
- *tb_ptr += 1;
- return value;
+ return tci_read_r(regs, tb_ptr);
}
#endif
@@ -390,8 +381,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
break;
@@ -672,7 +663,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_mov_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1);
break;
case INDEX_op_tci_movi_i64:
@@ -696,7 +687,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break;
case INDEX_op_st_i64:
- t0 = tci_read_r64(regs, &tb_ptr);
+ t0 = tci_read_r(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint64_t *)(t1 + t2) = t0;
@@ -706,62 +697,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_add_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2);
break;
case INDEX_op_sub_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2);
break;
case INDEX_op_mul_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
case INDEX_op_div_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
break;
case INDEX_op_divu_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
break;
case INDEX_op_rem_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
break;
case INDEX_op_remu_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
break;
case INDEX_op_and_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 & t2);
break;
case INDEX_op_or_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 | t2);
break;
case INDEX_op_xor_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 ^ t2);
break;
@@ -769,41 +760,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, rol64(t1, t2 & 63));
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ror64(t1, t2 & 63));
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
case INDEX_op_deposit_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
@@ -811,8 +802,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i64:
- t0 = tci_read_r64(regs, &tb_ptr);
- t1 = tci_read_r64(regs, &tb_ptr);
+ t0 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(t0, t1, condition)) {
@@ -882,21 +873,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap64(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i64
case INDEX_op_not_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i64
case INDEX_op_neg_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, -t1);
break;
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 12/71] tcg/tci: Merge basic arithmetic operations
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (10 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 11/71] tcg/tci: Reduce use of tci_read_r64 Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-18 23:17 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 13/71] tcg/tci: Merge extension operations Richard Henderson
` (59 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
This includes add, sub, mul, and, or, xor.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 83 +++++++++++++++++--------------------------------------
1 file changed, 25 insertions(+), 58 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 9efe69d05f..d0bf810781 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -451,26 +451,47 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
*(uint32_t *)(t1 + t2) = t0;
break;
- /* Arithmetic operations (32 bit). */
+ /* Arithmetic operations (mixed 32/64 bit). */
- case INDEX_op_add_i32:
+ CASE_32_64(add)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2);
break;
- case INDEX_op_sub_i32:
+ CASE_32_64(sub)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2);
break;
- case INDEX_op_mul_i32:
+ CASE_32_64(mul)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
+ CASE_32_64(and)
+ t0 = *tb_ptr++;
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, t1 & t2);
+ break;
+ CASE_32_64(or)
+ t0 = *tb_ptr++;
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, t1 | t2);
+ break;
+ CASE_32_64(xor)
+ t0 = *tb_ptr++;
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
+ tci_write_reg(regs, t0, t1 ^ t2);
+ break;
+
+ /* Arithmetic operations (32 bit). */
+
case INDEX_op_div_i32:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
@@ -495,24 +516,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
break;
- case INDEX_op_and_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 & t2);
- break;
- case INDEX_op_or_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 | t2);
- break;
- case INDEX_op_xor_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 ^ t2);
- break;
/* Shift/rotate operations (32 bit). */
@@ -695,24 +698,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (64 bit). */
- case INDEX_op_add_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 + t2);
- break;
- case INDEX_op_sub_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 - t2);
- break;
- case INDEX_op_mul_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 * t2);
- break;
case INDEX_op_div_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
@@ -737,24 +722,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
break;
- case INDEX_op_and_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 & t2);
- break;
- case INDEX_op_or_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 | t2);
- break;
- case INDEX_op_xor_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 ^ t2);
- break;
/* Shift/rotate operations (64 bit). */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 13/71] tcg/tci: Merge extension operations
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (11 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 12/71] tcg/tci: Merge basic arithmetic operations Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-18 23:22 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 14/71] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
` (58 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
This includes ext8s, ext8u, ext16s, ext16u.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 44 ++++++++------------------------------------
1 file changed, 8 insertions(+), 36 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index d0bf810781..73f639d23a 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -607,29 +607,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
-#if TCG_TARGET_HAS_ext8s_i32
- case INDEX_op_ext8s_i32:
+#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
+ CASE_32_64(ext8s)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int8_t)t1);
break;
#endif
-#if TCG_TARGET_HAS_ext16s_i32
- case INDEX_op_ext16s_i32:
+#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
+ CASE_32_64(ext16s)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int16_t)t1);
break;
#endif
-#if TCG_TARGET_HAS_ext8u_i32
- case INDEX_op_ext8u_i32:
+#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
+ CASE_32_64(ext8u)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint8_t)t1);
break;
#endif
-#if TCG_TARGET_HAS_ext16u_i32
- case INDEX_op_ext16u_i32:
+#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
+ CASE_32_64(ext16u)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint16_t)t1);
@@ -779,34 +779,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
continue;
}
break;
-#if TCG_TARGET_HAS_ext8u_i64
- case INDEX_op_ext8u_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint8_t)t1);
- break;
-#endif
-#if TCG_TARGET_HAS_ext8s_i64
- case INDEX_op_ext8s_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int8_t)t1);
- break;
-#endif
-#if TCG_TARGET_HAS_ext16s_i64
- case INDEX_op_ext16s_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int16_t)t1);
- break;
-#endif
-#if TCG_TARGET_HAS_ext16u_i64
- case INDEX_op_ext16u_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint16_t)t1);
- break;
-#endif
#if TCG_TARGET_HAS_ext32s_i64
case INDEX_op_ext32s_i64:
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 14/71] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (12 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 13/71] tcg/tci: Merge extension operations Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 15/71] tcg/tci: Merge bswap operations Richard Henderson
` (57 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
These operations are always available under different names:
INDEX_op_ext_i32_i64 and INDEX_op_extu_i32_i64, so we remove
no code with the ifdef.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 73f639d23a..a5ee37eb4e 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -779,17 +779,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
continue;
}
break;
-#if TCG_TARGET_HAS_ext32s_i64
case INDEX_op_ext32s_i64:
-#endif
case INDEX_op_ext_i32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1);
break;
-#if TCG_TARGET_HAS_ext32u_i64
case INDEX_op_ext32u_i64:
-#endif
case INDEX_op_extu_i32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 15/71] tcg/tci: Merge bswap operations
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (13 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 14/71] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-18 23:19 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 16/71] tcg/tci: Merge mov, not and neg operations Richard Henderson
` (56 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
This includes bswap16 and bswap32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 22 ++++------------------
1 file changed, 4 insertions(+), 18 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index a5ee37eb4e..288a70287e 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -635,15 +635,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg(regs, t0, (uint16_t)t1);
break;
#endif
-#if TCG_TARGET_HAS_bswap16_i32
- case INDEX_op_bswap16_i32:
+#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
+ CASE_32_64(bswap16)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap16(t1));
break;
#endif
-#if TCG_TARGET_HAS_bswap32_i32
- case INDEX_op_bswap32_i32:
+#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
+ CASE_32_64(bswap32)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap32(t1));
@@ -791,20 +791,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1);
break;
-#if TCG_TARGET_HAS_bswap16_i64
- case INDEX_op_bswap16_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, bswap16(t1));
- break;
-#endif
-#if TCG_TARGET_HAS_bswap32_i64
- case INDEX_op_bswap32_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, bswap32(t1));
- break;
-#endif
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
t0 = *tb_ptr++;
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 16/71] tcg/tci: Merge mov, not and neg operations
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (14 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 15/71] tcg/tci: Merge bswap operations Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-18 23:20 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 17/71] tcg/tci: Rename tci_read_r to tci_read_rval Richard Henderson
` (55 subsequent siblings)
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 29 +++++------------------------
1 file changed, 5 insertions(+), 24 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 288a70287e..6a0bdf028b 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -387,7 +387,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
break;
#endif
- case INDEX_op_mov_i32:
+ CASE_32_64(mov)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1);
@@ -649,26 +649,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg(regs, t0, bswap32(t1));
break;
#endif
-#if TCG_TARGET_HAS_not_i32
- case INDEX_op_not_i32:
+#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
+ CASE_32_64(not)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ~t1);
break;
#endif
-#if TCG_TARGET_HAS_neg_i32
- case INDEX_op_neg_i32:
+#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
+ CASE_32_64(neg)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, -t1);
break;
#endif
#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_mov_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
- break;
case INDEX_op_tci_movi_i64:
t0 = *tb_ptr++;
t1 = tci_read_i64(&tb_ptr);
@@ -798,20 +793,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg(regs, t0, bswap64(t1));
break;
#endif
-#if TCG_TARGET_HAS_not_i64
- case INDEX_op_not_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, ~t1);
- break;
-#endif
-#if TCG_TARGET_HAS_neg_i64
- case INDEX_op_neg_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, -t1);
- break;
-#endif
#endif /* TCG_TARGET_REG_BITS == 64 */
/* QEMU specific operations. */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 17/71] tcg/tci: Rename tci_read_r to tci_read_rval
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (15 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 16/71] tcg/tci: Merge mov, not and neg operations Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 18/71] tcg/tci: Split out tci_args_rrs Richard Henderson
` (54 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
In the next patches, we want to use tci_read_r to return
the raw register number. So rename the existing function,
which returns the register value, to tci_read_rval.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 192 +++++++++++++++++++++++++++---------------------------
1 file changed, 96 insertions(+), 96 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 6a0bdf028b..6d6a5510da 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -119,7 +119,7 @@ static uint64_t tci_read_i64(const uint8_t **tb_ptr)
/* Read indexed register (native size) from bytecode. */
static tcg_target_ulong
-tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
+tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
{
tcg_target_ulong value = tci_read_reg(regs, **tb_ptr);
*tb_ptr += 1;
@@ -131,15 +131,15 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
{
- uint32_t low = tci_read_r(regs, tb_ptr);
- return tci_uint64(tci_read_r(regs, tb_ptr), low);
+ uint32_t low = tci_read_rval(regs, tb_ptr);
+ return tci_uint64(tci_read_rval(regs, tb_ptr), low);
}
#elif TCG_TARGET_REG_BITS == 64
/* Read indexed register (64 bit) from bytecode. */
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
{
- return tci_read_r(regs, tb_ptr);
+ return tci_read_rval(regs, tb_ptr);
}
#endif
@@ -147,9 +147,9 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
static target_ulong
tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
{
- target_ulong taddr = tci_read_r(regs, tb_ptr);
+ target_ulong taddr = tci_read_rval(regs, tb_ptr);
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
- taddr += (uint64_t)tci_read_r(regs, tb_ptr) << 32;
+ taddr += (uint64_t)tci_read_rval(regs, tb_ptr) << 32;
#endif
return taddr;
}
@@ -365,8 +365,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
continue;
case INDEX_op_setcond_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
break;
@@ -381,15 +381,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
break;
#endif
CASE_32_64(mov)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1);
break;
case INDEX_op_tci_movi_i32:
@@ -402,51 +402,51 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
CASE_32_64(ld8u)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
break;
CASE_32_64(ld8s)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(int8_t *)(t1 + t2));
break;
CASE_32_64(ld16u)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2));
break;
CASE_32_64(ld16s)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(int16_t *)(t1 + t2));
break;
case INDEX_op_ld_i32:
CASE_64(ld32u)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
break;
CASE_32_64(st8)
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0;
break;
CASE_32_64(st16)
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint16_t *)(t1 + t2) = t0;
break;
case INDEX_op_st_i32:
CASE_64(st32)
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint32_t *)(t1 + t2) = t0;
break;
@@ -455,38 +455,38 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
CASE_32_64(add)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2);
break;
CASE_32_64(sub)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2);
break;
CASE_32_64(mul)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
CASE_32_64(and)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 & t2);
break;
CASE_32_64(or)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 | t2);
break;
CASE_32_64(xor)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 ^ t2);
break;
@@ -494,26 +494,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_div_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
break;
case INDEX_op_divu_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
break;
case INDEX_op_rem_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
break;
case INDEX_op_remu_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
break;
@@ -521,41 +521,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
break;
case INDEX_op_shr_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
break;
case INDEX_op_sar_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, rol32(t1, t2 & 31));
break;
case INDEX_op_rotr_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ror32(t1, t2 & 31));
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
case INDEX_op_deposit_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp32 = (((1 << tmp8) - 1) << tmp16);
@@ -563,8 +563,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i32:
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare32(t0, t1, condition)) {
@@ -602,64 +602,64 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_mulu2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
- t2 = tci_read_r(regs, &tb_ptr);
- tmp64 = (uint32_t)tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
+ tmp64 = (uint32_t)tci_read_rval(regs, &tb_ptr);
tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
CASE_32_64(ext8s)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int8_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
CASE_32_64(ext16s)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int16_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
CASE_32_64(ext8u)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint8_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
CASE_32_64(ext16u)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint16_t)t1);
break;
#endif
#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
CASE_32_64(bswap16)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap16(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
CASE_32_64(bswap32)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap32(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
CASE_32_64(not)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
CASE_32_64(neg)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, -t1);
break;
#endif
@@ -674,19 +674,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ld32s_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(int32_t *)(t1 + t2));
break;
case INDEX_op_ld_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break;
case INDEX_op_st_i64:
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint64_t *)(t1 + t2) = t0;
break;
@@ -695,26 +695,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_div_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
break;
case INDEX_op_divu_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
break;
case INDEX_op_rem_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
break;
case INDEX_op_remu_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
break;
@@ -722,41 +722,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, rol64(t1, t2 & 63));
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ror64(t1, t2 & 63));
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
case INDEX_op_deposit_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
@@ -764,8 +764,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i64:
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(t0, t1, condition)) {
@@ -777,19 +777,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ext32s_i64:
case INDEX_op_ext_i32_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1);
break;
case INDEX_op_ext32u_i64:
case INDEX_op_extu_i32_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1);
break;
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap64(t1));
break;
#endif
@@ -896,7 +896,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
break;
case INDEX_op_qemu_st_i32:
- t0 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
taddr = tci_read_ulong(regs, &tb_ptr);
oi = tci_read_i(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 18/71] tcg/tci: Split out tci_args_rrs
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (16 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 17/71] tcg/tci: Rename tci_read_r to tci_read_rval Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 19/71] tcg/tci: Split out tci_args_rr Richard Henderson
` (53 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Begin splitting out functions that do pure argument decode,
without actually loading values from the register set.
This means that decoding need not concern itself between
input and output registers. We can assert that the register
number is in range during decode, so that it is safe to
simply dereference from regs[] later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 111 ++++++++++++++++++++++++++++++++----------------------
1 file changed, 67 insertions(+), 44 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 6d6a5510da..5acf5c38c3 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -83,6 +83,20 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low)
}
#endif
+/* Read constant byte from bytecode. */
+static uint8_t tci_read_b(const uint8_t **tb_ptr)
+{
+ return *(tb_ptr[0]++);
+}
+
+/* Read register number from bytecode. */
+static TCGReg tci_read_r(const uint8_t **tb_ptr)
+{
+ uint8_t regno = tci_read_b(tb_ptr);
+ tci_assert(regno < TCG_TARGET_NB_REGS);
+ return regno;
+}
+
/* Read constant (native size) from bytecode. */
static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr)
{
@@ -161,6 +175,23 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
return label;
}
+/*
+ * Load sets of arguments all at once. The naming convention is:
+ * tci_args_<arguments>
+ * where arguments is a sequence of
+ *
+ * r = register
+ * s = signed ldst offset
+ */
+
+static void tci_args_rrs(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, int32_t *i2)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *i2 = tci_read_s32(tb_ptr);
+}
+
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
{
bool result = false;
@@ -311,6 +342,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint8_t op_size = tb_ptr[1];
const uint8_t *old_code_ptr = tb_ptr;
#endif
+ TCGReg r0, r1;
tcg_target_ulong t0;
tcg_target_ulong t1;
tcg_target_ulong t2;
@@ -325,6 +357,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint64_t v64;
#endif
TCGMemOpIdx oi;
+ int32_t ofs;
+ void *ptr;
/* Skip opcode and size entry. */
tb_ptr += 2;
@@ -401,54 +435,46 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Load/store operations (32 bit). */
CASE_32_64(ld8u)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ regs[r0] = *(uint8_t *)ptr;
break;
CASE_32_64(ld8s)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(int8_t *)(t1 + t2));
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ regs[r0] = *(int8_t *)ptr;
break;
CASE_32_64(ld16u)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2));
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ regs[r0] = *(uint16_t *)ptr;
break;
CASE_32_64(ld16s)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(int16_t *)(t1 + t2));
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ regs[r0] = *(int16_t *)ptr;
break;
case INDEX_op_ld_i32:
CASE_64(ld32u)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ regs[r0] = *(uint32_t *)ptr;
break;
CASE_32_64(st8)
- t0 = tci_read_rval(regs, &tb_ptr);
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- *(uint8_t *)(t1 + t2) = t0;
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ *(uint8_t *)ptr = regs[r0];
break;
CASE_32_64(st16)
- t0 = tci_read_rval(regs, &tb_ptr);
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- *(uint16_t *)(t1 + t2) = t0;
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ *(uint16_t *)ptr = regs[r0];
break;
case INDEX_op_st_i32:
CASE_64(st32)
- t0 = tci_read_rval(regs, &tb_ptr);
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- *(uint32_t *)(t1 + t2) = t0;
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ *(uint32_t *)ptr = regs[r0];
break;
/* Arithmetic operations (mixed 32/64 bit). */
@@ -673,22 +699,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Load/store operations (64 bit). */
case INDEX_op_ld32s_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(int32_t *)(t1 + t2));
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ regs[r0] = *(int32_t *)ptr;
break;
case INDEX_op_ld_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ regs[r0] = *(uint64_t *)ptr;
break;
case INDEX_op_st_i64:
- t0 = tci_read_rval(regs, &tb_ptr);
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- *(uint64_t *)(t1 + t2) = t0;
+ tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ ptr = (void *)(regs[r1] + ofs);
+ *(uint64_t *)ptr = regs[r0];
break;
/* Arithmetic operations (64 bit). */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 19/71] tcg/tci: Split out tci_args_rr
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (17 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 18/71] tcg/tci: Split out tci_args_rrs Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 20/71] tcg/tci: Split out tci_args_rrr Richard Henderson
` (52 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 67 +++++++++++++++++++++++++------------------------------
1 file changed, 31 insertions(+), 36 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 5acf5c38c3..e5aba3a9fa 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -184,6 +184,13 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* s = signed ldst offset
*/
+static void tci_args_rr(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+}
+
static void tci_args_rrs(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, int32_t *i2)
{
@@ -422,9 +429,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
CASE_32_64(mov)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = regs[r1];
break;
case INDEX_op_tci_movi_i32:
t0 = *tb_ptr++;
@@ -635,58 +641,50 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
CASE_32_64(ext8s)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int8_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (int8_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
CASE_32_64(ext16s)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int16_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (int16_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
CASE_32_64(ext8u)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint8_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (uint8_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
CASE_32_64(ext16u)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint16_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (uint16_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
CASE_32_64(bswap16)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, bswap16(t1));
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = bswap16(regs[r1]);
break;
#endif
#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
CASE_32_64(bswap32)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, bswap32(t1));
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = bswap32(regs[r1]);
break;
#endif
#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
CASE_32_64(not)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, ~t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = ~regs[r1];
break;
#endif
#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
CASE_32_64(neg)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, -t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = -regs[r1];
break;
#endif
#if TCG_TARGET_REG_BITS == 64
@@ -799,21 +797,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
case INDEX_op_ext32s_i64:
case INDEX_op_ext_i32_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int32_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (int32_t)regs[r1];
break;
case INDEX_op_ext32u_i64:
case INDEX_op_extu_i32_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint32_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (uint32_t)regs[r1];
break;
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, bswap64(t1));
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = bswap64(regs[r1]);
break;
#endif
#endif /* TCG_TARGET_REG_BITS == 64 */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 20/71] tcg/tci: Split out tci_args_rrr
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (18 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 19/71] tcg/tci: Split out tci_args_rr Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 21/71] tcg/tci: Split out tci_args_rrrc Richard Henderson
` (51 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 154 ++++++++++++++++++++----------------------------------
1 file changed, 57 insertions(+), 97 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index e5aba3a9fa..1c879a2536 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -191,6 +191,14 @@ static void tci_args_rr(const uint8_t **tb_ptr,
*r1 = tci_read_r(tb_ptr);
}
+static void tci_args_rrr(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGReg *r2)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+}
+
static void tci_args_rrs(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, int32_t *i2)
{
@@ -349,7 +357,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint8_t op_size = tb_ptr[1];
const uint8_t *old_code_ptr = tb_ptr;
#endif
- TCGReg r0, r1;
+ TCGReg r0, r1, r2;
tcg_target_ulong t0;
tcg_target_ulong t1;
tcg_target_ulong t2;
@@ -486,101 +494,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (mixed 32/64 bit). */
CASE_32_64(add)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 + t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] + regs[r2];
break;
CASE_32_64(sub)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 - t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] - regs[r2];
break;
CASE_32_64(mul)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 * t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] * regs[r2];
break;
CASE_32_64(and)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 & t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] & regs[r2];
break;
CASE_32_64(or)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 | t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] | regs[r2];
break;
CASE_32_64(xor)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 ^ t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] ^ regs[r2];
break;
/* Arithmetic operations (32 bit). */
case INDEX_op_div_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2];
break;
case INDEX_op_divu_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2];
break;
case INDEX_op_rem_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2];
break;
case INDEX_op_remu_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
break;
/* Shift/rotate operations (32 bit). */
case INDEX_op_shl_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31);
break;
case INDEX_op_shr_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31);
break;
case INDEX_op_sar_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31);
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, rol32(t1, t2 & 31));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = rol32(regs[r1], regs[r2] & 31);
break;
case INDEX_op_rotr_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, ror32(t1, t2 & 31));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = ror32(regs[r1], regs[r2] & 31);
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
@@ -715,62 +693,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (64 bit). */
case INDEX_op_div_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2];
break;
case INDEX_op_divu_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2];
break;
case INDEX_op_rem_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2];
break;
case INDEX_op_remu_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
break;
/* Shift/rotate operations (64 bit). */
case INDEX_op_shl_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 << (t2 & 63));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] << (regs[r2] & 63);
break;
case INDEX_op_shr_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 >> (t2 & 63));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] >> (regs[r2] & 63);
break;
case INDEX_op_sar_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63);
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, rol64(t1, t2 & 63));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = rol64(regs[r1], regs[r2] & 63);
break;
case INDEX_op_rotr_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, ror64(t1, t2 & 63));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = ror64(regs[r1], regs[r2] & 63);
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 21/71] tcg/tci: Split out tci_args_rrrc
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (19 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 20/71] tcg/tci: Split out tci_args_rrr Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 22/71] tcg/tci: Split out tci_args_l Richard Henderson
` (50 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 1c879a2536..bdd2127ec8 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -207,6 +207,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr,
*i2 = tci_read_s32(tb_ptr);
}
+static void tci_args_rrrc(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *c3 = tci_read_b(tb_ptr);
+}
+
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
{
bool result = false;
@@ -413,11 +422,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tb_ptr = (uint8_t *)label;
continue;
case INDEX_op_setcond_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- condition = *tb_ptr++;
- tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
+ tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition);
+ regs[r0] = tci_compare32(regs[r1], regs[r2], condition);
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
@@ -429,11 +435,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- condition = *tb_ptr++;
- tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
+ tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition);
+ regs[r0] = tci_compare64(regs[r1], regs[r2], condition);
break;
#endif
CASE_32_64(mov)
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 22/71] tcg/tci: Split out tci_args_l
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (20 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 21/71] tcg/tci: Split out tci_args_rrrc Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 23/71] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
` (49 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index bdd2127ec8..6e9d482885 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -184,6 +184,11 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* s = signed ldst offset
*/
+static void tci_args_l(const uint8_t **tb_ptr, void **l0)
+{
+ *l0 = (void *)tci_read_label(tb_ptr);
+}
+
static void tci_args_rr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1)
{
@@ -417,9 +422,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
break;
case INDEX_op_br:
- label = tci_read_label(&tb_ptr);
+ tci_args_l(&tb_ptr, &ptr);
tci_assert(tb_ptr == old_code_ptr + op_size);
- tb_ptr = (uint8_t *)label;
+ tb_ptr = ptr;
continue;
case INDEX_op_setcond_i32:
tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition);
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 23/71] tcg/tci: Split out tci_args_rrrrrc
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (21 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 22/71] tcg/tci: Split out tci_args_l Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 24/71] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
` (48 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 6e9d482885..558d03fd1b 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -221,6 +221,19 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
*c3 = tci_read_b(tb_ptr);
}
+#if TCG_TARGET_REG_BITS == 32
+static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+ TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *r3 = tci_read_r(tb_ptr);
+ *r4 = tci_read_r(tb_ptr);
+ *c5 = tci_read_b(tb_ptr);
+}
+#endif
+
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
{
bool result = false;
@@ -383,7 +396,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
- uint64_t v64;
+ TCGReg r3, r4;
+ uint64_t v64, T1, T2;
#endif
TCGMemOpIdx oi;
int32_t ofs;
@@ -432,11 +446,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
- t0 = *tb_ptr++;
- tmp64 = tci_read_r64(regs, &tb_ptr);
- v64 = tci_read_r64(regs, &tb_ptr);
- condition = *tb_ptr++;
- tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition));
+ tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition);
+ T1 = tci_uint64(regs[r2], regs[r1]);
+ T2 = tci_uint64(regs[r4], regs[r3]);
+ regs[r0] = tci_compare64(T1, T2, condition);
break;
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 24/71] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (22 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 23/71] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 25/71] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
` (47 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 52 ++++++++++++++++++++++++++++++++--------------------
1 file changed, 32 insertions(+), 20 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 558d03fd1b..c8df45ce28 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -212,6 +212,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr,
*i2 = tci_read_s32(tb_ptr);
}
+static void tci_args_rrcl(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *c2 = tci_read_b(tb_ptr);
+ *l3 = (void *)tci_read_label(tb_ptr);
+}
+
static void tci_args_rrrc(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{
@@ -222,6 +231,17 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
}
#if TCG_TARGET_REG_BITS == 32
+static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+ TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *r3 = tci_read_r(tb_ptr);
+ *c4 = tci_read_b(tb_ptr);
+ *l5 = (void *)tci_read_label(tb_ptr);
+}
+
static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
{
@@ -388,7 +408,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tcg_target_ulong t0;
tcg_target_ulong t1;
tcg_target_ulong t2;
- tcg_target_ulong label;
TCGCond condition;
target_ulong taddr;
uint8_t tmp8;
@@ -397,7 +416,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
TCGReg r3, r4;
- uint64_t v64, T1, T2;
+ uint64_t T1, T2;
#endif
TCGMemOpIdx oi;
int32_t ofs;
@@ -594,13 +613,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i32:
- t0 = tci_read_rval(regs, &tb_ptr);
- t1 = tci_read_rval(regs, &tb_ptr);
- condition = *tb_ptr++;
- label = tci_read_label(&tb_ptr);
- if (tci_compare32(t0, t1, condition)) {
+ tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
+ if (tci_compare32(regs[r0], regs[r1], condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size);
- tb_ptr = (uint8_t *)label;
+ tb_ptr = ptr;
continue;
}
break;
@@ -620,13 +636,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg64(regs, t1, t0, tmp64);
break;
case INDEX_op_brcond2_i32:
- tmp64 = tci_read_r64(regs, &tb_ptr);
- v64 = tci_read_r64(regs, &tb_ptr);
- condition = *tb_ptr++;
- label = tci_read_label(&tb_ptr);
- if (tci_compare64(tmp64, v64, condition)) {
+ tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr);
+ T1 = tci_uint64(regs[r1], regs[r0]);
+ T2 = tci_uint64(regs[r3], regs[r2]);
+ if (tci_compare64(T1, T2, condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size);
- tb_ptr = (uint8_t *)label;
+ tb_ptr = ptr;
continue;
}
break;
@@ -766,13 +781,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i64:
- t0 = tci_read_rval(regs, &tb_ptr);
- t1 = tci_read_rval(regs, &tb_ptr);
- condition = *tb_ptr++;
- label = tci_read_label(&tb_ptr);
- if (tci_compare64(t0, t1, condition)) {
+ tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
+ if (tci_compare64(regs[r0], regs[r1], condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size);
- tb_ptr = (uint8_t *)label;
+ tb_ptr = ptr;
continue;
}
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 25/71] tcg/tci: Split out tci_args_ri and tci_args_rI
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (23 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 24/71] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 26/71] tcg/tci: Reuse tci_args_l for calls Richard Henderson
` (46 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 38 ++++++++++++++++++++++----------------
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index c8df45ce28..cfbe039fa6 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -121,16 +121,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr)
return value;
}
-#if TCG_TARGET_REG_BITS == 64
-/* Read constant (64 bit) from bytecode. */
-static uint64_t tci_read_i64(const uint8_t **tb_ptr)
-{
- uint64_t value = *(const uint64_t *)(*tb_ptr);
- *tb_ptr += sizeof(value);
- return value;
-}
-#endif
-
/* Read indexed register (native size) from bytecode. */
static tcg_target_ulong
tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
@@ -180,6 +170,8 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* tci_args_<arguments>
* where arguments is a sequence of
*
+ * i = immediate (uint32_t)
+ * I = immediate (tcg_target_ulong)
* r = register
* s = signed ldst offset
*/
@@ -196,6 +188,22 @@ static void tci_args_rr(const uint8_t **tb_ptr,
*r1 = tci_read_r(tb_ptr);
}
+static void tci_args_ri(const uint8_t **tb_ptr,
+ TCGReg *r0, tcg_target_ulong *i1)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *i1 = tci_read_i32(tb_ptr);
+}
+
+#if TCG_TARGET_REG_BITS == 64
+static void tci_args_rI(const uint8_t **tb_ptr,
+ TCGReg *r0, tcg_target_ulong *i1)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *i1 = tci_read_i(tb_ptr);
+}
+#endif
+
static void tci_args_rrr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2)
{
@@ -481,9 +489,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
regs[r0] = regs[r1];
break;
case INDEX_op_tci_movi_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_i32(&tb_ptr);
- tci_write_reg(regs, t0, t1);
+ tci_args_ri(&tb_ptr, &r0, &t1);
+ regs[r0] = t1;
break;
/* Load/store operations (32 bit). */
@@ -703,9 +710,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_tci_movi_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_i64(&tb_ptr);
- tci_write_reg(regs, t0, t1);
+ tci_args_rI(&tb_ptr, &r0, &t1);
+ regs[r0] = t1;
break;
/* Load/store operations (64 bit). */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 26/71] tcg/tci: Reuse tci_args_l for calls.
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (24 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 25/71] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 27/71] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
` (45 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index cfbe039fa6..066e27b492 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -435,30 +435,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
switch (opc) {
case INDEX_op_call:
- t0 = tci_read_i(&tb_ptr);
+ tci_args_l(&tb_ptr, &ptr);
tci_tb_ptr = (uintptr_t)tb_ptr;
#if TCG_TARGET_REG_BITS == 32
- tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0),
- tci_read_reg(regs, TCG_REG_R1),
- tci_read_reg(regs, TCG_REG_R2),
- tci_read_reg(regs, TCG_REG_R3),
- tci_read_reg(regs, TCG_REG_R4),
- tci_read_reg(regs, TCG_REG_R5),
- tci_read_reg(regs, TCG_REG_R6),
- tci_read_reg(regs, TCG_REG_R7),
- tci_read_reg(regs, TCG_REG_R8),
- tci_read_reg(regs, TCG_REG_R9),
- tci_read_reg(regs, TCG_REG_R10),
- tci_read_reg(regs, TCG_REG_R11));
+ tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0),
+ tci_read_reg(regs, TCG_REG_R1),
+ tci_read_reg(regs, TCG_REG_R2),
+ tci_read_reg(regs, TCG_REG_R3),
+ tci_read_reg(regs, TCG_REG_R4),
+ tci_read_reg(regs, TCG_REG_R5),
+ tci_read_reg(regs, TCG_REG_R6),
+ tci_read_reg(regs, TCG_REG_R7),
+ tci_read_reg(regs, TCG_REG_R8),
+ tci_read_reg(regs, TCG_REG_R9),
+ tci_read_reg(regs, TCG_REG_R10),
+ tci_read_reg(regs, TCG_REG_R11));
tci_write_reg(regs, TCG_REG_R0, tmp64);
tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32);
#else
- tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0),
- tci_read_reg(regs, TCG_REG_R1),
- tci_read_reg(regs, TCG_REG_R2),
- tci_read_reg(regs, TCG_REG_R3),
- tci_read_reg(regs, TCG_REG_R4),
- tci_read_reg(regs, TCG_REG_R5));
+ tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0),
+ tci_read_reg(regs, TCG_REG_R1),
+ tci_read_reg(regs, TCG_REG_R2),
+ tci_read_reg(regs, TCG_REG_R3),
+ tci_read_reg(regs, TCG_REG_R4),
+ tci_read_reg(regs, TCG_REG_R5));
tci_write_reg(regs, TCG_REG_R0, tmp64);
#endif
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 27/71] tcg/tci: Reuse tci_args_l for exit_tb
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (25 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 26/71] tcg/tci: Reuse tci_args_l for calls Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 28/71] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
` (44 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t.
This reduces the size of the constant on 32-bit hosts.
The assert for label != NULL has to be removed because that
is a valid value for exit_tb.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 13 ++++---------
tcg/tci/tcg-target.c.inc | 2 +-
2 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 066e27b492..6fbbc48ecf 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -160,9 +160,7 @@ tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
{
- tcg_target_ulong label = tci_read_i(tb_ptr);
- tci_assert(label != 0);
- return label;
+ return tci_read_i(tb_ptr);
}
/*
@@ -400,7 +398,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tcg_target_ulong regs[TCG_TARGET_NB_REGS];
long tcg_temps[CPU_TEMP_BUF_NLONGS];
uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
- uintptr_t ret = 0;
regs[TCG_AREG0] = (tcg_target_ulong)env;
regs[TCG_REG_CALL_STACK] = sp_value;
@@ -815,9 +812,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* QEMU specific operations. */
case INDEX_op_exit_tb:
- ret = *(uint64_t *)tb_ptr;
- goto exit;
- break;
+ tci_args_l(&tb_ptr, &ptr);
+ return (uintptr_t)ptr;
+
case INDEX_op_goto_tb:
/* Jump address is aligned */
tb_ptr = QEMU_ALIGN_PTR_UP(tb_ptr, 4);
@@ -975,6 +972,4 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
tci_assert(tb_ptr == old_code_ptr + op_size);
}
-exit:
- return ret;
}
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index c79f9c32d8..ff8040510f 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -401,7 +401,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
switch (opc) {
case INDEX_op_exit_tb:
- tcg_out64(s, args[0]);
+ tcg_out_i(s, args[0]);
break;
case INDEX_op_goto_tb:
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 28/71] tcg/tci: Reuse tci_args_l for goto_tb
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (26 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 27/71] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 29/71] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
` (43 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Convert to indirect jumps, as it's less complicated.
Then we just have a pointer to the tb address at which
the chain is stored, from which we read.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 11 +++--------
tcg/tci.c | 8 +++-----
tcg/tci/tcg-target.c.inc | 13 +++----------
3 files changed, 9 insertions(+), 23 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 9c0021a26f..9285c930a2 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -87,7 +87,7 @@
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_goto_ptr 0
-#define TCG_TARGET_HAS_direct_jump 1
+#define TCG_TARGET_HAS_direct_jump 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
@@ -174,12 +174,7 @@ void tci_disas(uint8_t opc);
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
-static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- uintptr_t jmp_rw, uintptr_t addr)
-{
- /* patch the branch destination */
- qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4));
- /* no need to flush icache explicitly */
-}
+/* not defined -- call should be eliminated at compile time */
+void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
#endif /* TCG_TARGET_H */
diff --git a/tcg/tci.c b/tcg/tci.c
index 6fbbc48ecf..3fe0831b33 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -816,13 +816,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
return (uintptr_t)ptr;
case INDEX_op_goto_tb:
- /* Jump address is aligned */
- tb_ptr = QEMU_ALIGN_PTR_UP(tb_ptr, 4);
- t0 = qatomic_read((int32_t *)tb_ptr);
- tb_ptr += sizeof(int32_t);
+ tci_args_l(&tb_ptr, &ptr);
tci_assert(tb_ptr == old_code_ptr + op_size);
- tb_ptr += (int32_t)t0;
+ tb_ptr = *(void **)ptr;
continue;
+
case INDEX_op_qemu_ld_i32:
t0 = *tb_ptr++;
taddr = tci_read_ulong(regs, &tb_ptr);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index ff8040510f..2c64b4f617 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -405,16 +405,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
case INDEX_op_goto_tb:
- if (s->tb_jmp_insn_offset) {
- /* Direct jump method. */
- /* Align for atomic patching and thread safety */
- s->code_ptr = QEMU_ALIGN_PTR_UP(s->code_ptr, 4);
- s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
- tcg_out32(s, 0);
- } else {
- /* Indirect jump method. */
- TODO();
- }
+ tcg_debug_assert(s->tb_jmp_insn_offset == 0);
+ /* indirect jump method. */
+ tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0]));
set_jmp_reset_offset(s, args[0]);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 29/71] tcg/tci: Split out tci_args_rrrrrr
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (27 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 28/71] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 30/71] tcg/tci: Split out tci_args_rrrr Richard Henderson
` (42 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 31 ++++++++++++++++++++-----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 3fe0831b33..8b38687d9a 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -258,6 +258,17 @@ static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
*r4 = tci_read_r(tb_ptr);
*c5 = tci_read_b(tb_ptr);
}
+
+static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+ TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *r3 = tci_read_r(tb_ptr);
+ *r4 = tci_read_r(tb_ptr);
+ *r5 = tci_read_r(tb_ptr);
+}
#endif
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
@@ -420,7 +431,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
- TCGReg r3, r4;
+ TCGReg r3, r4, r5;
uint64_t T1, T2;
#endif
TCGMemOpIdx oi;
@@ -626,18 +637,16 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
- t0 = *tb_ptr++;
- t1 = *tb_ptr++;
- tmp64 = tci_read_r64(regs, &tb_ptr);
- tmp64 += tci_read_r64(regs, &tb_ptr);
- tci_write_reg64(regs, t1, t0, tmp64);
+ tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
+ T1 = tci_uint64(regs[r3], regs[r2]);
+ T2 = tci_uint64(regs[r5], regs[r4]);
+ tci_write_reg64(regs, r1, r0, T1 + T2);
break;
case INDEX_op_sub2_i32:
- t0 = *tb_ptr++;
- t1 = *tb_ptr++;
- tmp64 = tci_read_r64(regs, &tb_ptr);
- tmp64 -= tci_read_r64(regs, &tb_ptr);
- tci_write_reg64(regs, t1, t0, tmp64);
+ tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
+ T1 = tci_uint64(regs[r3], regs[r2]);
+ T2 = tci_uint64(regs[r5], regs[r4]);
+ tci_write_reg64(regs, r1, r0, T1 - T2);
break;
case INDEX_op_brcond2_i32:
tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr);
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 30/71] tcg/tci: Split out tci_args_rrrr
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (28 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 29/71] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 31/71] tcg/tci: Clean up deposit operations Richard Henderson
` (41 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 8b38687d9a..10f58e4f25 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -237,6 +237,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
}
#if TCG_TARGET_REG_BITS == 32
+static void tci_args_rrrr(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *r3 = tci_read_r(tb_ptr);
+}
+
static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5)
{
@@ -659,11 +668,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
break;
case INDEX_op_mulu2_i32:
- t0 = *tb_ptr++;
- t1 = *tb_ptr++;
- t2 = tci_read_rval(regs, &tb_ptr);
- tmp64 = (uint32_t)tci_read_rval(regs, &tb_ptr);
- tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
+ tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
+ tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 31/71] tcg/tci: Clean up deposit operations
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (29 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 30/71] tcg/tci: Split out tci_args_rrrr Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 32/71] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
` (40 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Use the correct set of asserts during code generation.
We do not require the first input to overlap the output;
the existing interpreter already supported that.
Split out tci_args_rrrbb in the translator.
Use the deposit32/64 functions rather than inline expansion.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target-con-set.h | 1 -
tcg/tci.c | 33 ++++++++++++++++-----------------
tcg/tci/tcg-target.c.inc | 24 ++++++++++++++----------
3 files changed, 30 insertions(+), 28 deletions(-)
diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
index f51b7bcb13..316730f32c 100644
--- a/tcg/tci/tcg-target-con-set.h
+++ b/tcg/tci/tcg-target-con-set.h
@@ -13,7 +13,6 @@ C_O0_I2(r, r)
C_O0_I3(r, r, r)
C_O0_I4(r, r, r, r)
C_O1_I1(r, r)
-C_O1_I2(r, 0, r)
C_O1_I2(r, r, r)
C_O1_I4(r, r, r, r, r)
C_O2_I1(r, r, r)
diff --git a/tcg/tci.c b/tcg/tci.c
index 10f58e4f25..3ce2b72316 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -168,6 +168,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* tci_args_<arguments>
* where arguments is a sequence of
*
+ * b = immediate (bit position)
* i = immediate (uint32_t)
* I = immediate (tcg_target_ulong)
* r = register
@@ -236,6 +237,16 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
*c3 = tci_read_b(tb_ptr);
}
+static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+ TCGReg *r2, uint8_t *i3, uint8_t *i4)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *i3 = tci_read_b(tb_ptr);
+ *i4 = tci_read_b(tb_ptr);
+}
+
#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
@@ -432,11 +443,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
TCGReg r0, r1, r2;
tcg_target_ulong t0;
tcg_target_ulong t1;
- tcg_target_ulong t2;
TCGCond condition;
target_ulong taddr;
- uint8_t tmp8;
- uint16_t tmp16;
+ uint8_t pos, len;
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
@@ -627,13 +636,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
#if TCG_TARGET_HAS_deposit_i32
case INDEX_op_deposit_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tmp16 = *tb_ptr++;
- tmp8 = *tb_ptr++;
- tmp32 = (((1 << tmp8) - 1) << tmp16);
- tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
+ tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
+ regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
break;
#endif
case INDEX_op_brcond_i32:
@@ -789,13 +793,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
#if TCG_TARGET_HAS_deposit_i64
case INDEX_op_deposit_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tmp16 = *tb_ptr++;
- tmp8 = *tb_ptr++;
- tmp64 = (((1ULL << tmp8) - 1) << tmp16);
- tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
+ tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
+ regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
break;
#endif
case INDEX_op_brcond_i64:
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 2c64b4f617..640407b4a8 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -126,11 +126,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_rotr_i64:
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
- return C_O1_I2(r, r, r);
-
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- return C_O1_I2(r, 0, r);
+ return C_O1_I2(r, r, r);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
@@ -480,13 +478,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_debug_assert(args[3] <= UINT8_MAX);
- tcg_out8(s, args[3]);
- tcg_debug_assert(args[4] <= UINT8_MAX);
- tcg_out8(s, args[4]);
+ {
+ TCGArg pos = args[3], len = args[4];
+ TCGArg max = opc == INDEX_op_deposit_i32 ? 32 : 64;
+
+ tcg_debug_assert(pos < max);
+ tcg_debug_assert(pos + len <= max);
+
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ tcg_out_r(s, args[2]);
+ tcg_out8(s, pos);
+ tcg_out8(s, len);
+ }
break;
CASE_32_64(brcond)
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 32/71] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (30 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 31/71] tcg/tci: Clean up deposit operations Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 33/71] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Richard Henderson
` (39 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
We are currently using the "natural" size routine, which
uses 64-bits on a 64-bit host. The TCGMemOpIdx operand
has 11 bits, so we can safely reduce to 32-bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 8 ++++----
tcg/tci/tcg-target.c.inc | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 3ce2b72316..583059f319 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -838,7 +838,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_qemu_ld_i32:
t0 = *tb_ptr++;
taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i(&tb_ptr);
+ oi = tci_read_i32(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
tmp32 = qemu_ld_ub;
@@ -875,7 +875,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t1 = *tb_ptr++;
}
taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i(&tb_ptr);
+ oi = tci_read_i32(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
tmp64 = qemu_ld_ub;
@@ -924,7 +924,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_qemu_st_i32:
t0 = tci_read_rval(regs, &tb_ptr);
taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i(&tb_ptr);
+ oi = tci_read_i32(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
qemu_st_b(t0);
@@ -948,7 +948,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_qemu_st_i64:
tmp64 = tci_read_r64(regs, &tb_ptr);
taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i(&tb_ptr);
+ oi = tci_read_i32(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
qemu_st_b(tmp64);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 640407b4a8..6c187a25cc 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -550,7 +550,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
tcg_out_r(s, *args++);
}
- tcg_out_i(s, *args++);
+ tcg_out32(s, *args++);
break;
case INDEX_op_qemu_ld_i64:
@@ -563,7 +563,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
tcg_out_r(s, *args++);
}
- tcg_out_i(s, *args++);
+ tcg_out32(s, *args++);
break;
case INDEX_op_mb:
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 33/71] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm}
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (31 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 32/71] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:19 ` [PATCH v4 34/71] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
` (38 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 147 ++++++++++++++++++++++++++++++------------------------
1 file changed, 81 insertions(+), 66 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 583059f319..f6cc5a3ab0 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -66,22 +66,18 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
regs[index] = value;
}
-#if TCG_TARGET_REG_BITS == 32
static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
uint32_t low_index, uint64_t value)
{
tci_write_reg(regs, low_index, value);
tci_write_reg(regs, high_index, value >> 32);
}
-#endif
-#if TCG_TARGET_REG_BITS == 32
/* Create a 64 bit value from two 32 bit values. */
static uint64_t tci_uint64(uint32_t high, uint32_t low)
{
return ((uint64_t)high << 32) + low;
}
-#endif
/* Read constant byte from bytecode. */
static uint8_t tci_read_b(const uint8_t **tb_ptr)
@@ -121,43 +117,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr)
return value;
}
-/* Read indexed register (native size) from bytecode. */
-static tcg_target_ulong
-tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
-{
- tcg_target_ulong value = tci_read_reg(regs, **tb_ptr);
- *tb_ptr += 1;
- return value;
-}
-
-#if TCG_TARGET_REG_BITS == 32
-/* Read two indexed registers (2 * 32 bit) from bytecode. */
-static uint64_t tci_read_r64(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- uint32_t low = tci_read_rval(regs, tb_ptr);
- return tci_uint64(tci_read_rval(regs, tb_ptr), low);
-}
-#elif TCG_TARGET_REG_BITS == 64
-/* Read indexed register (64 bit) from bytecode. */
-static uint64_t tci_read_r64(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- return tci_read_rval(regs, tb_ptr);
-}
-#endif
-
-/* Read indexed register(s) with target address from bytecode. */
-static target_ulong
-tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
-{
- target_ulong taddr = tci_read_rval(regs, tb_ptr);
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
- taddr += (uint64_t)tci_read_rval(regs, tb_ptr) << 32;
-#endif
- return taddr;
-}
-
static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
{
return tci_read_i(tb_ptr);
@@ -171,6 +130,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* b = immediate (bit position)
* i = immediate (uint32_t)
* I = immediate (tcg_target_ulong)
+ * m = immediate (TCGMemOpIdx)
* r = register
* s = signed ldst offset
*/
@@ -203,6 +163,14 @@ static void tci_args_rI(const uint8_t **tb_ptr,
}
#endif
+static void tci_args_rrm(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *m2 = tci_read_i32(tb_ptr);
+}
+
static void tci_args_rrr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2)
{
@@ -237,6 +205,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
*c3 = tci_read_b(tb_ptr);
}
+static void tci_args_rrrm(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *m3 = tci_read_i32(tb_ptr);
+}
+
static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, uint8_t *i3, uint8_t *i4)
{
@@ -247,6 +224,16 @@ static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
*i4 = tci_read_b(tb_ptr);
}
+static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+ TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *r3 = tci_read_r(tb_ptr);
+ *m4 = tci_read_i32(tb_ptr);
+}
+
#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
@@ -440,8 +427,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint8_t op_size = tb_ptr[1];
const uint8_t *old_code_ptr = tb_ptr;
#endif
- TCGReg r0, r1, r2;
- tcg_target_ulong t0;
+ TCGReg r0, r1, r2, r3;
tcg_target_ulong t1;
TCGCond condition;
target_ulong taddr;
@@ -449,7 +435,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
- TCGReg r3, r4, r5;
+ TCGReg r4, r5;
uint64_t T1, T2;
#endif
TCGMemOpIdx oi;
@@ -836,9 +822,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
continue;
case INDEX_op_qemu_ld_i32:
- t0 = *tb_ptr++;
- taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i32(&tb_ptr);
+ if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
+ tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ taddr = regs[r1];
+ } else {
+ tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ taddr = tci_uint64(regs[r2], regs[r1]);
+ }
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
tmp32 = qemu_ld_ub;
@@ -867,15 +857,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
default:
g_assert_not_reached();
}
- tci_write_reg(regs, t0, tmp32);
+ regs[r0] = tmp32;
break;
+
case INDEX_op_qemu_ld_i64:
- t0 = *tb_ptr++;
- if (TCG_TARGET_REG_BITS == 32) {
- t1 = *tb_ptr++;
+ if (TCG_TARGET_REG_BITS == 64) {
+ tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ taddr = regs[r1];
+ } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
+ tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ taddr = regs[r2];
+ } else {
+ tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
+ taddr = tci_uint64(regs[r3], regs[r2]);
}
- taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i32(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
tmp64 = qemu_ld_ub;
@@ -916,39 +911,58 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
default:
g_assert_not_reached();
}
- tci_write_reg(regs, t0, tmp64);
if (TCG_TARGET_REG_BITS == 32) {
- tci_write_reg(regs, t1, tmp64 >> 32);
+ tci_write_reg64(regs, r1, r0, tmp64);
+ } else {
+ regs[r0] = tmp64;
}
break;
+
case INDEX_op_qemu_st_i32:
- t0 = tci_read_rval(regs, &tb_ptr);
- taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i32(&tb_ptr);
+ if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
+ tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ taddr = regs[r1];
+ } else {
+ tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ taddr = tci_uint64(regs[r2], regs[r1]);
+ }
+ tmp32 = regs[r0];
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
- qemu_st_b(t0);
+ qemu_st_b(tmp32);
break;
case MO_LEUW:
- qemu_st_lew(t0);
+ qemu_st_lew(tmp32);
break;
case MO_LEUL:
- qemu_st_lel(t0);
+ qemu_st_lel(tmp32);
break;
case MO_BEUW:
- qemu_st_bew(t0);
+ qemu_st_bew(tmp32);
break;
case MO_BEUL:
- qemu_st_bel(t0);
+ qemu_st_bel(tmp32);
break;
default:
g_assert_not_reached();
}
break;
+
case INDEX_op_qemu_st_i64:
- tmp64 = tci_read_r64(regs, &tb_ptr);
- taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i32(&tb_ptr);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ taddr = regs[r1];
+ tmp64 = regs[r0];
+ } else {
+ if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
+ tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ taddr = regs[r2];
+ } else {
+ tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
+ taddr = tci_uint64(regs[r3], regs[r2]);
+ }
+ tmp64 = tci_uint64(regs[r1], regs[r0]);
+ }
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
qemu_st_b(tmp64);
@@ -975,6 +989,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
g_assert_not_reached();
}
break;
+
case INDEX_op_mb:
/* Ensure ordering for all kinds */
smp_mb();
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 34/71] tcg/tci: Hoist op_size checking into tci_args_*
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (32 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 33/71] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Richard Henderson
@ 2021-02-17 20:19 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 35/71] tcg/tci: Remove tci_disas Richard Henderson
` (37 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:19 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
This performs the size check while reading the arguments,
which means that we don't have to arrange for it to be
done after the operation. Which tidies all of the branches.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 73 insertions(+), 14 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index f6cc5a3ab0..6b63beea28 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -24,7 +24,7 @@
#if defined(CONFIG_DEBUG_TCG)
# define tci_assert(cond) assert(cond)
#else
-# define tci_assert(cond) ((void)0)
+# define tci_assert(cond) ((void)(cond))
#endif
#include "qemu-common.h"
@@ -135,146 +135,217 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* s = signed ldst offset
*/
+static void check_size(const uint8_t *start, const uint8_t **tb_ptr)
+{
+ const uint8_t *old_code_ptr = start - 2;
+ uint8_t op_size = old_code_ptr[1];
+ tci_assert(*tb_ptr == old_code_ptr + op_size);
+}
+
static void tci_args_l(const uint8_t **tb_ptr, void **l0)
{
+ const uint8_t *start = *tb_ptr;
+
*l0 = (void *)tci_read_label(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_ri(const uint8_t **tb_ptr,
TCGReg *r0, tcg_target_ulong *i1)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*i1 = tci_read_i32(tb_ptr);
+
+ check_size(start, tb_ptr);
}
#if TCG_TARGET_REG_BITS == 64
static void tci_args_rI(const uint8_t **tb_ptr,
TCGReg *r0, tcg_target_ulong *i1)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*i1 = tci_read_i(tb_ptr);
+
+ check_size(start, tb_ptr);
}
#endif
static void tci_args_rrm(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*m2 = tci_read_i32(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rrr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rrs(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, int32_t *i2)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*i2 = tci_read_s32(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rrcl(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*c2 = tci_read_b(tb_ptr);
*l3 = (void *)tci_read_label(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rrrc(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*c3 = tci_read_b(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rrrm(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*m3 = tci_read_i32(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, uint8_t *i3, uint8_t *i4)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*i3 = tci_read_b(tb_ptr);
*i4 = tci_read_b(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*r3 = tci_read_r(tb_ptr);
*m4 = tci_read_i32(tb_ptr);
+
+ check_size(start, tb_ptr);
}
#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*r3 = tci_read_r(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*r3 = tci_read_r(tb_ptr);
*c4 = tci_read_b(tb_ptr);
*l5 = (void *)tci_read_label(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*r3 = tci_read_r(tb_ptr);
*r4 = tci_read_r(tb_ptr);
*c5 = tci_read_b(tb_ptr);
+
+ check_size(start, tb_ptr);
}
static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
{
+ const uint8_t *start = *tb_ptr;
+
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*r3 = tci_read_r(tb_ptr);
*r4 = tci_read_r(tb_ptr);
*r5 = tci_read_r(tb_ptr);
+
+ check_size(start, tb_ptr);
}
#endif
@@ -423,10 +494,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
for (;;) {
TCGOpcode opc = tb_ptr[0];
-#if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
- uint8_t op_size = tb_ptr[1];
- const uint8_t *old_code_ptr = tb_ptr;
-#endif
TCGReg r0, r1, r2, r3;
tcg_target_ulong t1;
TCGCond condition;
@@ -476,7 +543,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
case INDEX_op_br:
tci_args_l(&tb_ptr, &ptr);
- tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = ptr;
continue;
case INDEX_op_setcond_i32:
@@ -629,9 +695,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_brcond_i32:
tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
if (tci_compare32(regs[r0], regs[r1], condition)) {
- tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = ptr;
- continue;
}
break;
#if TCG_TARGET_REG_BITS == 32
@@ -652,7 +716,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
T1 = tci_uint64(regs[r1], regs[r0]);
T2 = tci_uint64(regs[r3], regs[r2]);
if (tci_compare64(T1, T2, condition)) {
- tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = ptr;
continue;
}
@@ -786,9 +849,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_brcond_i64:
tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
if (tci_compare64(regs[r0], regs[r1], condition)) {
- tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = ptr;
- continue;
}
break;
case INDEX_op_ext32s_i64:
@@ -817,9 +878,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_goto_tb:
tci_args_l(&tb_ptr, &ptr);
- tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = *(void **)ptr;
- continue;
+ break;
case INDEX_op_qemu_ld_i32:
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
@@ -997,6 +1057,5 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
default:
g_assert_not_reached();
}
- tci_assert(tb_ptr == old_code_ptr + op_size);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 35/71] tcg/tci: Remove tci_disas
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (33 preceding siblings ...)
2021-02-17 20:19 ` [PATCH v4 34/71] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 36/71] tcg/tci: Implement the disassembler properly Richard Henderson
` (36 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
This function is unused. It's not even the disassembler,
which is print_insn_tci, located in disas/tci.c.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 2 --
tcg/tci/tcg-target.c.inc | 10 ----------
2 files changed, 12 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 9285c930a2..52af6d8bc5 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -163,8 +163,6 @@ typedef enum {
#define TCG_TARGET_CALL_STACK_OFFSET 0
#define TCG_TARGET_STACK_ALIGN 16
-void tci_disas(uint8_t opc);
-
#define HAVE_TCG_QEMU_TB_EXEC
/* We could notice __i386__ or __s390x__ and reduce the barriers depending
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 6c187a25cc..7fb3b04eaf 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -253,16 +253,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
return true;
}
-#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
-/* Show current bytecode. Used by tcg interpreter. */
-void tci_disas(uint8_t opc)
-{
- const TCGOpDef *def = &tcg_op_defs[opc];
- fprintf(stderr, "TCG %s %u, %u, %u\n",
- def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs);
-}
-#endif
-
/* Write value (native size). */
static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 36/71] tcg/tci: Implement the disassembler properly
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (34 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 35/71] tcg/tci: Remove tci_disas Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 37/71] tcg: Build ffi data structures for helpers Richard Henderson
` (35 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Actually print arguments as opposed to simply the opcodes
and, uselessly, the argument counts. Reuse all of the helpers
developed as part of the interpreter.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
meson.build | 2 +-
include/tcg/tcg-opc.h | 2 -
disas/tci.c | 61 ---------
tcg/tci.c | 283 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 284 insertions(+), 64 deletions(-)
delete mode 100644 disas/tci.c
diff --git a/meson.build b/meson.build
index a923f249d8..da225d68a7 100644
--- a/meson.build
+++ b/meson.build
@@ -1925,7 +1925,7 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files(
'tcg/tcg-op.c',
'tcg/tcg.c',
))
-specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('disas/tci.c', 'tcg/tci.c'))
+specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'))
subdir('backends')
subdir('disas')
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 900984c005..bbb0884af8 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -278,10 +278,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
#ifdef TCG_TARGET_INTERPRETER
/* These opcodes are only for use between the tci generator and interpreter. */
DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
-#if TCG_TARGET_REG_BITS == 64
DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
#endif
-#endif
#undef TLADDR_ARGS
#undef DATA64_ARGS
diff --git a/disas/tci.c b/disas/tci.c
deleted file mode 100644
index f1d6c6b469..0000000000
--- a/disas/tci.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Tiny Code Interpreter for QEMU - disassembler
- *
- * Copyright (c) 2011 Stefan Weil
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "qemu-common.h"
-#include "disas/dis-asm.h"
-#include "tcg/tcg.h"
-
-/* Disassemble TCI bytecode. */
-int print_insn_tci(bfd_vma addr, disassemble_info *info)
-{
- int length;
- uint8_t byte;
- int status;
- TCGOpcode op;
-
- status = info->read_memory_func(addr, &byte, 1, info);
- if (status != 0) {
- info->memory_error_func(status, addr, info);
- return -1;
- }
- op = byte;
-
- addr++;
- status = info->read_memory_func(addr, &byte, 1, info);
- if (status != 0) {
- info->memory_error_func(status, addr, info);
- return -1;
- }
- length = byte;
-
- if (op >= tcg_op_defs_max) {
- info->fprintf_func(info->stream, "illegal opcode %d", op);
- } else {
- const TCGOpDef *def = &tcg_op_defs[op];
- int nb_oargs = def->nb_oargs;
- int nb_iargs = def->nb_iargs;
- int nb_cargs = def->nb_cargs;
- /* TODO: Improve disassembler output. */
- info->fprintf_func(info->stream, "%s\to=%d i=%d c=%d",
- def->name, nb_oargs, nb_iargs, nb_cargs);
- }
-
- return length;
-}
diff --git a/tcg/tci.c b/tcg/tci.c
index 6b63beea28..41d73edc3a 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -1059,3 +1059,286 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
}
}
+
+/*
+ * Disassembler that matches the interpreter
+ */
+
+static const char *str_r(TCGReg r)
+{
+ static const char regs[TCG_TARGET_NB_REGS][4] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp"
+ };
+
+ QEMU_BUILD_BUG_ON(TCG_AREG0 != TCG_REG_R14);
+ QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK != TCG_REG_R15);
+
+ assert((unsigned)r < TCG_TARGET_NB_REGS);
+ return regs[r];
+}
+
+static const char *str_c(TCGCond c)
+{
+ static const char cond[16][8] = {
+ [TCG_COND_NEVER] = "never",
+ [TCG_COND_ALWAYS] = "always",
+ [TCG_COND_EQ] = "eq",
+ [TCG_COND_NE] = "ne",
+ [TCG_COND_LT] = "lt",
+ [TCG_COND_GE] = "ge",
+ [TCG_COND_LE] = "le",
+ [TCG_COND_GT] = "gt",
+ [TCG_COND_LTU] = "ltu",
+ [TCG_COND_GEU] = "geu",
+ [TCG_COND_LEU] = "leu",
+ [TCG_COND_GTU] = "gtu",
+ };
+
+ assert((unsigned)c < ARRAY_SIZE(cond));
+ assert(cond[c][0] != 0);
+ return cond[c];
+}
+
+/* Disassemble TCI bytecode. */
+int print_insn_tci(bfd_vma addr, disassemble_info *info)
+{
+ uint8_t buf[256];
+ int length, status;
+ const TCGOpDef *def;
+ const char *op_name;
+ TCGOpcode op;
+ TCGReg r0, r1, r2, r3;
+#if TCG_TARGET_REG_BITS == 32
+ TCGReg r4, r5;
+#endif
+ tcg_target_ulong i1;
+ int32_t s2;
+ TCGCond c;
+ TCGMemOpIdx oi;
+ uint8_t pos, len;
+ void *ptr;
+ const uint8_t *tb_ptr;
+
+ status = info->read_memory_func(addr, buf, 2, info);
+ if (status != 0) {
+ info->memory_error_func(status, addr, info);
+ return -1;
+ }
+ op = buf[0];
+ length = buf[1];
+
+ if (length < 2) {
+ info->fprintf_func(info->stream, "invalid length %d", length);
+ return 1;
+ }
+
+ status = info->read_memory_func(addr + 2, buf + 2, length - 2, info);
+ if (status != 0) {
+ info->memory_error_func(status, addr + 2, info);
+ return -1;
+ }
+
+ def = &tcg_op_defs[op];
+ op_name = def->name;
+ tb_ptr = buf + 2;
+
+ switch (op) {
+ case INDEX_op_br:
+ case INDEX_op_call:
+ case INDEX_op_exit_tb:
+ case INDEX_op_goto_tb:
+ tci_args_l(&tb_ptr, &ptr);
+ info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
+ break;
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s,%p",
+ op_name, str_r(r0), str_r(r1), str_c(c), ptr);
+ break;
+
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s",
+ op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c));
+ break;
+
+ case INDEX_op_tci_movi_i32:
+ tci_args_ri(&tb_ptr, &r0, &i1);
+ info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "",
+ op_name, str_r(r0), i1);
+ break;
+
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_tci_movi_i64:
+ tci_args_rI(&tb_ptr, &r0, &i1);
+ info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "",
+ op_name, str_r(r0), i1);
+ break;
+#endif
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld_i64:
+ case INDEX_op_st8_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i32:
+ case INDEX_op_st_i64:
+ tci_args_rrs(&tb_ptr, &r0, &r1, &s2);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%d",
+ op_name, str_r(r0), str_r(r1), s2);
+ break;
+
+ case INDEX_op_mov_i32:
+ case INDEX_op_mov_i64:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ case INDEX_op_neg_i32:
+ case INDEX_op_neg_i64:
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ info->fprintf_func(info->stream, "%-12s %s,%s",
+ op_name, str_r(r0), str_r(r1));
+ break;
+
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ case INDEX_op_mul_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ case INDEX_op_div_i32:
+ case INDEX_op_div_i64:
+ case INDEX_op_rem_i32:
+ case INDEX_op_rem_i64:
+ case INDEX_op_divu_i32:
+ case INDEX_op_divu_i64:
+ case INDEX_op_remu_i32:
+ case INDEX_op_remu_i64:
+ case INDEX_op_shl_i32:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i32:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i32:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotr_i64:
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s",
+ op_name, str_r(r0), str_r(r1), str_r(r2));
+ break;
+
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s,%d,%d",
+ op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
+ break;
+
+#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_setcond2_i32:
+ tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s",
+ op_name, str_r(r0), str_r(r1), str_r(r2),
+ str_r(r3), str_r(r4), str_c(c));
+ break;
+
+ case INDEX_op_brcond2_i32:
+ tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%p",
+ op_name, str_r(r0), str_r(r1),
+ str_r(r2), str_r(r3), str_c(c), ptr);
+ break;
+
+ case INDEX_op_mulu2_i32:
+ tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s",
+ op_name, str_r(r0), str_r(r1),
+ str_r(r2), str_r(r3));
+ break;
+
+ case INDEX_op_add2_i32:
+ case INDEX_op_sub2_i32:
+ tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s",
+ op_name, str_r(r0), str_r(r1), str_r(r2),
+ str_r(r3), str_r(r4), str_r(r5));
+ break;
+#endif
+
+ case INDEX_op_qemu_ld_i64:
+ case INDEX_op_qemu_st_i64:
+ len = DIV_ROUND_UP(64, TCG_TARGET_REG_BITS);
+ goto do_qemu_ldst;
+ case INDEX_op_qemu_ld_i32:
+ case INDEX_op_qemu_st_i32:
+ len = 1;
+ do_qemu_ldst:
+ len += DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS);
+ switch (len) {
+ case 2:
+ tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%x",
+ op_name, str_r(r0), str_r(r1), oi);
+ break;
+ case 3:
+ tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s,%x",
+ op_name, str_r(r0), str_r(r1), str_r(r2), oi);
+ break;
+ case 4:
+ tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%x",
+ op_name, str_r(r0), str_r(r1),
+ str_r(r2), str_r(r3), oi);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ default:
+ info->fprintf_func(info->stream, "illegal opcode %d", op);
+ break;
+ }
+
+ return length;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 37/71] tcg: Build ffi data structures for helpers
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (35 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 36/71] tcg/tci: Implement the disassembler properly Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 38/71] tcg/tci: Use ffi for calls Richard Henderson
` (34 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
We will shortly use libffi for tci, as that is the only
portable way of calling arbitrary functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
meson.build | 9 +-
include/exec/helper-ffi.h | 115 +++++++++++++++++++++++++
include/exec/helper-tcg.h | 24 ++++--
target/hppa/helper.h | 2 +
| 6 ++
target/m68k/helper.h | 1 +
target/ppc/helper.h | 3 +
tcg/tcg.c | 20 +++++
tests/docker/dockerfiles/fedora.docker | 1 +
9 files changed, 172 insertions(+), 9 deletions(-)
create mode 100644 include/exec/helper-ffi.h
diff --git a/meson.build b/meson.build
index da225d68a7..6d5d1b914b 100644
--- a/meson.build
+++ b/meson.build
@@ -1925,7 +1925,14 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files(
'tcg/tcg-op.c',
'tcg/tcg.c',
))
-specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'))
+
+if get_option('tcg_interpreter')
+ libffi = dependency('libffi', version: '>=3.0',
+ static: enable_static, method: 'pkg-config',
+ required: true)
+ specific_ss.add(libffi)
+ specific_ss.add(files('tcg/tci.c'))
+endif
subdir('backends')
subdir('disas')
diff --git a/include/exec/helper-ffi.h b/include/exec/helper-ffi.h
new file mode 100644
index 0000000000..3af1065af3
--- /dev/null
+++ b/include/exec/helper-ffi.h
@@ -0,0 +1,115 @@
+/*
+ * Helper file for declaring TCG helper functions.
+ * This one defines data structures private to tcg.c.
+ */
+
+#ifndef HELPER_FFI_H
+#define HELPER_FFI_H 1
+
+#include "exec/helper-head.h"
+
+#define dh_ffitype_i32 &ffi_type_uint32
+#define dh_ffitype_s32 &ffi_type_sint32
+#define dh_ffitype_int &ffi_type_sint
+#define dh_ffitype_i64 &ffi_type_uint64
+#define dh_ffitype_s64 &ffi_type_sint64
+#define dh_ffitype_f16 &ffi_type_uint32
+#define dh_ffitype_f32 &ffi_type_uint32
+#define dh_ffitype_f64 &ffi_type_uint64
+#ifdef TARGET_LONG_BITS
+# if TARGET_LONG_BITS == 32
+# define dh_ffitype_tl &ffi_type_uint32
+# else
+# define dh_ffitype_tl &ffi_type_uint64
+# endif
+#endif
+#define dh_ffitype_ptr &ffi_type_pointer
+#define dh_ffitype_cptr &ffi_type_pointer
+#define dh_ffitype_void &ffi_type_void
+#define dh_ffitype_noreturn &ffi_type_void
+#define dh_ffitype_env &ffi_type_pointer
+#define dh_ffitype(t) glue(dh_ffitype_, t)
+
+#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 0, \
+ };
+
+#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \
+ static ffi_type *glue(cif_args_,NAME)[1] = { dh_ffitype(t1) }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 1, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
+
+#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \
+ static ffi_type *glue(cif_args_,NAME)[2] = { \
+ dh_ffitype(t1), dh_ffitype(t2) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 2, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
+
+#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \
+ static ffi_type *glue(cif_args_,NAME)[3] = { \
+ dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 3, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
+
+#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \
+ static ffi_type *glue(cif_args_,NAME)[4] = { \
+ dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), dh_ffitype(t4) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 4, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
+
+#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \
+ static ffi_type *glue(cif_args_,NAME)[5] = { \
+ dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \
+ dh_ffitype(t4), dh_ffitype(t5) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 5, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
+
+#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \
+ static ffi_type *glue(cif_args_,NAME)[6] = { \
+ dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \
+ dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 6, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
+
+#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
+ static ffi_type *glue(cif_args_,NAME)[7] = { \
+ dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \
+ dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6), dh_ffitype(t7) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 7, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
+
+#include "helper.h"
+#include "trace/generated-helpers.h"
+#include "tcg-runtime.h"
+
+#undef DEF_HELPER_FLAGS_0
+#undef DEF_HELPER_FLAGS_1
+#undef DEF_HELPER_FLAGS_2
+#undef DEF_HELPER_FLAGS_3
+#undef DEF_HELPER_FLAGS_4
+#undef DEF_HELPER_FLAGS_5
+#undef DEF_HELPER_FLAGS_6
+#undef DEF_HELPER_FLAGS_7
+
+#endif /* HELPER_FFI_H */
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
index 27870509a2..a71b848576 100644
--- a/include/exec/helper-tcg.h
+++ b/include/exec/helper-tcg.h
@@ -10,50 +10,57 @@
to get all the macros expanded first. */
#define str(s) #s
+#ifdef CONFIG_TCG_INTERPRETER
+# define DO_CIF(NAME) .cif = &cif_##NAME,
+#else
+# define DO_CIF(NAME)
+#endif
+
#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \
- { .func = HELPER(NAME), .name = str(NAME), \
+ { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) },
#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \
- { .func = HELPER(NAME), .name = str(NAME), \
+ { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) },
#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \
- { .func = HELPER(NAME), .name = str(NAME), \
+ { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) },
#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \
- { .func = HELPER(NAME), .name = str(NAME), \
+ { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) },
#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \
- { .func = HELPER(NAME), .name = str(NAME), \
+ { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) },
#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \
- { .func = HELPER(NAME), .name = str(NAME), \
+ { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
| dh_sizemask(t5, 5) },
#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \
- { .func = HELPER(NAME), .name = str(NAME), \
+ { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) },
#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
- { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
+ { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \
+ .flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) },
@@ -64,6 +71,7 @@
#include "plugin-helpers.h"
#undef str
+#undef DO_CIF
#undef DEF_HELPER_FLAGS_0
#undef DEF_HELPER_FLAGS_1
#undef DEF_HELPER_FLAGS_2
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 2d483aab58..35c612f09d 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -1,9 +1,11 @@
#if TARGET_REGISTER_BITS == 64
# define dh_alias_tr i64
# define dh_is_64bit_tr 1
+# define dh_ffitype_tr dh_ffitype_i64
#else
# define dh_alias_tr i32
# define dh_is_64bit_tr 0
+# define dh_ffitype_tr dh_ffitype_i32
#endif
#define dh_ctype_tr target_ureg
#define dh_is_signed_tr 0
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 6c0c849347..cae50f77eb 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -27,13 +27,19 @@
#define dh_alias_Reg ptr
#define dh_alias_ZMMReg ptr
#define dh_alias_MMXReg ptr
+
#define dh_ctype_Reg Reg *
#define dh_ctype_ZMMReg ZMMReg *
#define dh_ctype_MMXReg MMXReg *
+
#define dh_is_signed_Reg dh_is_signed_ptr
#define dh_is_signed_ZMMReg dh_is_signed_ptr
#define dh_is_signed_MMXReg dh_is_signed_ptr
+#define dh_ffitype_Reg dh_ffitype_ptr
+#define dh_ffitype_ZMMReg dh_ffitype_ptr
+#define dh_ffitype_MMXReg dh_ffitype_ptr
+
DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(psllw, SUFFIX), void, env, Reg, Reg)
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index 77808497a9..672c99d5de 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -18,6 +18,7 @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32)
#define dh_alias_fp ptr
#define dh_ctype_fp FPReg *
#define dh_is_signed_fp dh_is_signed_ptr
+#define dh_ffitype_fp dh_ffitype_ptr
DEF_HELPER_3(exts32, void, env, fp, s32)
DEF_HELPER_3(extf32, void, env, fp, f32)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6a4dccf70c..bbd4700064 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -108,10 +108,12 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
#define dh_alias_avr ptr
#define dh_ctype_avr ppc_avr_t *
#define dh_is_signed_avr dh_is_signed_ptr
+#define dh_ffitype_avr dh_ffitype_ptr
#define dh_alias_vsr ptr
#define dh_ctype_vsr ppc_vsr_t *
#define dh_is_signed_vsr dh_is_signed_ptr
+#define dh_ffitype_vsr dh_ffitype_ptr
DEF_HELPER_3(vavgub, void, avr, avr, avr)
DEF_HELPER_3(vavguh, void, avr, avr, avr)
@@ -696,6 +698,7 @@ DEF_HELPER_3(store_601_batu, void, env, i32, tl)
#define dh_alias_fprp ptr
#define dh_ctype_fprp ppc_fprp_t *
#define dh_is_signed_fprp dh_is_signed_ptr
+#define dh_ffitype_fprp dh_ffitype_ptr
DEF_HELPER_4(dadd, void, env, fprp, fprp, fprp)
DEF_HELPER_4(daddq, void, env, fprp, fprp, fprp)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 2991112829..6382112215 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -66,6 +66,10 @@
#include "exec/log.h"
#include "sysemu/sysemu.h"
+#ifdef CONFIG_TCG_INTERPRETER
+#include <ffi.h>
+#endif
+
/* Forward declarations for functions declared in tcg-target.c.inc and
used here. */
static void tcg_target_init(TCGContext *s);
@@ -1082,6 +1086,9 @@ void tcg_pool_reset(TCGContext *s)
typedef struct TCGHelperInfo {
void *func;
+#ifdef CONFIG_TCG_INTERPRETER
+ ffi_cif *cif;
+#endif
const char *name;
unsigned flags;
unsigned sizemask;
@@ -1089,6 +1096,10 @@ typedef struct TCGHelperInfo {
#include "exec/helper-proto.h"
+#ifdef CONFIG_TCG_INTERPRETER
+#include "exec/helper-ffi.h"
+#endif
+
static const TCGHelperInfo all_helpers[] = {
#include "exec/helper-tcg.h"
};
@@ -1136,6 +1147,15 @@ void tcg_context_init(TCGContext *s)
(gpointer)&all_helpers[i]);
}
+#ifdef CONFIG_TCG_INTERPRETER
+ for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) {
+ ffi_cif *cif = all_helpers[i].cif;
+ ffi_status ok = ffi_prep_cif(cif, FFI_DEFAULT_ABI, cif->nargs,
+ cif->rtype, cif->arg_types);
+ tcg_debug_assert(ok == FFI_OK);
+ }
+#endif
+
tcg_target_init(s);
process_op_defs(s);
diff --git a/tests/docker/dockerfiles/fedora.docker b/tests/docker/dockerfiles/fedora.docker
index 0d7602abbe..45fc1a77bd 100644
--- a/tests/docker/dockerfiles/fedora.docker
+++ b/tests/docker/dockerfiles/fedora.docker
@@ -32,6 +32,7 @@ ENV PACKAGES \
libcurl-devel \
libepoxy-devel \
libfdt-devel \
+ libffi-devel \
libiscsi-devel \
libjpeg-devel \
libpmem-devel \
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 38/71] tcg/tci: Use ffi for calls
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (36 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 37/71] tcg: Build ffi data structures for helpers Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 39/71] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
` (33 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
This requires adjusting where arguments are stored.
Place them on the stack at left-aligned positions.
Adjust the stack frame to be at entirely positive offsets.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 1 +
tcg/tci/tcg-target.h | 2 +-
tcg/tcg.c | 72 ++++++++++++--------
tcg/tci.c | 138 +++++++++++++++++++++++----------------
tcg/tci/tcg-target.c.inc | 50 +++++++-------
5 files changed, 150 insertions(+), 113 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 0f0695e90d..e5573a9877 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -53,6 +53,7 @@
#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
#define CPU_TEMP_BUF_NLONGS 128
+#define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long))
/* Default target word size to pointer size. */
#ifndef TCG_TARGET_REG_BITS
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 52af6d8bc5..4df10e2e83 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -161,7 +161,7 @@ typedef enum {
/* Used for function call generation. */
#define TCG_TARGET_CALL_STACK_OFFSET 0
-#define TCG_TARGET_STACK_ALIGN 16
+#define TCG_TARGET_STACK_ALIGN 8
#define HAVE_TCG_QEMU_TB_EXEC
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 6382112215..92aec0d238 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -208,6 +208,18 @@ static size_t tree_size;
static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT];
static TCGRegSet tcg_target_call_clobber_regs;
+typedef struct TCGHelperInfo {
+ void *func;
+#ifdef CONFIG_TCG_INTERPRETER
+ ffi_cif *cif;
+#endif
+ const char *name;
+ unsigned flags;
+ unsigned sizemask;
+} TCGHelperInfo;
+
+static GHashTable *helper_table;
+
#if TCG_TARGET_INSN_UNIT_SIZE == 1
static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v)
{
@@ -1084,16 +1096,6 @@ void tcg_pool_reset(TCGContext *s)
s->pool_current = NULL;
}
-typedef struct TCGHelperInfo {
- void *func;
-#ifdef CONFIG_TCG_INTERPRETER
- ffi_cif *cif;
-#endif
- const char *name;
- unsigned flags;
- unsigned sizemask;
-} TCGHelperInfo;
-
#include "exec/helper-proto.h"
#ifdef CONFIG_TCG_INTERPRETER
@@ -1103,7 +1105,6 @@ typedef struct TCGHelperInfo {
static const TCGHelperInfo all_helpers[] = {
#include "exec/helper-tcg.h"
};
-static GHashTable *helper_table;
static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)];
static void process_op_defs(TCGContext *s);
@@ -2081,25 +2082,38 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
real_args = 0;
for (i = 0; i < nargs; i++) {
- int is_64bit = sizemask & (1 << (i+1)*2);
- if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
-#ifdef TCG_TARGET_CALL_ALIGN_ARGS
- /* some targets want aligned 64 bit args */
- if (real_args & 1) {
- op->args[pi++] = TCG_CALL_DUMMY_ARG;
- real_args++;
- }
+ bool is_64bit = sizemask & (1 << (i+1)*2);
+ bool want_align = false;
+
+#if defined(CONFIG_TCG_INTERPRETER)
+ /*
+ * Align all arguments, so that they land in predictable places
+ * for passing off to ffi_call.
+ */
+ want_align = true;
+#elif defined(TCG_TARGET_CALL_ALIGN_ARGS)
+ /* Some targets want aligned 64 bit args */
+ want_align = is_64bit;
#endif
- /* If stack grows up, then we will be placing successive
- arguments at lower addresses, which means we need to
- reverse the order compared to how we would normally
- treat either big or little-endian. For those arguments
- that will wind up in registers, this still works for
- HPPA (the only current STACK_GROWSUP target) since the
- argument registers are *also* allocated in decreasing
- order. If another such target is added, this logic may
- have to get more complicated to differentiate between
- stack arguments and register arguments. */
+
+ if (TCG_TARGET_REG_BITS < 64 && want_align && (real_args & 1)) {
+ op->args[pi++] = TCG_CALL_DUMMY_ARG;
+ real_args++;
+ }
+
+ if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
+ /*
+ * If stack grows up, then we will be placing successive
+ * arguments at lower addresses, which means we need to
+ * reverse the order compared to how we would normally
+ * treat either big or little-endian. For those arguments
+ * that will wind up in registers, this still works for
+ * HPPA (the only current STACK_GROWSUP target) since the
+ * argument registers are *also* allocated in decreasing
+ * order. If another such target is added, this logic may
+ * have to get more complicated to differentiate between
+ * stack arguments and register arguments.
+ */
#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
op->args[pi++] = temp_arg(args[i] + 1);
op->args[pi++] = temp_arg(args[i]);
diff --git a/tcg/tci.c b/tcg/tci.c
index 41d73edc3a..5718fc42a6 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -18,6 +18,13 @@
*/
#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
+#include "exec/cpu_ldst.h"
+#include "tcg/tcg-op.h"
+#include "qemu/compiler.h"
+#include <ffi.h>
+
/* Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
* Without assertions, the interpreter runs much faster. */
@@ -27,36 +34,8 @@
# define tci_assert(cond) ((void)(cond))
#endif
-#include "qemu-common.h"
-#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
-#include "exec/cpu_ldst.h"
-#include "tcg/tcg-op.h"
-#include "qemu/compiler.h"
-
-#if MAX_OPC_PARAM_IARGS != 6
-# error Fix needed, number of supported input arguments changed!
-#endif
-#if TCG_TARGET_REG_BITS == 32
-typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong);
-#else
-typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong);
-#endif
-
__thread uintptr_t tci_tb_ptr;
-static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
-{
- tci_assert(index < TCG_TARGET_NB_REGS);
- return regs[index];
-}
-
static void
tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
{
@@ -131,6 +110,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* i = immediate (uint32_t)
* I = immediate (tcg_target_ulong)
* m = immediate (TCGMemOpIdx)
+ * n = immediate (call return length)
* r = register
* s = signed ldst offset
*/
@@ -151,6 +131,16 @@ static void tci_args_l(const uint8_t **tb_ptr, void **l0)
check_size(start, tb_ptr);
}
+static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1)
+{
+ const uint8_t *start = *tb_ptr;
+
+ *n0 = tci_read_b(tb_ptr);
+ *l1 = (void *)tci_read_label(tb_ptr);
+
+ check_size(start, tb_ptr);
+}
+
static void tci_args_rr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1)
{
@@ -474,6 +464,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
# define CASE_64(x)
#endif
+
/* Interpret pseudo code in tb. */
/*
* Disable CFI checks.
@@ -485,11 +476,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
{
const uint8_t *tb_ptr = v_tb_ptr;
tcg_target_ulong regs[TCG_TARGET_NB_REGS];
- long tcg_temps[CPU_TEMP_BUF_NLONGS];
- uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
+ uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE)
+ / sizeof(uint64_t)];
+ void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)];
regs[TCG_AREG0] = (tcg_target_ulong)env;
- regs[TCG_REG_CALL_STACK] = sp_value;
+ regs[TCG_REG_CALL_STACK] = (uintptr_t)stack;
+ call_slots[0] = NULL;
tci_assert(tb_ptr);
for (;;) {
@@ -514,33 +507,60 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
switch (opc) {
case INDEX_op_call:
- tci_args_l(&tb_ptr, &ptr);
+ /*
+ * We are passed a pointer to the TCGHelperInfo, which contains
+ * the function pointer followed by the ffi_cif pointer.
+ */
+ tci_args_nl(&tb_ptr, &len, &ptr);
+
+ /* Helper functions may need to access the "return address" */
tci_tb_ptr = (uintptr_t)tb_ptr;
-#if TCG_TARGET_REG_BITS == 32
- tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0),
- tci_read_reg(regs, TCG_REG_R1),
- tci_read_reg(regs, TCG_REG_R2),
- tci_read_reg(regs, TCG_REG_R3),
- tci_read_reg(regs, TCG_REG_R4),
- tci_read_reg(regs, TCG_REG_R5),
- tci_read_reg(regs, TCG_REG_R6),
- tci_read_reg(regs, TCG_REG_R7),
- tci_read_reg(regs, TCG_REG_R8),
- tci_read_reg(regs, TCG_REG_R9),
- tci_read_reg(regs, TCG_REG_R10),
- tci_read_reg(regs, TCG_REG_R11));
- tci_write_reg(regs, TCG_REG_R0, tmp64);
- tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32);
-#else
- tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0),
- tci_read_reg(regs, TCG_REG_R1),
- tci_read_reg(regs, TCG_REG_R2),
- tci_read_reg(regs, TCG_REG_R3),
- tci_read_reg(regs, TCG_REG_R4),
- tci_read_reg(regs, TCG_REG_R5));
- tci_write_reg(regs, TCG_REG_R0, tmp64);
-#endif
+
+ /*
+ * Set up the ffi_avalue array once, delayed until now
+ * because many TB's do not make any calls. In tcg_gen_callN,
+ * we arranged for every real argument to be "left-aligned"
+ * in each 64-bit slot.
+ */
+ if (call_slots[0] == NULL) {
+ for (int i = 0; i < ARRAY_SIZE(call_slots); ++i) {
+ call_slots[i] = &stack[i];
+ }
+ }
+
+ /*
+ * Call the helper function. Any result winds up
+ * "left-aligned" in the stack[0] slot.
+ */
+ {
+ void **pptr = ptr;
+ ffi_call(pptr[1], pptr[0], stack, call_slots);
+ }
+ switch (len) {
+ case 0: /* void */
+ break;
+ case 1: /* uint32_t */
+ /*
+ * Note that libffi has an odd special case in that it will
+ * always widen an integral result to ffi_arg.
+ */
+ if (sizeof(ffi_arg) == 4) {
+ regs[TCG_REG_R0] = *(uint32_t *)stack;
+ break;
+ }
+ /* fall through */
+ case 2: /* uint64_t */
+ if (TCG_TARGET_REG_BITS == 32) {
+ tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]);
+ } else {
+ regs[TCG_REG_R0] = stack[0];
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
break;
+
case INDEX_op_br:
tci_args_l(&tb_ptr, &ptr);
tb_ptr = ptr;
@@ -1145,13 +1165,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
switch (op) {
case INDEX_op_br:
- case INDEX_op_call:
case INDEX_op_exit_tb:
case INDEX_op_goto_tb:
tci_args_l(&tb_ptr, &ptr);
info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
break;
+ case INDEX_op_call:
+ tci_args_nl(&tb_ptr, &len, &ptr);
+ info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr);
+ break;
+
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 7fb3b04eaf..8d75482546 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -192,23 +192,8 @@ static const int tcg_target_reg_alloc_order[] = {
# error Fix needed, number of supported input arguments changed!
#endif
-static const int tcg_target_call_iarg_regs[] = {
- TCG_REG_R0,
- TCG_REG_R1,
- TCG_REG_R2,
- TCG_REG_R3,
- TCG_REG_R4,
- TCG_REG_R5,
-#if TCG_TARGET_REG_BITS == 32
- /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
- TCG_REG_R6,
- TCG_REG_R7,
- TCG_REG_R8,
- TCG_REG_R9,
- TCG_REG_R10,
- TCG_REG_R11,
-#endif
-};
+/* No call arguments via registers. All will be stored on the "stack". */
+static const int tcg_target_call_iarg_regs[] = { };
static const int tcg_target_call_oarg_regs[] = {
TCG_REG_R0,
@@ -292,8 +277,9 @@ static void tci_out_label(TCGContext *s, TCGLabel *label)
static void stack_bounds_check(TCGReg base, target_long offset)
{
if (base == TCG_REG_CALL_STACK) {
- tcg_debug_assert(offset < 0);
- tcg_debug_assert(offset >= -(CPU_TEMP_BUF_NLONGS * sizeof(long)));
+ tcg_debug_assert(offset >= 0);
+ tcg_debug_assert(offset < (TCG_STATIC_CALL_ARGS_SIZE +
+ TCG_STATIC_FRAME_SIZE));
}
}
@@ -360,11 +346,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
-static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
+static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
{
uint8_t *old_code_ptr = s->code_ptr;
+ const TCGHelperInfo *info;
+ uint8_t which;
+
+ info = g_hash_table_lookup(helper_table, (gpointer)arg);
+ if (info->cif->rtype == &ffi_type_void) {
+ which = 0;
+ } else if (info->cif->rtype->size == 4) {
+ which = 1;
+ } else {
+ tcg_debug_assert(info->cif->rtype->size == 8);
+ which = 2;
+ }
tcg_out_op_t(s, INDEX_op_call);
- tcg_out_i(s, (uintptr_t)arg);
+ tcg_out8(s, which);
+ tcg_out_i(s, (uintptr_t)info);
+
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
@@ -629,11 +629,9 @@ static void tcg_target_init(TCGContext *s)
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
- /* We use negative offsets from "sp" so that we can distinguish
- stores that might pretend to be call arguments. */
- tcg_set_frame(s, TCG_REG_CALL_STACK,
- -CPU_TEMP_BUF_NLONGS * sizeof(long),
- CPU_TEMP_BUF_NLONGS * sizeof(long));
+ /* The call arguments come first, followed by the temp storage. */
+ tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
+ TCG_STATIC_FRAME_SIZE);
}
/* Generate global QEMU prologue and epilogue code. */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 39/71] tcg/tci: Improve tcg_target_call_clobber_regs
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (37 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 38/71] tcg/tci: Use ffi for calls Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 40/71] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
` (32 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
The current setting is much too pessimistic. Indicating only
the one or two registers that are actually assigned after a
call should avoid unnecessary movement between the register
array and the stack array.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 8d75482546..4dae09deda 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -623,8 +623,14 @@ static void tcg_target_init(TCGContext *s)
tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;
/* Registers available for 64 bit operations. */
tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;
- /* TODO: Which registers should be set here? */
- tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1;
+ /*
+ * The interpreter "registers" are in the local stack frame and
+ * cannot be clobbered by the called helper functions. However,
+ * the interpreter assumes a 64-bit return value and assigns to
+ * the return value registers.
+ */
+ tcg_target_call_clobber_regs =
+ MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS);
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 40/71] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (38 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 39/71] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 41/71] tcg/tci: Push opcode emit into each case Richard Henderson
` (31 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
As the only call-clobbered regs for TCI, these should
receive the least priority.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 4dae09deda..53edc50a3b 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -170,8 +170,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
}
static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_R0,
- TCG_REG_R1,
TCG_REG_R2,
TCG_REG_R3,
TCG_REG_R4,
@@ -186,6 +184,8 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
+ TCG_REG_R1,
+ TCG_REG_R0,
};
#if MAX_OPC_PARAM_IARGS != 6
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 41/71] tcg/tci: Push opcode emit into each case
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (39 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 40/71] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 42/71] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
` (30 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
We're about to split out bytecode output into helpers, but
we can't do that one at a time if tcg_out_op_t is being done
outside of the switch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 53edc50a3b..050d514853 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -385,40 +385,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
{
uint8_t *old_code_ptr = s->code_ptr;
- tcg_out_op_t(s, opc);
-
switch (opc) {
case INDEX_op_exit_tb:
+ tcg_out_op_t(s, opc);
tcg_out_i(s, args[0]);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
case INDEX_op_goto_tb:
tcg_debug_assert(s->tb_jmp_insn_offset == 0);
/* indirect jump method. */
+ tcg_out_op_t(s, opc);
tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0]));
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
set_jmp_reset_offset(s, args[0]);
break;
case INDEX_op_br:
+ tcg_out_op_t(s, opc);
tci_out_label(s, arg_label(args[0]));
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
CASE_32_64(setcond)
+ tcg_out_op_t(s, opc);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out_r(s, args[2]);
tcg_out8(s, args[3]); /* condition */
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
/* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
+ tcg_out_op_t(s, opc);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out_r(s, args[2]);
tcg_out_r(s, args[3]);
tcg_out_r(s, args[4]);
tcg_out8(s, args[5]); /* condition */
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
#endif
@@ -436,10 +444,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
CASE_64(st32)
CASE_64(st)
stack_bounds_check(args[1], args[2]);
+ tcg_out_op_t(s, opc);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_debug_assert(args[2] == (int32_t)args[2]);
tcg_out32(s, args[2]);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
CASE_32_64(add)
@@ -462,12 +472,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */
CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */
CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */
+ tcg_out_op_t(s, opc);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out_r(s, args[2]);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */
+ tcg_out_op_t(s, opc);
{
TCGArg pos = args[3], len = args[4];
TCGArg max = opc == INDEX_op_deposit_i32 ? 32 : 64;
@@ -481,13 +494,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out8(s, pos);
tcg_out8(s, len);
}
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
CASE_32_64(brcond)
+ tcg_out_op_t(s, opc);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out8(s, args[2]); /* condition */
tci_out_label(s, arg_label(args[3]));
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
@@ -503,48 +519,59 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */
CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */
CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */
+ tcg_out_op_t(s, opc);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
+ tcg_out_op_t(s, opc);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out_r(s, args[2]);
tcg_out_r(s, args[3]);
tcg_out_r(s, args[4]);
tcg_out_r(s, args[5]);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
case INDEX_op_brcond2_i32:
+ tcg_out_op_t(s, opc);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out_r(s, args[2]);
tcg_out_r(s, args[3]);
tcg_out8(s, args[4]); /* condition */
tci_out_label(s, arg_label(args[5]));
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
case INDEX_op_mulu2_i32:
+ tcg_out_op_t(s, opc);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out_r(s, args[2]);
tcg_out_r(s, args[3]);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
#endif
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_st_i32:
+ tcg_out_op_t(s, opc);
tcg_out_r(s, *args++);
tcg_out_r(s, *args++);
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
tcg_out_r(s, *args++);
}
tcg_out32(s, *args++);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
+ tcg_out_op_t(s, opc);
tcg_out_r(s, *args++);
if (TCG_TARGET_REG_BITS == 32) {
tcg_out_r(s, *args++);
@@ -554,9 +581,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_r(s, *args++);
}
tcg_out32(s, *args++);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
case INDEX_op_mb:
+ tcg_out_op_t(s, opc);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
@@ -565,7 +595,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
default:
tcg_abort();
}
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 42/71] tcg/tci: Split out tcg_out_op_rrs
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (40 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 41/71] tcg/tci: Push opcode emit into each case Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 43/71] tcg/tci: Split out tcg_out_op_l Richard Henderson
` (29 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 84 +++++++++++++++++++---------------------
1 file changed, 39 insertions(+), 45 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 050d514853..707f801099 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -283,32 +283,38 @@ static void stack_bounds_check(TCGReg base, target_long offset)
}
}
-static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
- intptr_t arg2)
+static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, intptr_t i2)
{
uint8_t *old_code_ptr = s->code_ptr;
- stack_bounds_check(arg1, arg2);
- if (type == TCG_TYPE_I32) {
- tcg_out_op_t(s, INDEX_op_ld_i32);
- tcg_out_r(s, ret);
- tcg_out_r(s, arg1);
- tcg_out32(s, arg2);
- } else {
- tcg_debug_assert(type == TCG_TYPE_I64);
-#if TCG_TARGET_REG_BITS == 64
- tcg_out_op_t(s, INDEX_op_ld_i64);
- tcg_out_r(s, ret);
- tcg_out_r(s, arg1);
- tcg_debug_assert(arg2 == (int32_t)arg2);
- tcg_out32(s, arg2);
-#else
- TODO();
-#endif
- }
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_debug_assert(i2 == (int32_t)i2);
+ tcg_out32(s, i2);
+
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
+ intptr_t offset)
+{
+ stack_bounds_check(base, offset);
+ switch (type) {
+ case TCG_TYPE_I32:
+ tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset);
+ break;
+#if TCG_TARGET_REG_BITS == 64
+ case TCG_TYPE_I64:
+ tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset);
+ break;
+#endif
+ default:
+ g_assert_not_reached();
+ }
+}
+
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
uint8_t *old_code_ptr = s->code_ptr;
@@ -444,12 +450,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
CASE_64(st32)
CASE_64(st)
stack_bounds_check(args[1], args[2]);
- tcg_out_op_t(s, opc);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_debug_assert(args[2] == (int32_t)args[2]);
- tcg_out32(s, args[2]);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_rrs(s, opc, args[0], args[1], args[2]);
break;
CASE_32_64(add)
@@ -597,29 +598,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
}
}
-static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
- intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
+ intptr_t offset)
{
- uint8_t *old_code_ptr = s->code_ptr;
-
- stack_bounds_check(arg1, arg2);
- if (type == TCG_TYPE_I32) {
- tcg_out_op_t(s, INDEX_op_st_i32);
- tcg_out_r(s, arg);
- tcg_out_r(s, arg1);
- tcg_out32(s, arg2);
- } else {
- tcg_debug_assert(type == TCG_TYPE_I64);
+ stack_bounds_check(base, offset);
+ switch (type) {
+ case TCG_TYPE_I32:
+ tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset);
+ break;
#if TCG_TARGET_REG_BITS == 64
- tcg_out_op_t(s, INDEX_op_st_i64);
- tcg_out_r(s, arg);
- tcg_out_r(s, arg1);
- tcg_out32(s, arg2);
-#else
- TODO();
+ case TCG_TYPE_I64:
+ tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset);
+ break;
#endif
+ default:
+ g_assert_not_reached();
}
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 43/71] tcg/tci: Split out tcg_out_op_l
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (41 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 42/71] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 44/71] tcg/tci: Split out tcg_out_op_p Richard Henderson
` (28 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 707f801099..1e3f2c4049 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -283,6 +283,16 @@ static void stack_bounds_check(TCGReg base, target_long offset)
}
}
+static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tci_out_label(s, l0);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, intptr_t i2)
{
@@ -408,9 +418,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
case INDEX_op_br:
- tcg_out_op_t(s, opc);
- tci_out_label(s, arg_label(args[0]));
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_l(s, opc, arg_label(args[0]));
break;
CASE_32_64(setcond)
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 44/71] tcg/tci: Split out tcg_out_op_p
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (42 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 43/71] tcg/tci: Split out tcg_out_op_l Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 45/71] tcg/tci: Split out tcg_out_op_rr Richard Henderson
` (27 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 1e3f2c4049..cb0cbbb8da 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -293,6 +293,16 @@ static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0)
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_i(s, (uintptr_t)p0);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, intptr_t i2)
{
@@ -403,17 +413,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
switch (opc) {
case INDEX_op_exit_tb:
- tcg_out_op_t(s, opc);
- tcg_out_i(s, args[0]);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_p(s, opc, (void *)args[0]);
break;
case INDEX_op_goto_tb:
tcg_debug_assert(s->tb_jmp_insn_offset == 0);
/* indirect jump method. */
- tcg_out_op_t(s, opc);
- tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0]));
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]);
set_jmp_reset_offset(s, args[0]);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 45/71] tcg/tci: Split out tcg_out_op_rr
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (43 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 44/71] tcg/tci: Split out tcg_out_op_p Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 46/71] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
` (26 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
At the same time, validate the type argument in tcg_out_mov.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 36 +++++++++++++++++++++++-------------
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index cb0cbbb8da..272e3ca70b 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -303,6 +303,17 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0)
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, intptr_t i2)
{
@@ -337,16 +348,18 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
- uint8_t *old_code_ptr = s->code_ptr;
- tcg_debug_assert(ret != arg);
-#if TCG_TARGET_REG_BITS == 32
- tcg_out_op_t(s, INDEX_op_mov_i32);
-#else
- tcg_out_op_t(s, INDEX_op_mov_i64);
+ switch (type) {
+ case TCG_TYPE_I32:
+ tcg_out_op_rr(s, INDEX_op_mov_i32, ret, arg);
+ break;
+#if TCG_TARGET_REG_BITS == 64
+ case TCG_TYPE_I64:
+ tcg_out_op_rr(s, INDEX_op_mov_i64, ret, arg);
+ break;
#endif
- tcg_out_r(s, ret);
- tcg_out_r(s, arg);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ default:
+ g_assert_not_reached();
+ }
return true;
}
@@ -534,10 +547,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */
CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */
CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */
- tcg_out_op_t(s, opc);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_rr(s, opc, args[0], args[1]);
break;
#if TCG_TARGET_REG_BITS == 32
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 46/71] tcg/tci: Split out tcg_out_op_rrr
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (44 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 45/71] tcg/tci: Split out tcg_out_op_rr Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 47/71] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
` (25 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 272e3ca70b..546424c2bd 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, TCGReg r2)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out_r(s, r2);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, intptr_t i2)
{
@@ -500,11 +513,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */
CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */
CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */
- tcg_out_op_t(s, opc);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_rrr(s, opc, args[0], args[1], args[2]);
break;
CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 47/71] tcg/tci: Split out tcg_out_op_rrrc
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (45 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 46/71] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 48/71] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
` (24 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 546424c2bd..5848779208 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -341,6 +341,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out_r(s, r2);
+ tcg_out8(s, c3);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
intptr_t offset)
{
@@ -454,12 +468,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
CASE_32_64(setcond)
- tcg_out_op_t(s, opc);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_out8(s, args[3]); /* condition */
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]);
break;
#if TCG_TARGET_REG_BITS == 32
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 48/71] tcg/tci: Split out tcg_out_op_rrrrrc
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (46 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 47/71] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 49/71] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
` (23 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 30 +++++++++++++++++++++---------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 5848779208..8eda159dde 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -355,6 +355,25 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+#if TCG_TARGET_REG_BITS == 32
+static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, TCGReg r2,
+ TCGReg r3, TCGReg r4, TCGCond c5)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out_r(s, r2);
+ tcg_out_r(s, r3);
+ tcg_out_r(s, r4);
+ tcg_out8(s, c5);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+#endif
+
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
intptr_t offset)
{
@@ -473,15 +492,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
- /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
- tcg_out_op_t(s, opc);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_out_r(s, args[3]);
- tcg_out_r(s, args[4]);
- tcg_out8(s, args[5]); /* condition */
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2],
+ args[3], args[4], args[5]);
break;
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 49/71] tcg/tci: Split out tcg_out_op_rrrbb
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (47 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 48/71] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 50/71] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
` (22 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 8eda159dde..6c743a8fbd 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -355,6 +355,21 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
+ TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out_r(s, r2);
+ tcg_out8(s, b3);
+ tcg_out8(s, b4);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
@@ -538,7 +553,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */
- tcg_out_op_t(s, opc);
{
TCGArg pos = args[3], len = args[4];
TCGArg max = opc == INDEX_op_deposit_i32 ? 32 : 64;
@@ -546,13 +560,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_debug_assert(pos < max);
tcg_debug_assert(pos + len <= max);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_out8(s, pos);
- tcg_out8(s, len);
+ tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], pos, len);
}
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
CASE_32_64(brcond)
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 50/71] tcg/tci: Split out tcg_out_op_rrcl
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (48 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 49/71] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 51/71] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
` (21 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 6c743a8fbd..8cc63124d4 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -341,6 +341,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out8(s, c2);
+ tci_out_label(s, l3);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
{
@@ -565,12 +579,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
CASE_32_64(brcond)
- tcg_out_op_t(s, opc);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out8(s, args[2]); /* condition */
- tci_out_label(s, arg_label(args[3]));
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[3]));
break;
CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 51/71] tcg/tci: Split out tcg_out_op_rrrrrr
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (49 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 50/71] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 52/71] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
` (20 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 8cc63124d4..f7595fbd65 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -401,6 +401,23 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+
+static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, TCGReg r2,
+ TCGReg r3, TCGReg r4, TCGReg r5)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out_r(s, r2);
+ tcg_out_r(s, r3);
+ tcg_out_r(s, r4);
+ tcg_out_r(s, r5);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
#endif
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
@@ -601,14 +618,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- tcg_out_op_t(s, opc);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_out_r(s, args[3]);
- tcg_out_r(s, args[4]);
- tcg_out_r(s, args[5]);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2],
+ args[3], args[4], args[5]);
break;
case INDEX_op_brcond2_i32:
tcg_out_op_t(s, opc);
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 52/71] tcg/tci: Split out tcg_out_op_rrrr
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (50 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 51/71] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 53/71] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
` (19 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index f7595fbd65..c2bbd85130 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -385,6 +385,20 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
}
#if TCG_TARGET_REG_BITS == 32
+static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out_r(s, r2);
+ tcg_out_r(s, r3);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGCond c5)
@@ -632,12 +646,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
case INDEX_op_mulu2_i32:
- tcg_out_op_t(s, opc);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_out_r(s, args[3]);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]);
break;
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 53/71] tcg/tci: Split out tcg_out_op_rrrrcl
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (51 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 52/71] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 54/71] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
` (18 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index c2bbd85130..fb4aacaca3 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -399,6 +399,23 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3,
+ TCGCond c4, TCGLabel *l5)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out_r(s, r2);
+ tcg_out_r(s, r3);
+ tcg_out8(s, c4);
+ tci_out_label(s, l5);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGCond c5)
@@ -636,14 +653,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
args[3], args[4], args[5]);
break;
case INDEX_op_brcond2_i32:
- tcg_out_op_t(s, opc);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_out_r(s, args[3]);
- tcg_out8(s, args[4]); /* condition */
- tci_out_label(s, arg_label(args[5]));
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2],
+ args[3], args[4], arg_label(args[5]));
break;
case INDEX_op_mulu2_i32:
tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]);
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 54/71] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm}
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (52 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 53/71] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 55/71] tcg/tci: Split out tcg_out_op_v Richard Henderson
` (17 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++----------
1 file changed, 53 insertions(+), 17 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index fb4aacaca3..f93772f01f 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, TCGArg m2)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out32(s, m2);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2)
{
@@ -369,6 +382,20 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out_r(s, r2);
+ tcg_out32(s, m3);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4)
{
@@ -384,6 +411,21 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0,
+ TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_out_r(s, r2);
+ tcg_out_r(s, r3);
+ tcg_out32(s, m4);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3)
@@ -663,29 +705,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_st_i32:
- tcg_out_op_t(s, opc);
- tcg_out_r(s, *args++);
- tcg_out_r(s, *args++);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_out_r(s, *args++);
+ if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
+ tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
+ } else {
+ tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]);
}
- tcg_out32(s, *args++);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
- tcg_out_op_t(s, opc);
- tcg_out_r(s, *args++);
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out_r(s, *args++);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
+ } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
+ tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]);
+ } else {
+ tcg_out_op_rrrrm(s, opc, args[0], args[1],
+ args[2], args[3], args[4]);
}
- tcg_out_r(s, *args++);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_out_r(s, *args++);
- }
- tcg_out32(s, *args++);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
break;
case INDEX_op_mb:
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 55/71] tcg/tci: Split out tcg_out_op_v
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (53 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 54/71] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 56/71] tcg/tci: Split out tcg_out_op_np Richard Henderson
` (16 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index f93772f01f..eeafec6d44 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -303,6 +303,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0)
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_v(TCGContext *s, TCGOpcode op)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
{
uint8_t *old_code_ptr = s->code_ptr;
@@ -587,8 +596,6 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args)
{
- uint8_t *old_code_ptr = s->code_ptr;
-
switch (opc) {
case INDEX_op_exit_tb:
tcg_out_op_p(s, opc, (void *)args[0]);
@@ -725,8 +732,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
case INDEX_op_mb:
- tcg_out_op_t(s, opc);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_v(s, opc);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 56/71] tcg/tci: Split out tcg_out_op_np
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (54 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 55/71] tcg/tci: Split out tcg_out_op_v Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 57/71] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
` (15 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index eeafec6d44..e4a5872b2a 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -312,6 +312,18 @@ static void tcg_out_op_v(TCGContext *s, TCGOpcode op)
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_np(TCGContext *s, TCGOpcode op,
+ uint8_t n0, const void *p1)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out8(s, n0);
+ tcg_out_i(s, (uintptr_t)p1);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
{
uint8_t *old_code_ptr = s->code_ptr;
@@ -561,7 +573,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
{
- uint8_t *old_code_ptr = s->code_ptr;
const TCGHelperInfo *info;
uint8_t which;
@@ -574,11 +585,8 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
tcg_debug_assert(info->cif->rtype->size == 8);
which = 2;
}
- tcg_out_op_t(s, INDEX_op_call);
- tcg_out8(s, which);
- tcg_out_i(s, (uintptr_t)info);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_np(s, INDEX_op_call, which, info);
}
#if TCG_TARGET_REG_BITS == 64
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 57/71] tcg/tci: Split out tcg_out_op_r[iI]
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (55 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 56/71] tcg/tci: Split out tcg_out_op_np Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 58/71] tcg/tci: Reserve r13 for a temporary Richard Henderson
` (14 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 50 ++++++++++++++++++++++++++++------------
1 file changed, 35 insertions(+), 15 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index e4a5872b2a..c2d2bd24d7 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -324,6 +324,31 @@ static void tcg_out_op_np(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t i1)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out32(s, i1);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
+#if TCG_TARGET_REG_BITS == 64
+static void tcg_out_op_rI(TCGContext *s, TCGOpcode op,
+ TCGReg r0, uint64_t i1)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out64(s, i1);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+#endif
+
static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
{
uint8_t *old_code_ptr = s->code_ptr;
@@ -550,25 +575,20 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
}
static void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg t0, tcg_target_long arg)
+ TCGReg ret, tcg_target_long arg)
{
- uint8_t *old_code_ptr = s->code_ptr;
- uint32_t arg32 = arg;
- if (type == TCG_TYPE_I32 || arg == arg32) {
- tcg_out_op_t(s, INDEX_op_tci_movi_i32);
- tcg_out_r(s, t0);
- tcg_out32(s, arg32);
- } else {
- tcg_debug_assert(type == TCG_TYPE_I64);
+ switch (type) {
+ case TCG_TYPE_I32:
+ tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg);
+ break;
#if TCG_TARGET_REG_BITS == 64
- tcg_out_op_t(s, INDEX_op_tci_movi_i64);
- tcg_out_r(s, t0);
- tcg_out64(s, arg);
-#else
- TODO();
+ case TCG_TYPE_I64:
+ tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg);
+ break;
#endif
+ default:
+ g_assert_not_reached();
}
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 58/71] tcg/tci: Reserve r13 for a temporary
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (56 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 57/71] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 59/71] tcg/tci: Emit setcond before brcond Richard Henderson
` (13 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
We're about to adjust the offset range on host memory ops,
and the format of branches. Both will require a temporary.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 1 +
tcg/tci/tcg-target.c.inc | 1 +
2 files changed, 2 insertions(+)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 4df10e2e83..1558a6e44e 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -155,6 +155,7 @@ typedef enum {
TCG_REG_R14,
TCG_REG_R15,
+ TCG_REG_TMP = TCG_REG_R13,
TCG_AREG0 = TCG_REG_R14,
TCG_REG_CALL_STACK = TCG_REG_R15,
} TCGReg;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index c2d2bd24d7..b29e75425d 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -829,6 +829,7 @@ static void tcg_target_init(TCGContext *s)
MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS);
s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
/* The call arguments come first, followed by the temp storage. */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 59/71] tcg/tci: Emit setcond before brcond
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (57 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 58/71] tcg/tci: Reserve r13 for a temporary Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 60/71] tcg/tci: Remove tci_write_reg Richard Henderson
` (12 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
The encoding planned for tci does not have enough room for
brcond2, with 4 registers and a condition as input as well
as the label. Resolve the condition into TCG_REG_TMP, and
relax brcond to one register plus a label, considering the
condition to always be reg != 0.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 68 ++++++++++------------------------------
tcg/tci/tcg-target.c.inc | 52 +++++++++++-------------------
2 files changed, 35 insertions(+), 85 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 5718fc42a6..3f8c6a0291 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -141,6 +141,16 @@ static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1)
check_size(start, tb_ptr);
}
+static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1)
+{
+ const uint8_t *start = *tb_ptr;
+
+ *r0 = tci_read_r(tb_ptr);
+ *l1 = (void *)tci_read_label(tb_ptr);
+
+ check_size(start, tb_ptr);
+}
+
static void tci_args_rr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1)
{
@@ -212,19 +222,6 @@ static void tci_args_rrs(const uint8_t **tb_ptr,
check_size(start, tb_ptr);
}
-static void tci_args_rrcl(const uint8_t **tb_ptr,
- TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3)
-{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *c2 = tci_read_b(tb_ptr);
- *l3 = (void *)tci_read_label(tb_ptr);
-
- check_size(start, tb_ptr);
-}
-
static void tci_args_rrrc(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{
@@ -293,21 +290,6 @@ static void tci_args_rrrr(const uint8_t **tb_ptr,
check_size(start, tb_ptr);
}
-static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
- TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5)
-{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *r3 = tci_read_r(tb_ptr);
- *c4 = tci_read_b(tb_ptr);
- *l5 = (void *)tci_read_label(tb_ptr);
-
- check_size(start, tb_ptr);
-}
-
static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
{
@@ -713,8 +695,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i32:
- tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
- if (tci_compare32(regs[r0], regs[r1], condition)) {
+ tci_args_rl(&tb_ptr, &r0, &ptr);
+ if ((uint32_t)regs[r0]) {
tb_ptr = ptr;
}
break;
@@ -731,15 +713,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 - T2);
break;
- case INDEX_op_brcond2_i32:
- tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr);
- T1 = tci_uint64(regs[r1], regs[r0]);
- T2 = tci_uint64(regs[r3], regs[r2]);
- if (tci_compare64(T1, T2, condition)) {
- tb_ptr = ptr;
- continue;
- }
- break;
case INDEX_op_mulu2_i32:
tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]);
@@ -867,8 +840,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i64:
- tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
- if (tci_compare64(regs[r0], regs[r1], condition)) {
+ tci_args_rl(&tb_ptr, &r0, &ptr);
+ if (regs[r0]) {
tb_ptr = ptr;
}
break;
@@ -1178,9 +1151,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr);
- info->fprintf_func(info->stream, "%-12s %s,%s,%s,%p",
- op_name, str_r(r0), str_r(r1), str_c(c), ptr);
+ tci_args_rl(&tb_ptr, &r0, &ptr);
+ info->fprintf_func(info->stream, "%-12s %s,0,ne,%p",
+ op_name, str_r(r0), ptr);
break;
case INDEX_op_setcond_i32:
@@ -1305,13 +1278,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
str_r(r3), str_r(r4), str_c(c));
break;
- case INDEX_op_brcond2_i32:
- tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr);
- info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%p",
- op_name, str_r(r0), str_r(r1),
- str_r(r2), str_r(r3), str_c(c), ptr);
- break;
-
case INDEX_op_mulu2_i32:
tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s",
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index b29e75425d..e06d4e9380 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -349,6 +349,17 @@ static void tcg_out_op_rI(TCGContext *s, TCGOpcode op,
}
#endif
+static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel *l1)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tci_out_label(s, l1);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
{
uint8_t *old_code_ptr = s->code_ptr;
@@ -400,20 +411,6 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
-static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op,
- TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3)
-{
- uint8_t *old_code_ptr = s->code_ptr;
-
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out8(s, c2);
- tci_out_label(s, l3);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
{
@@ -487,23 +484,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
-static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op,
- TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3,
- TCGCond c4, TCGLabel *l5)
-{
- uint8_t *old_code_ptr = s->code_ptr;
-
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out_r(s, r3);
- tcg_out8(s, c4);
- tci_out_label(s, l5);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGCond c5)
@@ -704,7 +684,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
CASE_32_64(brcond)
- tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[3]));
+ tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32
+ ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64),
+ TCG_REG_TMP, args[0], args[1], args[2]);
+ tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3]));
break;
CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
@@ -730,8 +713,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
args[3], args[4], args[5]);
break;
case INDEX_op_brcond2_i32:
- tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2],
- args[3], args[4], arg_label(args[5]));
+ tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP,
+ args[0], args[1], args[2], args[3], args[4]);
+ tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[5]));
break;
case INDEX_op_mulu2_i32:
tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]);
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 60/71] tcg/tci: Remove tci_write_reg
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (58 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 59/71] tcg/tci: Emit setcond before brcond Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 61/71] tcg/tci: Change encoding to uint32_t units Richard Henderson
` (11 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Inline it into its one caller, tci_write_reg64.
Drop the asserts that are redundant with tcg_read_r.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 3f8c6a0291..0b2bc905ea 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -36,20 +36,11 @@
__thread uintptr_t tci_tb_ptr;
-static void
-tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
-{
- tci_assert(index < TCG_TARGET_NB_REGS);
- tci_assert(index != TCG_AREG0);
- tci_assert(index != TCG_REG_CALL_STACK);
- regs[index] = value;
-}
-
static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
uint32_t low_index, uint64_t value)
{
- tci_write_reg(regs, low_index, value);
- tci_write_reg(regs, high_index, value >> 32);
+ regs[low_index] = value;
+ regs[high_index] = value >> 32;
}
/* Create a 64 bit value from two 32 bit values. */
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 61/71] tcg/tci: Change encoding to uint32_t units
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (59 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 60/71] tcg/tci: Remove tci_write_reg Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 62/71] tcg/tci: Implement goto_ptr Richard Henderson
` (10 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
This removes all of the problems with unaligned accesses
to the bytecode stream.
With an 8-bit opcode at the bottom, we have 24 bits remaining,
which are generally split into 6 4-bit slots. This fits well
with the maximum length opcodes, e.g. INDEX_op_add2_i386, which
have 6 register operands.
We have, in previous patches, rearranged things such that there
are no operations with a label, which have more than one other
operand. Which leaves us with a 20-bit field in which to encode
a label, giving us a maximum TB size of 512k -- easily large.
Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il].
The former puts the immediate in the upper 20 bits of the insn,
like we do for the label displacement. The later uses a label
to reference an entry in the constant pool. Thus, in the worst
case we still have a single memory reference for any constant,
but now the constants are out-of-line of the bytecode and can
be shared between different moves saving space.
Change INDEX_op_call to use a label to reference a pair of
pointers in the constant pool. This removes the only slightly
dodgy link with the layout of struct TCGHelperInfo.
The re-encode cannot be done in pieces.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-opc.h | 4 +-
tcg/tci/tcg-target.h | 3 +-
tcg/tci.c | 534 +++++++++++++++------------------------
tcg/tci/tcg-target.c.inc | 386 +++++++++++++---------------
tcg/tci/README | 20 +-
5 files changed, 380 insertions(+), 567 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index bbb0884af8..5bbec858aa 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -277,8 +277,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
#ifdef TCG_TARGET_INTERPRETER
/* These opcodes are only for use between the tci generator and interpreter. */
-DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
-DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
+DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT)
+DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT)
#endif
#undef TLADDR_ARGS
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 1558a6e44e..d953f2ead3 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -41,7 +41,7 @@
#define TCG_TARGET_H
#define TCG_TARGET_INTERPRETER 1
-#define TCG_TARGET_INSN_UNIT_SIZE 1
+#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
#if UINTPTR_MAX == UINT32_MAX
@@ -165,6 +165,7 @@ typedef enum {
#define TCG_TARGET_STACK_ALIGN 8
#define HAVE_TCG_QEMU_TB_EXEC
+#define TCG_TARGET_NEED_POOL_LABELS
/* We could notice __i386__ or __s390x__ and reduce the barriers depending
on the host. But if you want performance, you use the normal backend.
diff --git a/tcg/tci.c b/tcg/tci.c
index 0b2bc905ea..76bbf440a8 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -49,49 +49,6 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low)
return ((uint64_t)high << 32) + low;
}
-/* Read constant byte from bytecode. */
-static uint8_t tci_read_b(const uint8_t **tb_ptr)
-{
- return *(tb_ptr[0]++);
-}
-
-/* Read register number from bytecode. */
-static TCGReg tci_read_r(const uint8_t **tb_ptr)
-{
- uint8_t regno = tci_read_b(tb_ptr);
- tci_assert(regno < TCG_TARGET_NB_REGS);
- return regno;
-}
-
-/* Read constant (native size) from bytecode. */
-static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr)
-{
- tcg_target_ulong value = *(const tcg_target_ulong *)(*tb_ptr);
- *tb_ptr += sizeof(value);
- return value;
-}
-
-/* Read unsigned constant (32 bit) from bytecode. */
-static uint32_t tci_read_i32(const uint8_t **tb_ptr)
-{
- uint32_t value = *(const uint32_t *)(*tb_ptr);
- *tb_ptr += sizeof(value);
- return value;
-}
-
-/* Read signed constant (32 bit) from bytecode. */
-static int32_t tci_read_s32(const uint8_t **tb_ptr)
-{
- int32_t value = *(const int32_t *)(*tb_ptr);
- *tb_ptr += sizeof(value);
- return value;
-}
-
-static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
-{
- return tci_read_i(tb_ptr);
-}
-
/*
* Load sets of arguments all at once. The naming convention is:
* tci_args_<arguments>
@@ -106,209 +63,128 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* s = signed ldst offset
*/
-static void check_size(const uint8_t *start, const uint8_t **tb_ptr)
+static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0)
{
- const uint8_t *old_code_ptr = start - 2;
- uint8_t op_size = old_code_ptr[1];
- tci_assert(*tb_ptr == old_code_ptr + op_size);
+ int diff = sextract32(insn, 12, 20);
+ *l0 = diff ? (void *)tb_ptr + diff : NULL;
}
-static void tci_args_l(const uint8_t **tb_ptr, void **l0)
+static void tci_args_nl(uint32_t insn, const void *tb_ptr,
+ uint8_t *n0, void **l1)
{
- const uint8_t *start = *tb_ptr;
-
- *l0 = (void *)tci_read_label(tb_ptr);
-
- check_size(start, tb_ptr);
+ *n0 = extract32(insn, 8, 4);
+ *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr;
}
-static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1)
+static void tci_args_rl(uint32_t insn, const void *tb_ptr,
+ TCGReg *r0, void **l1)
{
- const uint8_t *start = *tb_ptr;
-
- *n0 = tci_read_b(tb_ptr);
- *l1 = (void *)tci_read_label(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr;
}
-static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1)
+static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *l1 = (void *)tci_read_label(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
}
-static void tci_args_rr(const uint8_t **tb_ptr,
- TCGReg *r0, TCGReg *r1)
+static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *i1 = sextract32(insn, 12, 20);
}
-static void tci_args_ri(const uint8_t **tb_ptr,
- TCGReg *r0, tcg_target_ulong *i1)
+static void tci_args_rrm(uint32_t insn, TCGReg *r0,
+ TCGReg *r1, TCGMemOpIdx *m2)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *i1 = tci_read_i32(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *m2 = extract32(insn, 20, 12);
}
-#if TCG_TARGET_REG_BITS == 64
-static void tci_args_rI(const uint8_t **tb_ptr,
- TCGReg *r0, tcg_target_ulong *i1)
+static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *i1 = tci_read_i(tb_ptr);
-
- check_size(start, tb_ptr);
-}
-#endif
-
-static void tci_args_rrm(const uint8_t **tb_ptr,
- TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2)
-{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *m2 = tci_read_i32(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
}
-static void tci_args_rrr(const uint8_t **tb_ptr,
- TCGReg *r0, TCGReg *r1, TCGReg *r2)
+static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *i2 = sextract32(insn, 16, 16);
}
-static void tci_args_rrs(const uint8_t **tb_ptr,
- TCGReg *r0, TCGReg *r1, int32_t *i2)
-{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *i2 = tci_read_s32(tb_ptr);
-
- check_size(start, tb_ptr);
-}
-
-static void tci_args_rrrc(const uint8_t **tb_ptr,
+static void tci_args_rrrc(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *c3 = tci_read_b(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *c3 = extract32(insn, 20, 4);
}
-static void tci_args_rrrm(const uint8_t **tb_ptr,
+static void tci_args_rrrm(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *m3 = tci_read_i32(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *m3 = extract32(insn, 20, 12);
}
-static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, uint8_t *i3, uint8_t *i4)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *i3 = tci_read_b(tb_ptr);
- *i4 = tci_read_b(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *i3 = extract32(insn, 20, 6);
+ *i4 = extract32(insn, 26, 6);
}
-static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
- TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4)
+static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
+ TCGReg *r2, TCGReg *r3, TCGReg *r4)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *r3 = tci_read_r(tb_ptr);
- *m4 = tci_read_i32(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *r3 = extract32(insn, 20, 4);
+ *r4 = extract32(insn, 24, 4);
}
#if TCG_TARGET_REG_BITS == 32
-static void tci_args_rrrr(const uint8_t **tb_ptr,
+static void tci_args_rrrr(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *r3 = tci_read_r(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *r3 = extract32(insn, 20, 4);
}
-static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *r3 = tci_read_r(tb_ptr);
- *r4 = tci_read_r(tb_ptr);
- *c5 = tci_read_b(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *r3 = extract32(insn, 20, 4);
+ *r4 = extract32(insn, 24, 4);
+ *c5 = extract32(insn, 28, 4);
}
-static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *r3 = tci_read_r(tb_ptr);
- *r4 = tci_read_r(tb_ptr);
- *r5 = tci_read_r(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *r3 = extract32(insn, 20, 4);
+ *r4 = extract32(insn, 24, 4);
+ *r5 = extract32(insn, 28, 4);
}
#endif
@@ -447,7 +323,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
const void *v_tb_ptr)
{
- const uint8_t *tb_ptr = v_tb_ptr;
+ const uint32_t *tb_ptr = v_tb_ptr;
tcg_target_ulong regs[TCG_TARGET_NB_REGS];
uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE)
/ sizeof(uint64_t)];
@@ -459,8 +335,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_assert(tb_ptr);
for (;;) {
- TCGOpcode opc = tb_ptr[0];
- TCGReg r0, r1, r2, r3;
+ uint32_t insn;
+ TCGOpcode opc;
+ TCGReg r0, r1, r2, r3, r4;
tcg_target_ulong t1;
TCGCond condition;
target_ulong taddr;
@@ -468,23 +345,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
- TCGReg r4, r5;
+ TCGReg r5;
uint64_t T1, T2;
#endif
TCGMemOpIdx oi;
int32_t ofs;
void *ptr;
- /* Skip opcode and size entry. */
- tb_ptr += 2;
+ insn = *tb_ptr++;
+ opc = extract32(insn, 0, 8);
switch (opc) {
case INDEX_op_call:
- /*
- * We are passed a pointer to the TCGHelperInfo, which contains
- * the function pointer followed by the ffi_cif pointer.
- */
- tci_args_nl(&tb_ptr, &len, &ptr);
+ tci_args_nl(insn, tb_ptr, &len, &ptr);
/* Helper functions may need to access the "return address" */
tci_tb_ptr = (uintptr_t)tb_ptr;
@@ -502,8 +375,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
/*
- * Call the helper function. Any result winds up
- * "left-aligned" in the stack[0] slot.
+ * We are passed a pointer into the constant pool, which
+ * contains a pair of the function pointer and the cif pointer.
+ * Any result winds up "left-aligned" in the stack[0] slot.
*/
{
void **pptr = ptr;
@@ -535,76 +409,80 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
case INDEX_op_br:
- tci_args_l(&tb_ptr, &ptr);
+ tci_args_l(insn, tb_ptr, &ptr);
tb_ptr = ptr;
continue;
case INDEX_op_setcond_i32:
- tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition);
+ tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
regs[r0] = tci_compare32(regs[r1], regs[r2], condition);
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
- tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition);
+ tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
T1 = tci_uint64(regs[r2], regs[r1]);
T2 = tci_uint64(regs[r4], regs[r3]);
regs[r0] = tci_compare64(T1, T2, condition);
break;
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
- tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition);
+ tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
regs[r0] = tci_compare64(regs[r1], regs[r2], condition);
break;
#endif
CASE_32_64(mov)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = regs[r1];
break;
- case INDEX_op_tci_movi_i32:
- tci_args_ri(&tb_ptr, &r0, &t1);
+ case INDEX_op_tci_movi:
+ tci_args_ri(insn, &r0, &t1);
regs[r0] = t1;
break;
+ case INDEX_op_tci_movl:
+ tci_args_rl(insn, tb_ptr, &r0, &ptr);
+ regs[r0] = *(tcg_target_ulong *)ptr;
+ break;
/* Load/store operations (32 bit). */
CASE_32_64(ld8u)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(uint8_t *)ptr;
break;
CASE_32_64(ld8s)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(int8_t *)ptr;
break;
CASE_32_64(ld16u)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(uint16_t *)ptr;
break;
CASE_32_64(ld16s)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(int16_t *)ptr;
break;
case INDEX_op_ld_i32:
CASE_64(ld32u)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(uint32_t *)ptr;
break;
CASE_32_64(st8)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
*(uint8_t *)ptr = regs[r0];
break;
CASE_32_64(st16)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
*(uint16_t *)ptr = regs[r0];
break;
case INDEX_op_st_i32:
CASE_64(st32)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
*(uint32_t *)ptr = regs[r0];
break;
@@ -612,171 +490,166 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (mixed 32/64 bit). */
CASE_32_64(add)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] + regs[r2];
break;
CASE_32_64(sub)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] - regs[r2];
break;
CASE_32_64(mul)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] * regs[r2];
break;
CASE_32_64(and)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] & regs[r2];
break;
CASE_32_64(or)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] | regs[r2];
break;
CASE_32_64(xor)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] ^ regs[r2];
break;
/* Arithmetic operations (32 bit). */
case INDEX_op_div_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2];
break;
case INDEX_op_divu_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2];
break;
case INDEX_op_rem_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2];
break;
case INDEX_op_remu_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
break;
/* Shift/rotate operations (32 bit). */
case INDEX_op_shl_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31);
break;
case INDEX_op_shr_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31);
break;
case INDEX_op_sar_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31);
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = rol32(regs[r1], regs[r2] & 31);
break;
case INDEX_op_rotr_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = ror32(regs[r1], regs[r2] & 31);
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
case INDEX_op_deposit_i32:
- tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
+ tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
break;
#endif
case INDEX_op_brcond_i32:
- tci_args_rl(&tb_ptr, &r0, &ptr);
+ tci_args_rl(insn, tb_ptr, &r0, &ptr);
if ((uint32_t)regs[r0]) {
tb_ptr = ptr;
}
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
- tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 + T2);
break;
case INDEX_op_sub2_i32:
- tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 - T2);
break;
case INDEX_op_mulu2_i32:
- tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
CASE_32_64(ext8s)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (int8_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
CASE_32_64(ext16s)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (int16_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
CASE_32_64(ext8u)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (uint8_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
CASE_32_64(ext16u)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (uint16_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
CASE_32_64(bswap16)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap16(regs[r1]);
break;
#endif
#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
CASE_32_64(bswap32)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap32(regs[r1]);
break;
#endif
#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
CASE_32_64(not)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = ~regs[r1];
break;
#endif
#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
CASE_32_64(neg)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = -regs[r1];
break;
#endif
#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_tci_movi_i64:
- tci_args_rI(&tb_ptr, &r0, &t1);
- regs[r0] = t1;
- break;
-
/* Load/store operations (64 bit). */
case INDEX_op_ld32s_i64:
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(int32_t *)ptr;
break;
case INDEX_op_ld_i64:
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(uint64_t *)ptr;
break;
case INDEX_op_st_i64:
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
*(uint64_t *)ptr = regs[r0];
break;
@@ -784,71 +657,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (64 bit). */
case INDEX_op_div_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2];
break;
case INDEX_op_divu_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2];
break;
case INDEX_op_rem_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2];
break;
case INDEX_op_remu_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
break;
/* Shift/rotate operations (64 bit). */
case INDEX_op_shl_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] << (regs[r2] & 63);
break;
case INDEX_op_shr_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] >> (regs[r2] & 63);
break;
case INDEX_op_sar_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63);
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = rol64(regs[r1], regs[r2] & 63);
break;
case INDEX_op_rotr_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = ror64(regs[r1], regs[r2] & 63);
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
case INDEX_op_deposit_i64:
- tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
+ tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
break;
#endif
case INDEX_op_brcond_i64:
- tci_args_rl(&tb_ptr, &r0, &ptr);
+ tci_args_rl(insn, tb_ptr, &r0, &ptr);
if (regs[r0]) {
tb_ptr = ptr;
}
break;
case INDEX_op_ext32s_i64:
case INDEX_op_ext_i32_i64:
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (int32_t)regs[r1];
break;
case INDEX_op_ext32u_i64:
case INDEX_op_extu_i32_i64:
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (uint32_t)regs[r1];
break;
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap64(regs[r1]);
break;
#endif
@@ -857,20 +730,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* QEMU specific operations. */
case INDEX_op_exit_tb:
- tci_args_l(&tb_ptr, &ptr);
+ tci_args_l(insn, tb_ptr, &ptr);
return (uintptr_t)ptr;
case INDEX_op_goto_tb:
- tci_args_l(&tb_ptr, &ptr);
+ tci_args_l(insn, tb_ptr, &ptr);
tb_ptr = *(void **)ptr;
break;
case INDEX_op_qemu_ld_i32:
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
- tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
} else {
- tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = tci_uint64(regs[r2], regs[r1]);
}
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
@@ -906,14 +779,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_qemu_ld_i64:
if (TCG_TARGET_REG_BITS == 64) {
- tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
} else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
- tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = regs[r2];
} else {
- tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
+ tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
taddr = tci_uint64(regs[r3], regs[r2]);
+ oi = regs[r4];
}
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
@@ -964,10 +838,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_qemu_st_i32:
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
- tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
} else {
- tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = tci_uint64(regs[r2], regs[r1]);
}
tmp32 = regs[r0];
@@ -994,16 +868,17 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_qemu_st_i64:
if (TCG_TARGET_REG_BITS == 64) {
- tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
tmp64 = regs[r0];
} else {
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
- tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = regs[r2];
} else {
- tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
+ tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
taddr = tci_uint64(regs[r3], regs[r2]);
+ oi = regs[r4];
}
tmp64 = tci_uint64(regs[r1], regs[r0]);
}
@@ -1087,14 +962,14 @@ static const char *str_c(TCGCond c)
/* Disassemble TCI bytecode. */
int print_insn_tci(bfd_vma addr, disassemble_info *info)
{
- uint8_t buf[256];
- int length, status;
+ const uint32_t *tb_ptr = (const void *)(uintptr_t)addr;
const TCGOpDef *def;
const char *op_name;
+ uint32_t insn;
TCGOpcode op;
- TCGReg r0, r1, r2, r3;
+ TCGReg r0, r1, r2, r3, r4;
#if TCG_TARGET_REG_BITS == 32
- TCGReg r4, r5;
+ TCGReg r5;
#endif
tcg_target_ulong i1;
int32_t s2;
@@ -1102,71 +977,54 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
TCGMemOpIdx oi;
uint8_t pos, len;
void *ptr;
- const uint8_t *tb_ptr;
- status = info->read_memory_func(addr, buf, 2, info);
- if (status != 0) {
- info->memory_error_func(status, addr, info);
- return -1;
- }
- op = buf[0];
- length = buf[1];
+ /* TCI is always the host, so we don't need to load indirect. */
+ insn = *tb_ptr++;
- if (length < 2) {
- info->fprintf_func(info->stream, "invalid length %d", length);
- return 1;
- }
-
- status = info->read_memory_func(addr + 2, buf + 2, length - 2, info);
- if (status != 0) {
- info->memory_error_func(status, addr + 2, info);
- return -1;
- }
+ info->fprintf_func(info->stream, "%08x ", insn);
+ op = extract32(insn, 0, 8);
def = &tcg_op_defs[op];
op_name = def->name;
- tb_ptr = buf + 2;
switch (op) {
case INDEX_op_br:
case INDEX_op_exit_tb:
case INDEX_op_goto_tb:
- tci_args_l(&tb_ptr, &ptr);
+ tci_args_l(insn, tb_ptr, &ptr);
info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
break;
case INDEX_op_call:
- tci_args_nl(&tb_ptr, &len, &ptr);
+ tci_args_nl(insn, tb_ptr, &len, &ptr);
info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr);
break;
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- tci_args_rl(&tb_ptr, &r0, &ptr);
+ tci_args_rl(insn, tb_ptr, &r0, &ptr);
info->fprintf_func(info->stream, "%-12s %s,0,ne,%p",
op_name, str_r(r0), ptr);
break;
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
- tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c);
+ tci_args_rrrc(insn, &r0, &r1, &r2, &c);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s",
op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c));
break;
- case INDEX_op_tci_movi_i32:
- tci_args_ri(&tb_ptr, &r0, &i1);
+ case INDEX_op_tci_movi:
+ tci_args_ri(insn, &r0, &i1);
info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "",
op_name, str_r(r0), i1);
break;
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_tci_movi_i64:
- tci_args_rI(&tb_ptr, &r0, &i1);
- info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "",
- op_name, str_r(r0), i1);
+ case INDEX_op_tci_movl:
+ tci_args_rl(insn, tb_ptr, &r0, &ptr);
+ info->fprintf_func(info->stream, "%-12s %s,%p",
+ op_name, str_r(r0), ptr);
break;
-#endif
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
@@ -1187,7 +1045,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_st32_i64:
case INDEX_op_st_i32:
case INDEX_op_st_i64:
- tci_args_rrs(&tb_ptr, &r0, &r1, &s2);
+ tci_args_rrs(insn, &r0, &r1, &s2);
info->fprintf_func(info->stream, "%-12s %s,%s,%d",
op_name, str_r(r0), str_r(r1), s2);
break;
@@ -1214,7 +1072,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_not_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
info->fprintf_func(info->stream, "%-12s %s,%s",
op_name, str_r(r0), str_r(r1));
break;
@@ -1249,28 +1107,28 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
info->fprintf_func(info->stream, "%-12s %s,%s,%s",
op_name, str_r(r0), str_r(r1), str_r(r2));
break;
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
+ tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%d,%d",
op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
- tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c);
+ tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s",
op_name, str_r(r0), str_r(r1), str_r(r2),
str_r(r3), str_r(r4), str_c(c));
break;
case INDEX_op_mulu2_i32:
- tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s",
op_name, str_r(r0), str_r(r1),
str_r(r2), str_r(r3));
@@ -1278,7 +1136,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s",
op_name, str_r(r0), str_r(r1), str_r(r2),
str_r(r3), str_r(r4), str_r(r5));
@@ -1296,30 +1154,38 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
len += DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS);
switch (len) {
case 2:
- tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ tci_args_rrm(insn, &r0, &r1, &oi);
info->fprintf_func(info->stream, "%-12s %s,%s,%x",
op_name, str_r(r0), str_r(r1), oi);
break;
case 3:
- tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%x",
op_name, str_r(r0), str_r(r1), str_r(r2), oi);
break;
case 4:
- tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
- info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%x",
+ tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s",
op_name, str_r(r0), str_r(r1),
- str_r(r2), str_r(r3), oi);
+ str_r(r2), str_r(r3), str_r(r4));
break;
default:
g_assert_not_reached();
}
break;
+ case 0:
+ /* tcg_out_nop_fill uses zeros */
+ if (insn == 0) {
+ info->fprintf_func(info->stream, "align");
+ break;
+ }
+ /* fall through */
+
default:
info->fprintf_func(info->stream, "illegal opcode %d", op);
break;
}
- return length;
+ return sizeof(insn);
}
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index e06d4e9380..0df8384be7 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -22,20 +22,7 @@
* THE SOFTWARE.
*/
-/* TODO list:
- * - See TODO comments in code.
- */
-
-/* Marker for missing code. */
-#define TODO() \
- do { \
- fprintf(stderr, "TODO %s:%u: %s()\n", \
- __FILE__, __LINE__, __func__); \
- tcg_abort(); \
- } while (0)
-
-/* Bitfield n...m (in 32 bit value). */
-#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
+#include "../tcg-pool.c.inc"
static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
{
@@ -226,52 +213,16 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
- /* tcg_out_reloc always uses the same type, addend. */
- tcg_debug_assert(type == sizeof(tcg_target_long));
+ intptr_t diff = value - (intptr_t)(code_ptr + 1);
+
tcg_debug_assert(addend == 0);
- tcg_debug_assert(value != 0);
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_patch32(code_ptr, value);
- } else {
- tcg_patch64(code_ptr, value);
- }
- return true;
-}
-
-/* Write value (native size). */
-static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
-{
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out32(s, v);
- } else {
- tcg_out64(s, v);
- }
-}
-
-/* Write opcode. */
-static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
-{
- tcg_out8(s, op);
- tcg_out8(s, 0);
-}
-
-/* Write register. */
-static void tcg_out_r(TCGContext *s, TCGArg t0)
-{
- tcg_debug_assert(t0 < TCG_TARGET_NB_REGS);
- tcg_out8(s, t0);
-}
-
-/* Write label. */
-static void tci_out_label(TCGContext *s, TCGLabel *label)
-{
- if (label->has_value) {
- tcg_out_i(s, label->u.value);
- tcg_debug_assert(label->u.value);
- } else {
- tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0);
- s->code_ptr += sizeof(tcg_target_ulong);
+ tcg_debug_assert(type == 20);
+
+ if (diff == sextract32(diff, 0, type)) {
+ tcg_patch32(code_ptr, deposit32(*code_ptr, 32 - type, type, diff));
+ return true;
}
+ return false;
}
static void stack_bounds_check(TCGReg base, target_long offset)
@@ -285,251 +236,236 @@ static void stack_bounds_check(TCGReg base, target_long offset)
static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tci_out_label(s, l0);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_reloc(s, s->code_ptr, 20, l0, 0);
+ insn = deposit32(insn, 0, 8, op);
+ tcg_out32(s, insn);
}
static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
+ intptr_t diff;
- tcg_out_op_t(s, op);
- tcg_out_i(s, (uintptr_t)p0);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ /* Special case for exit_tb: map null -> 0. */
+ if (p0 == NULL) {
+ diff = 0;
+ } else {
+ diff = p0 - (void *)(s->code_ptr + 1);
+ tcg_debug_assert(diff != 0);
+ if (diff != sextract32(diff, 0, 20)) {
+ tcg_raise_tb_overflow(s);
+ }
+ }
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 12, 20, diff);
+ tcg_out32(s, insn);
}
static void tcg_out_op_v(TCGContext *s, TCGOpcode op)
{
- uint8_t *old_code_ptr = s->code_ptr;
-
- tcg_out_op_t(s, op);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
-static void tcg_out_op_np(TCGContext *s, TCGOpcode op,
- uint8_t n0, const void *p1)
-{
- uint8_t *old_code_ptr = s->code_ptr;
-
- tcg_out_op_t(s, op);
- tcg_out8(s, n0);
- tcg_out_i(s, (uintptr_t)p1);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out32(s, (uint8_t)op);
}
static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t i1)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out32(s, i1);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_debug_assert(i1 == sextract32(i1, 0, 20));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 20, i1);
+ tcg_out32(s, insn);
}
-#if TCG_TARGET_REG_BITS == 64
-static void tcg_out_op_rI(TCGContext *s, TCGOpcode op,
- TCGReg r0, uint64_t i1)
-{
- uint8_t *old_code_ptr = s->code_ptr;
-
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out64(s, i1);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-#endif
-
static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel *l1)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tci_out_label(s, l1);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_reloc(s, s->code_ptr, 20, l1, 0);
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGArg m2)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out32(s, m2);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_debug_assert(m2 == extract32(m2, 0, 12));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 20, 12, m2);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, intptr_t i2)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_debug_assert(i2 == (int32_t)i2);
- tcg_out32(s, i2);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_debug_assert(i2 == sextract32(i2, 0, 16));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 16, i2);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out8(s, c3);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 4, c3);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out32(s, m3);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_debug_assert(m3 == extract32(m3, 0, 12));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 12, m3);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out8(s, b3);
- tcg_out8(s, b4);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_debug_assert(b3 == extract32(b3, 0, 6));
+ tcg_debug_assert(b4 == extract32(b4, 0, 6));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 6, b3);
+ insn = deposit32(insn, 26, 6, b4);
+ tcg_out32(s, insn);
}
-static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0,
- TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4)
+static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0,
+ TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out_r(s, r3);
- tcg_out32(s, m4);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 4, r3);
+ insn = deposit32(insn, 24, 4, r4);
+ tcg_out32(s, insn);
}
#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out_r(s, r3);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 4, r3);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGCond c5)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out_r(s, r3);
- tcg_out_r(s, r4);
- tcg_out8(s, c5);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 4, r3);
+ insn = deposit32(insn, 24, 4, r4);
+ insn = deposit32(insn, 28, 4, c5);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGReg r5)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out_r(s, r3);
- tcg_out_r(s, r4);
- tcg_out_r(s, r5);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 4, r3);
+ insn = deposit32(insn, 24, 4, r4);
+ insn = deposit32(insn, 28, 4, r5);
+ tcg_out32(s, insn);
}
#endif
+static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val,
+ TCGReg base, intptr_t offset)
+{
+ stack_bounds_check(base, offset);
+ if (offset != sextract32(offset, 0, 16)) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset);
+ tcg_out_op_rrr(s, (TCG_TARGET_REG_BITS == 32
+ ? INDEX_op_add_i32 : INDEX_op_add_i64),
+ TCG_REG_TMP, TCG_REG_TMP, base);
+ base = TCG_REG_TMP;
+ offset = 0;
+ }
+ tcg_out_op_rrs(s, op, val, base, offset);
+}
+
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
intptr_t offset)
{
- stack_bounds_check(base, offset);
switch (type) {
case TCG_TYPE_I32:
- tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset);
+ tcg_out_ldst(s, INDEX_op_ld_i32, val, base, offset);
break;
#if TCG_TARGET_REG_BITS == 64
case TCG_TYPE_I64:
- tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset);
+ tcg_out_ldst(s, INDEX_op_ld_i64, val, base, offset);
break;
#endif
default:
@@ -559,22 +495,33 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
{
switch (type) {
case TCG_TYPE_I32:
- tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg);
- break;
#if TCG_TARGET_REG_BITS == 64
+ arg = (int32_t)arg;
+ /* fall through */
case TCG_TYPE_I64:
- tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg);
- break;
#endif
+ break;
default:
g_assert_not_reached();
}
+
+ if (arg == sextract32(arg, 0, 20)) {
+ tcg_out_op_ri(s, INDEX_op_tci_movi, ret, arg);
+ } else {
+ tcg_insn_unit insn = 0;
+
+ new_pool_label(s, arg, 20, s->code_ptr, 0);
+ insn = deposit32(insn, 0, 8, INDEX_op_tci_movl);
+ insn = deposit32(insn, 8, 4, ret);
+ tcg_out32(s, insn);
+ }
}
static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
{
const TCGHelperInfo *info;
uint8_t which;
+ tcg_insn_unit insn = 0;
info = g_hash_table_lookup(helper_table, (gpointer)arg);
if (info->cif->rtype == &ffi_type_void) {
@@ -586,7 +533,11 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
which = 2;
}
- tcg_out_op_np(s, INDEX_op_call, which, info);
+ new_pool_l2(s, 20, s->code_ptr, 0,
+ (uintptr_t)info->func, (uintptr_t)info->cif);
+ insn = deposit32(insn, 0, 8, INDEX_op_call);
+ insn = deposit32(insn, 8, 4, which);
+ tcg_out32(s, insn);
}
#if TCG_TARGET_REG_BITS == 64
@@ -644,8 +595,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_st_i32:
CASE_64(st32)
CASE_64(st)
- stack_bounds_check(args[1], args[2]);
- tcg_out_op_rrs(s, opc, args[0], args[1], args[2]);
+ tcg_out_ldst(s, opc, args[0], args[1], args[2]);
break;
CASE_32_64(add)
@@ -738,8 +688,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
} else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]);
} else {
- tcg_out_op_rrrrm(s, opc, args[0], args[1],
- args[2], args[3], args[4]);
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]);
+ tcg_out_op_rrrrr(s, opc, args[0], args[1],
+ args[2], args[3], TCG_REG_TMP);
}
break;
@@ -787,6 +738,11 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
return arg_ct->ct & TCG_CT_CONST;
}
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ memset(p, 0, sizeof(*p) * count);
+}
+
static void tcg_target_init(TCGContext *s)
{
#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
diff --git a/tcg/tci/README b/tcg/tci/README
index 9bb7d7a5d3..f72a40a395 100644
--- a/tcg/tci/README
+++ b/tcg/tci/README
@@ -23,10 +23,12 @@ This is what TCI (Tiny Code Interpreter) does.
Like each TCG host frontend, TCI implements the code generator in
tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci.
-The additional file tcg/tci.c adds the interpreter.
+The additional file tcg/tci.c adds the interpreter and disassembler.
-The bytecode consists of opcodes (same numeric values as those used by
-TCG), command length and arguments of variable size and number.
+The bytecode consists of opcodes (with only a few exceptions, with
+the same same numeric values and semantics as used by TCG), and up
+to six arguments packed into a 32-bit integer. See comments in tci.c
+for details on the encoding.
3) Usage
@@ -39,11 +41,6 @@ suggest using this option. Setting it automatically would need
additional code in configure which must be fixed when new native TCG
implementations are added.
-System emulation should work on any 32 or 64 bit host.
-User mode emulation might work. Maybe a new linker script (*.ld)
-is needed. Byte order might be wrong (on big endian hosts)
-and need fixes in configure.
-
For hosts with native TCG, the interpreter TCI can be enabled by
configure --enable-tcg-interpreter
@@ -118,13 +115,6 @@ u1 = linux-user-test works
in the interpreter. These opcodes raise a runtime exception, so it is
possible to see where code must be added.
-* The pseudo code is not optimized and still ugly. For hosts with special
- alignment requirements, it needs some fixes (maybe aligned bytecode
- would also improve speed for hosts which support byte alignment).
-
-* A better disassembler for the pseudo code would be nice (a very primitive
- disassembler is included in tcg-target.c.inc).
-
* It might be useful to have a runtime option which selects the native TCG
or TCI, so QEMU would have to include two TCGs. Today, selecting TCI
is a configure option, so you need two compilations of QEMU.
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 62/71] tcg/tci: Implement goto_ptr
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (60 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 61/71] tcg/tci: Change encoding to uint32_t units Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 63/71] tcg/tci: Implement movcond Richard Henderson
` (9 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
This operation is critical to staying within the interpretation
loop longer, which avoids the overhead of setup and teardown for
many TBs.
The check in tcg_prologue_init is disabled because TCI does
want to use NULL to indicate exit, as opposed to branching to
a real epilogue.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target-con-set.h | 1 +
tcg/tci/tcg-target.h | 2 +-
tcg/tcg.c | 2 ++
tcg/tci.c | 19 +++++++++++++++++++
tcg/tci/tcg-target.c.inc | 16 ++++++++++++++++
5 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
index 316730f32c..ae2dc3b844 100644
--- a/tcg/tci/tcg-target-con-set.h
+++ b/tcg/tci/tcg-target-con-set.h
@@ -9,6 +9,7 @@
* Each operand should be a sequence of constraint letters as defined by
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
+C_O0_I1(r)
C_O0_I2(r, r)
C_O0_I3(r, r, r)
C_O0_I4(r, r, r, r)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index d953f2ead3..17911d3297 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -86,7 +86,7 @@
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
-#define TCG_TARGET_HAS_goto_ptr 0
+#define TCG_TARGET_HAS_goto_ptr 1
#define TCG_TARGET_HAS_direct_jump 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 92aec0d238..ce80adcfbe 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1314,10 +1314,12 @@ void tcg_prologue_init(TCGContext *s)
}
#endif
+#ifndef CONFIG_TCG_INTERPRETER
/* Assert that goto_ptr is implemented completely. */
if (TCG_TARGET_HAS_goto_ptr) {
tcg_debug_assert(tcg_code_gen_epilogue != NULL);
}
+#endif
}
void tcg_func_start(TCGContext *s)
diff --git a/tcg/tci.c b/tcg/tci.c
index 76bbf440a8..c229050c66 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -69,6 +69,11 @@ static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0)
*l0 = diff ? (void *)tb_ptr + diff : NULL;
}
+static void tci_args_r(uint32_t insn, TCGReg *r0)
+{
+ *r0 = extract32(insn, 8, 4);
+}
+
static void tci_args_nl(uint32_t insn, const void *tb_ptr,
uint8_t *n0, void **l1)
{
@@ -738,6 +743,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tb_ptr = *(void **)ptr;
break;
+ case INDEX_op_goto_ptr:
+ tci_args_r(insn, &r0);
+ ptr = (void *)regs[r0];
+ if (!ptr) {
+ return 0;
+ }
+ tb_ptr = ptr;
+ break;
+
case INDEX_op_qemu_ld_i32:
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
tci_args_rrm(insn, &r0, &r1, &oi);
@@ -995,6 +1009,11 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
break;
+ case INDEX_op_goto_ptr:
+ tci_args_r(insn, &r0);
+ info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0));
+ break;
+
case INDEX_op_call:
tci_args_nl(insn, tb_ptr, &len, &ptr);
info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 0df8384be7..db29bc6e54 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -27,6 +27,9 @@
static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
{
switch (op) {
+ case INDEX_op_goto_ptr:
+ return C_O0_I1(r);
+
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
case INDEX_op_ld16u_i32:
@@ -263,6 +266,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0)
tcg_out32(s, insn);
}
+static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0)
+{
+ tcg_insn_unit insn = 0;
+
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ tcg_out32(s, insn);
+}
+
static void tcg_out_op_v(TCGContext *s, TCGOpcode op)
{
tcg_out32(s, (uint8_t)op);
@@ -567,6 +579,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
set_jmp_reset_offset(s, args[0]);
break;
+ case INDEX_op_goto_ptr:
+ tcg_out_op_r(s, opc, args[0]);
+ break;
+
case INDEX_op_br:
tcg_out_op_l(s, opc, arg_label(args[0]));
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 63/71] tcg/tci: Implement movcond
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (61 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 62/71] tcg/tci: Implement goto_ptr Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 64/71] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
` (8 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
When this opcode is not available in the backend, tcg middle-end
will expand this as a series of 5 opcodes. So implementing this
saves bytecode space.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 4 ++--
tcg/tci.c | 16 +++++++++++++++-
tcg/tci/tcg-target.c.inc | 10 +++++++---
3 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 17911d3297..f53773a555 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -82,7 +82,7 @@
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_rot_i32 1
-#define TCG_TARGET_HAS_movcond_i32 0
+#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
@@ -119,7 +119,7 @@
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_rot_i64 1
-#define TCG_TARGET_HAS_movcond_i64 0
+#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
diff --git a/tcg/tci.c b/tcg/tci.c
index c229050c66..2391dd4d3b 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -169,6 +169,7 @@ static void tci_args_rrrr(uint32_t insn,
*r2 = extract32(insn, 16, 4);
*r3 = extract32(insn, 20, 4);
}
+#endif
static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
@@ -181,6 +182,7 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
*c5 = extract32(insn, 28, 4);
}
+#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
{
@@ -421,6 +423,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
regs[r0] = tci_compare32(regs[r1], regs[r2], condition);
break;
+ case INDEX_op_movcond_i32:
+ tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
+ tmp32 = tci_compare32(regs[r1], regs[r2], condition);
+ regs[r0] = regs[tmp32 ? r3 : r4];
+ break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
@@ -433,6 +440,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
regs[r0] = tci_compare64(regs[r1], regs[r2], condition);
break;
+ case INDEX_op_movcond_i64:
+ tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
+ tmp32 = tci_compare64(regs[r1], regs[r2], condition);
+ regs[r0] = regs[tmp32 ? r3 : r4];
+ break;
#endif
CASE_32_64(mov)
tci_args_rr(insn, &r0, &r1);
@@ -1138,7 +1150,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
break;
-#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
case INDEX_op_setcond2_i32:
tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s",
@@ -1146,6 +1159,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
str_r(r3), str_r(r4), str_c(c));
break;
+#if TCG_TARGET_REG_BITS == 32
case INDEX_op_mulu2_i32:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s",
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index db29bc6e54..a0c458a60a 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -133,9 +133,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
return C_O0_I4(r, r, r, r);
case INDEX_op_mulu2_i32:
return C_O2_I2(r, r, r, r);
+#endif
+
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
case INDEX_op_setcond2_i32:
return C_O1_I4(r, r, r, r, r);
-#endif
case INDEX_op_qemu_ld_i32:
return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
@@ -419,6 +422,7 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
insn = deposit32(insn, 20, 4, r3);
tcg_out32(s, insn);
}
+#endif
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
@@ -436,6 +440,7 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
tcg_out32(s, insn);
}
+#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGReg r5)
@@ -591,12 +596,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]);
break;
-#if TCG_TARGET_REG_BITS == 32
+ CASE_32_64(movcond)
case INDEX_op_setcond2_i32:
tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2],
args[3], args[4], args[5]);
break;
-#endif
CASE_32_64(ld8u)
CASE_32_64(ld8s)
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 64/71] tcg/tci: Implement andc, orc, eqv, nand, nor
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (62 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 63/71] tcg/tci: Implement movcond Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 65/71] tcg/tci: Implement extract, sextract Richard Henderson
` (7 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
These were already present in tcg-target.c.inc,
but not in the interpreter.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 20 ++++++++++----------
tcg/tci.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+), 10 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index f53773a555..5945272a43 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -67,20 +67,20 @@
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_andc_i32 0
+#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_extract2_i32 0
-#define TCG_TARGET_HAS_eqv_i32 0
-#define TCG_TARGET_HAS_nand_i32 0
-#define TCG_TARGET_HAS_nor_i32 0
+#define TCG_TARGET_HAS_eqv_i32 1
+#define TCG_TARGET_HAS_nand_i32 1
+#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_clz_i32 0
#define TCG_TARGET_HAS_ctz_i32 0
#define TCG_TARGET_HAS_ctpop_i32 0
#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_not_i32 1
-#define TCG_TARGET_HAS_orc_i32 0
+#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_muls2_i32 0
@@ -108,16 +108,16 @@
#define TCG_TARGET_HAS_ext8u_i64 1
#define TCG_TARGET_HAS_ext16u_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
-#define TCG_TARGET_HAS_andc_i64 0
-#define TCG_TARGET_HAS_eqv_i64 0
-#define TCG_TARGET_HAS_nand_i64 0
-#define TCG_TARGET_HAS_nor_i64 0
+#define TCG_TARGET_HAS_andc_i64 1
+#define TCG_TARGET_HAS_eqv_i64 1
+#define TCG_TARGET_HAS_nand_i64 1
+#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_clz_i64 0
#define TCG_TARGET_HAS_ctz_i64 0
#define TCG_TARGET_HAS_ctpop_i64 0
#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_not_i64 1
-#define TCG_TARGET_HAS_orc_i64 0
+#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_muls2_i64 0
diff --git a/tcg/tci.c b/tcg/tci.c
index 2391dd4d3b..02fad3370d 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -530,6 +530,36 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] ^ regs[r2];
break;
+#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64
+ CASE_32_64(andc)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] & ~regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64
+ CASE_32_64(orc)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] | ~regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64
+ CASE_32_64(eqv)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = ~(regs[r1] ^ regs[r2]);
+ break;
+#endif
+#if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64
+ CASE_32_64(nand)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = ~(regs[r1] & regs[r2]);
+ break;
+#endif
+#if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64
+ CASE_32_64(nor)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = ~(regs[r1] | regs[r2]);
+ break;
+#endif
/* Arithmetic operations (32 bit). */
@@ -1120,6 +1150,16 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ case INDEX_op_orc_i32:
+ case INDEX_op_orc_i64:
+ case INDEX_op_eqv_i32:
+ case INDEX_op_eqv_i64:
+ case INDEX_op_nand_i32:
+ case INDEX_op_nand_i64:
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
case INDEX_op_div_i32:
case INDEX_op_div_i64:
case INDEX_op_rem_i32:
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 65/71] tcg/tci: Implement extract, sextract
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (63 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 64/71] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 66/71] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
` (6 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 8 ++++----
tcg/tci.c | 42 ++++++++++++++++++++++++++++++++++++++++
tcg/tci/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++
3 files changed, 78 insertions(+), 4 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 5945272a43..60b67b196b 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -69,8 +69,8 @@
#define TCG_TARGET_HAS_ext16u_i32 1
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
-#define TCG_TARGET_HAS_extract_i32 0
-#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract_i32 1
+#define TCG_TARGET_HAS_sextract_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
@@ -97,8 +97,8 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_deposit_i64 1
-#define TCG_TARGET_HAS_extract_i64 0
-#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract_i64 1
+#define TCG_TARGET_HAS_sextract_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1
diff --git a/tcg/tci.c b/tcg/tci.c
index 02fad3370d..dcf8dc418f 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -122,6 +122,15 @@ static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2)
*i2 = sextract32(insn, 16, 16);
}
+static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
+ uint8_t *i2, uint8_t *i3)
+{
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *i2 = extract32(insn, 16, 6);
+ *i3 = extract32(insn, 22, 6);
+}
+
static void tci_args_rrrc(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{
@@ -609,6 +618,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
break;
+#endif
+#if TCG_TARGET_HAS_extract_i32
+ case INDEX_op_extract_i32:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = extract32(regs[r1], pos, len);
+ break;
+#endif
+#if TCG_TARGET_HAS_sextract_i32
+ case INDEX_op_sextract_i32:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = sextract32(regs[r1], pos, len);
+ break;
#endif
case INDEX_op_brcond_i32:
tci_args_rl(insn, tb_ptr, &r0, &ptr);
@@ -749,6 +770,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
break;
+#endif
+#if TCG_TARGET_HAS_extract_i64
+ case INDEX_op_extract_i64:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = extract64(regs[r1], pos, len);
+ break;
+#endif
+#if TCG_TARGET_HAS_sextract_i64
+ case INDEX_op_sextract_i64:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = sextract64(regs[r1], pos, len);
+ break;
#endif
case INDEX_op_brcond_i64:
tci_args_rl(insn, tb_ptr, &r0, &ptr);
@@ -1190,6 +1223,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
break;
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i32:
+ case INDEX_op_sextract_i64:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d",
+ op_name, str_r(r0), str_r(r1), pos, len);
+ break;
+
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
case INDEX_op_setcond2_i32:
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index a0c458a60a..cedd0328df 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -63,6 +63,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i32:
+ case INDEX_op_sextract_i64:
return C_O1_I1(r, r);
case INDEX_op_st8_i32:
@@ -352,6 +356,21 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
tcg_out32(s, insn);
}
+static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
+ TCGReg r1, uint8_t b2, uint8_t b3)
+{
+ tcg_insn_unit insn = 0;
+
+ tcg_debug_assert(b2 == extract32(b2, 0, 6));
+ tcg_debug_assert(b3 == extract32(b3, 0, 6));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 6, b2);
+ insn = deposit32(insn, 22, 6, b3);
+ tcg_out32(s, insn);
+}
+
static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
{
@@ -653,6 +672,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
}
break;
+ CASE_32_64(extract) /* Optional (TCG_TARGET_HAS_extract_*). */
+ CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */
+ {
+ TCGArg pos = args[2], len = args[3];
+ TCGArg max = tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 32;
+
+ tcg_debug_assert(pos < max);
+ tcg_debug_assert(pos + len <= max);
+
+ tcg_out_op_rrbb(s, opc, args[0], args[1], pos, len);
+ }
+ break;
+
CASE_32_64(brcond)
tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32
? INDEX_op_setcond_i32 : INDEX_op_setcond_i64),
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 66/71] tcg/tci: Implement clz, ctz, ctpop
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (64 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 65/71] tcg/tci: Implement extract, sextract Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 67/71] tcg/tci: Implement mulu2, muls2 Richard Henderson
` (5 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 12 +++++------
tcg/tci.c | 44 ++++++++++++++++++++++++++++++++++++++++
tcg/tci/tcg-target.c.inc | 9 ++++++++
3 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 60b67b196b..59859bd8a6 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -75,9 +75,9 @@
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
#define TCG_TARGET_HAS_nor_i32 1
-#define TCG_TARGET_HAS_clz_i32 0
-#define TCG_TARGET_HAS_ctz_i32 0
-#define TCG_TARGET_HAS_ctpop_i32 0
+#define TCG_TARGET_HAS_clz_i32 1
+#define TCG_TARGET_HAS_ctz_i32 1
+#define TCG_TARGET_HAS_ctpop_i32 1
#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 1
@@ -112,9 +112,9 @@
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 1
#define TCG_TARGET_HAS_nor_i64 1
-#define TCG_TARGET_HAS_clz_i64 0
-#define TCG_TARGET_HAS_ctz_i64 0
-#define TCG_TARGET_HAS_ctpop_i64 0
+#define TCG_TARGET_HAS_clz_i64 1
+#define TCG_TARGET_HAS_ctz_i64 1
+#define TCG_TARGET_HAS_ctpop_i64 1
#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 1
diff --git a/tcg/tci.c b/tcg/tci.c
index dcf8dc418f..068d742a80 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -588,6 +588,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
break;
+#if TCG_TARGET_HAS_clz_i32
+ case INDEX_op_clz_i32:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ tmp32 = regs[r1];
+ regs[r0] = tmp32 ? clz32(tmp32) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctz_i32
+ case INDEX_op_ctz_i32:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ tmp32 = regs[r1];
+ regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctpop_i32
+ case INDEX_op_ctpop_i32:
+ tci_args_rr(insn, &r0, &r1);
+ regs[r0] = ctpop32(regs[r1]);
+ break;
+#endif
/* Shift/rotate operations (32 bit). */
@@ -740,6 +760,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
break;
+#if TCG_TARGET_HAS_clz_i64
+ case INDEX_op_clz_i64:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctz_i64
+ case INDEX_op_ctz_i64:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctpop_i64
+ case INDEX_op_ctpop_i64:
+ tci_args_rr(insn, &r0, &r1);
+ regs[r0] = ctpop64(regs[r1]);
+ break;
+#endif
/* Shift/rotate operations (64 bit). */
@@ -1166,6 +1204,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_not_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
+ case INDEX_op_ctpop_i32:
+ case INDEX_op_ctpop_i64:
tci_args_rr(insn, &r0, &r1);
info->fprintf_func(info->stream, "%-12s %s,%s",
op_name, str_r(r0), str_r(r1));
@@ -1211,6 +1251,10 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
+ case INDEX_op_clz_i32:
+ case INDEX_op_clz_i64:
+ case INDEX_op_ctz_i32:
+ case INDEX_op_ctz_i64:
tci_args_rrr(insn, &r0, &r1, &r2);
info->fprintf_func(info->stream, "%-12s %s,%s,%s",
op_name, str_r(r0), str_r(r1), str_r(r2));
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index cedd0328df..664d715440 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -67,6 +67,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
+ case INDEX_op_ctpop_i32:
+ case INDEX_op_ctpop_i64:
return C_O1_I1(r, r);
case INDEX_op_st8_i32:
@@ -122,6 +124,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_setcond_i64:
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
+ case INDEX_op_clz_i32:
+ case INDEX_op_clz_i64:
+ case INDEX_op_ctz_i32:
+ case INDEX_op_ctz_i64:
return C_O1_I2(r, r, r);
case INDEX_op_brcond_i32:
@@ -657,6 +663,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */
CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */
CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */
+ CASE_32_64(clz) /* Optional (TCG_TARGET_HAS_clz_*). */
+ CASE_32_64(ctz) /* Optional (TCG_TARGET_HAS_ctz_*). */
tcg_out_op_rrr(s, opc, args[0], args[1], args[2]);
break;
@@ -705,6 +713,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */
CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */
CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */
+ CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */
tcg_out_op_rr(s, opc, args[0], args[1]);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 67/71] tcg/tci: Implement mulu2, muls2
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (65 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 66/71] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 68/71] tcg/tci: Implement add2, sub2 Richard Henderson
` (4 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
We already had mulu2_i32 for a 32-bit host; expand this to 64-bit
hosts as well. The muls2_i32 and the 64-bit opcodes are new.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 8 ++++----
tcg/tci.c | 35 +++++++++++++++++++++++++++++------
tcg/tci/tcg-target.c.inc | 16 ++++++++++------
3 files changed, 43 insertions(+), 16 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 59859bd8a6..71a44bbfb0 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -83,7 +83,7 @@
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
-#define TCG_TARGET_HAS_muls2_i32 0
+#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_goto_ptr 1
@@ -120,13 +120,13 @@
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
-#define TCG_TARGET_HAS_muls2_i64 0
+#define TCG_TARGET_HAS_muls2_i64 1
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
-#define TCG_TARGET_HAS_mulu2_i32 0
+#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
-#define TCG_TARGET_HAS_mulu2_i64 0
+#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
#else
diff --git a/tcg/tci.c b/tcg/tci.c
index 068d742a80..d76b9f5798 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -39,7 +39,7 @@ __thread uintptr_t tci_tb_ptr;
static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
uint32_t low_index, uint64_t value)
{
- regs[low_index] = value;
+ regs[low_index] = (uint32_t)value;
regs[high_index] = value >> 32;
}
@@ -169,7 +169,6 @@ static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
*r4 = extract32(insn, 24, 4);
}
-#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrr(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
{
@@ -178,7 +177,6 @@ static void tci_args_rrrr(uint32_t insn,
*r2 = extract32(insn, 16, 4);
*r3 = extract32(insn, 20, 4);
}
-#endif
static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
@@ -670,11 +668,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 - T2);
break;
+#endif /* TCG_TARGET_REG_BITS == 32 */
+#if TCG_TARGET_HAS_mulu2_i32
case INDEX_op_mulu2_i32:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
- tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]);
+ tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3];
+ tci_write_reg64(regs, r1, r0, tmp64);
break;
-#endif /* TCG_TARGET_REG_BITS == 32 */
+#endif
+#if TCG_TARGET_HAS_muls2_i32
+ case INDEX_op_muls2_i32:
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
+ tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3];
+ tci_write_reg64(regs, r1, r0, tmp64);
+ break;
+#endif
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
CASE_32_64(ext8s)
tci_args_rr(insn, &r0, &r1);
@@ -778,6 +786,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
regs[r0] = ctpop64(regs[r1]);
break;
#endif
+#if TCG_TARGET_HAS_mulu2_i64
+ case INDEX_op_mulu2_i64:
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
+ mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]);
+ break;
+#endif
+#if TCG_TARGET_HAS_muls2_i64
+ case INDEX_op_muls2_i64:
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
+ muls64(®s[r0], ®s[r1], regs[r2], regs[r3]);
+ break;
+#endif
/* Shift/rotate operations (64 bit). */
@@ -1285,14 +1305,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
str_r(r3), str_r(r4), str_c(c));
break;
-#if TCG_TARGET_REG_BITS == 32
case INDEX_op_mulu2_i32:
+ case INDEX_op_mulu2_i64:
+ case INDEX_op_muls2_i32:
+ case INDEX_op_muls2_i64:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s",
op_name, str_r(r0), str_r(r1),
str_r(r2), str_r(r3));
break;
+#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 664d715440..eb48633fba 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -141,10 +141,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
return C_O2_I4(r, r, r, r, r, r);
case INDEX_op_brcond2_i32:
return C_O0_I4(r, r, r, r);
- case INDEX_op_mulu2_i32:
- return C_O2_I2(r, r, r, r);
#endif
+ case INDEX_op_mulu2_i32:
+ case INDEX_op_mulu2_i64:
+ case INDEX_op_muls2_i32:
+ case INDEX_op_muls2_i64:
+ return C_O2_I2(r, r, r, r);
+
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
case INDEX_op_setcond2_i32:
@@ -434,7 +438,6 @@ static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0,
tcg_out32(s, insn);
}
-#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3)
{
@@ -447,7 +450,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
insn = deposit32(insn, 20, 4, r3);
tcg_out32(s, insn);
}
-#endif
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
@@ -728,10 +730,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
args[0], args[1], args[2], args[3], args[4]);
tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[5]));
break;
- case INDEX_op_mulu2_i32:
+#endif
+
+ CASE_32_64(mulu2)
+ CASE_32_64(muls2)
tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]);
break;
-#endif
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_st_i32:
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 68/71] tcg/tci: Implement add2, sub2
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (66 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 67/71] tcg/tci: Implement mulu2, muls2 Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 69/71] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
` (3 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
We already had the 32-bit versions for a 32-bit host; expand this
to 64-bit hosts as well. The 64-bit opcodes are new.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 8 ++++----
tcg/tci.c | 40 ++++++++++++++++++++++++++--------------
tcg/tci/tcg-target.c.inc | 15 ++++++++-------
3 files changed, 38 insertions(+), 25 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 71a44bbfb0..515b3c7a56 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -121,11 +121,11 @@
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_muls2_i64 1
-#define TCG_TARGET_HAS_add2_i32 0
-#define TCG_TARGET_HAS_sub2_i32 0
+#define TCG_TARGET_HAS_add2_i32 1
+#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
-#define TCG_TARGET_HAS_add2_i64 0
-#define TCG_TARGET_HAS_sub2_i64 0
+#define TCG_TARGET_HAS_add2_i64 1
+#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
diff --git a/tcg/tci.c b/tcg/tci.c
index d76b9f5798..0240d850cf 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -189,7 +189,6 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
*c5 = extract32(insn, 28, 4);
}
-#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
{
@@ -200,7 +199,6 @@ static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
*r4 = extract32(insn, 24, 4);
*r5 = extract32(insn, 28, 4);
}
-#endif
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
{
@@ -351,17 +349,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
for (;;) {
uint32_t insn;
TCGOpcode opc;
- TCGReg r0, r1, r2, r3, r4;
+ TCGReg r0, r1, r2, r3, r4, r5;
tcg_target_ulong t1;
TCGCond condition;
target_ulong taddr;
uint8_t pos, len;
uint32_t tmp32;
uint64_t tmp64;
-#if TCG_TARGET_REG_BITS == 32
- TCGReg r5;
uint64_t T1, T2;
-#endif
TCGMemOpIdx oi;
int32_t ofs;
void *ptr;
@@ -655,20 +650,22 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tb_ptr = ptr;
}
break;
-#if TCG_TARGET_REG_BITS == 32
+#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32
case INDEX_op_add2_i32:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 + T2);
break;
+#endif
+#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32
case INDEX_op_sub2_i32:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 - T2);
break;
-#endif /* TCG_TARGET_REG_BITS == 32 */
+#endif
#if TCG_TARGET_HAS_mulu2_i32
case INDEX_op_mulu2_i32:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
@@ -798,6 +795,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
muls64(®s[r0], ®s[r1], regs[r2], regs[r3]);
break;
#endif
+#if TCG_TARGET_HAS_add2_i64
+ case INDEX_op_add2_i64:
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
+ T1 = regs[r2] + regs[r4];
+ T2 = regs[r3] + regs[r5] + (T1 < regs[r2]);
+ regs[r0] = T1;
+ regs[r1] = T2;
+ break;
+#endif
+#if TCG_TARGET_HAS_add2_i64
+ case INDEX_op_sub2_i64:
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
+ T1 = regs[r2] - regs[r4];
+ T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]);
+ regs[r0] = T1;
+ regs[r1] = T2;
+ break;
+#endif
/* Shift/rotate operations (64 bit). */
@@ -1114,10 +1129,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
const char *op_name;
uint32_t insn;
TCGOpcode op;
- TCGReg r0, r1, r2, r3, r4;
-#if TCG_TARGET_REG_BITS == 32
- TCGReg r5;
-#endif
+ TCGReg r0, r1, r2, r3, r4, r5;
tcg_target_ulong i1;
int32_t s2;
TCGCond c;
@@ -1315,15 +1327,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
str_r(r2), str_r(r3));
break;
-#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
+ case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
+ case INDEX_op_sub2_i64:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s",
op_name, str_r(r0), str_r(r1), str_r(r2),
str_r(r3), str_r(r4), str_r(r5));
break;
-#endif
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index eb48633fba..9b2e2c32a1 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -134,11 +134,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_brcond_i64:
return C_O0_I2(r, r);
-#if TCG_TARGET_REG_BITS == 32
- /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
case INDEX_op_add2_i32:
+ case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
+ case INDEX_op_sub2_i64:
return C_O2_I4(r, r, r, r, r, r);
+
+#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
return C_O0_I4(r, r, r, r);
#endif
@@ -467,7 +469,6 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
tcg_out32(s, insn);
}
-#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGReg r5)
@@ -483,7 +484,6 @@ static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
insn = deposit32(insn, 28, 4, r5);
tcg_out32(s, insn);
}
-#endif
static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val,
TCGReg base, intptr_t offset)
@@ -719,12 +719,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_op_rr(s, opc, args[0], args[1]);
break;
-#if TCG_TARGET_REG_BITS == 32
- case INDEX_op_add2_i32:
- case INDEX_op_sub2_i32:
+ CASE_32_64(add2)
+ CASE_32_64(sub2)
tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2],
args[3], args[4], args[5]);
break;
+
+#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP,
args[0], args[1], args[2], args[3], args[4]);
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 69/71] tcg/tci: Split out tci_qemu_ld, tci_qemu_st
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (67 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 68/71] tcg/tci: Implement add2, sub2 Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 70/71] tests/tcg: Increase timeout for TCI Richard Henderson
` (2 subsequent siblings)
71 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
Expand the single-use macros into the new functions.
Use cpu_ldsb_mmuidx_ra and cpu_ldsw_le_mmuidx_ra so
that the trace event receives the correct sign flag.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 215 +++++++++++++++++++-----------------------------------
1 file changed, 75 insertions(+), 140 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 0240d850cf..84bef41af3 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -284,34 +284,77 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
return result;
}
-#define qemu_ld_ub \
- cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_leuw \
- cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_leul \
- cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_leq \
- cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_beuw \
- cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_beul \
- cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_beq \
- cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_b(X) \
- cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_lew(X) \
- cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_lel(X) \
- cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_leq(X) \
- cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_bew(X) \
- cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_bel(X) \
- cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_beq(X) \
- cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
+ TCGMemOpIdx oi, const void *tb_ptr)
+{
+ uintptr_t ra = (uintptr_t)tb_ptr;
+ int mmu_idx = get_mmuidx(oi);
+ MemOp mop = get_memop(oi);
+
+ switch (mop & (MO_BSWAP | MO_SSIZE)) {
+ case MO_UB:
+ return cpu_ldub_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_SB:
+ return cpu_ldsb_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_LEUW:
+ return cpu_lduw_le_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_BEUW:
+ return cpu_lduw_be_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_LESW:
+ return cpu_ldsw_le_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_BESW:
+ return cpu_ldsw_be_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_LEUL:
+ return cpu_ldl_le_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_BEUL:
+ return cpu_ldl_be_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_LESL:
+ return (int32_t)cpu_ldl_le_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_BESL:
+ return (int32_t)cpu_ldl_be_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_LEQ:
+ return cpu_ldq_le_mmuidx_ra(env, taddr, mmu_idx, ra);
+ case MO_BEQ:
+ return cpu_ldq_be_mmuidx_ra(env, taddr, mmu_idx, ra);
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
+ TCGMemOpIdx oi, const void *tb_ptr)
+{
+ uintptr_t ra = (uintptr_t)tb_ptr;
+ int mmu_idx = get_mmuidx(oi);
+ MemOp mop = get_memop(oi);
+
+ switch (mop & (MO_BSWAP | MO_SIZE)) {
+ case MO_UB:
+ cpu_stb_mmuidx_ra(env, taddr, val, mmu_idx, ra);
+ break;
+ case MO_LEUW:
+ cpu_stw_le_mmuidx_ra(env, taddr, val, mmu_idx, ra);
+ break;
+ case MO_BEUW:
+ cpu_stw_be_mmuidx_ra(env, taddr, val, mmu_idx, ra);
+ break;
+ case MO_LEUL:
+ cpu_stl_le_mmuidx_ra(env, taddr, val, mmu_idx, ra);
+ break;
+ case MO_BEUL:
+ cpu_stl_be_mmuidx_ra(env, taddr, val, mmu_idx, ra);
+ break;
+ case MO_LEQ:
+ cpu_stq_le_mmuidx_ra(env, taddr, val, mmu_idx, ra);
+ break;
+ case MO_BEQ:
+ cpu_stq_be_mmuidx_ra(env, taddr, val, mmu_idx, ra);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
#if TCG_TARGET_REG_BITS == 64
# define CASE_32_64(x) \
@@ -908,34 +951,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = tci_uint64(regs[r2], regs[r1]);
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
- case MO_UB:
- tmp32 = qemu_ld_ub;
- break;
- case MO_SB:
- tmp32 = (int8_t)qemu_ld_ub;
- break;
- case MO_LEUW:
- tmp32 = qemu_ld_leuw;
- break;
- case MO_LESW:
- tmp32 = (int16_t)qemu_ld_leuw;
- break;
- case MO_LEUL:
- tmp32 = qemu_ld_leul;
- break;
- case MO_BEUW:
- tmp32 = qemu_ld_beuw;
- break;
- case MO_BESW:
- tmp32 = (int16_t)qemu_ld_beuw;
- break;
- case MO_BEUL:
- tmp32 = qemu_ld_beul;
- break;
- default:
- g_assert_not_reached();
- }
+ tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr);
regs[r0] = tmp32;
break;
@@ -951,46 +967,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
taddr = tci_uint64(regs[r3], regs[r2]);
oi = regs[r4];
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
- case MO_UB:
- tmp64 = qemu_ld_ub;
- break;
- case MO_SB:
- tmp64 = (int8_t)qemu_ld_ub;
- break;
- case MO_LEUW:
- tmp64 = qemu_ld_leuw;
- break;
- case MO_LESW:
- tmp64 = (int16_t)qemu_ld_leuw;
- break;
- case MO_LEUL:
- tmp64 = qemu_ld_leul;
- break;
- case MO_LESL:
- tmp64 = (int32_t)qemu_ld_leul;
- break;
- case MO_LEQ:
- tmp64 = qemu_ld_leq;
- break;
- case MO_BEUW:
- tmp64 = qemu_ld_beuw;
- break;
- case MO_BESW:
- tmp64 = (int16_t)qemu_ld_beuw;
- break;
- case MO_BEUL:
- tmp64 = qemu_ld_beul;
- break;
- case MO_BESL:
- tmp64 = (int32_t)qemu_ld_beul;
- break;
- case MO_BEQ:
- tmp64 = qemu_ld_beq;
- break;
- default:
- g_assert_not_reached();
- }
+ tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr);
if (TCG_TARGET_REG_BITS == 32) {
tci_write_reg64(regs, r1, r0, tmp64);
} else {
@@ -1007,25 +984,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
taddr = tci_uint64(regs[r2], regs[r1]);
}
tmp32 = regs[r0];
- switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
- case MO_UB:
- qemu_st_b(tmp32);
- break;
- case MO_LEUW:
- qemu_st_lew(tmp32);
- break;
- case MO_LEUL:
- qemu_st_lel(tmp32);
- break;
- case MO_BEUW:
- qemu_st_bew(tmp32);
- break;
- case MO_BEUL:
- qemu_st_bel(tmp32);
- break;
- default:
- g_assert_not_reached();
- }
+ tci_qemu_st(env, taddr, tmp32, oi, tb_ptr);
break;
case INDEX_op_qemu_st_i64:
@@ -1044,31 +1003,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
tmp64 = tci_uint64(regs[r1], regs[r0]);
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
- case MO_UB:
- qemu_st_b(tmp64);
- break;
- case MO_LEUW:
- qemu_st_lew(tmp64);
- break;
- case MO_LEUL:
- qemu_st_lel(tmp64);
- break;
- case MO_LEQ:
- qemu_st_leq(tmp64);
- break;
- case MO_BEUW:
- qemu_st_bew(tmp64);
- break;
- case MO_BEUL:
- qemu_st_bel(tmp64);
- break;
- case MO_BEQ:
- qemu_st_beq(tmp64);
- break;
- default:
- g_assert_not_reached();
- }
+ tci_qemu_st(env, taddr, tmp64, oi, tb_ptr);
break;
case INDEX_op_mb:
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 70/71] tests/tcg: Increase timeout for TCI
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (68 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 69/71] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-18 6:09 ` Thomas Huth
2021-02-17 20:20 ` [PATCH v4 71/71] gitlab: Enable cross-i386 builds of TCI Richard Henderson
2021-02-17 21:37 ` [PATCH v4 00/71] TCI fixes and cleanups no-reply
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
The longest test at the moment seems to be a (slower)
aarch64 host, for which test-mmap takes 64 seconds.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
configure | 3 +++
tests/tcg/Makefile.target | 6 ++++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index a79b3746d4..b8924276bc 100755
--- a/configure
+++ b/configure
@@ -5797,6 +5797,9 @@ fi
if test "$optreset" = "yes" ; then
echo "HAVE_OPTRESET=y" >> $config_host_mak
fi
+if test "$tcg" = "enabled" -a "$tcg_interpreter" = "true" ; then
+ echo "CONFIG_TCG_INTERPRETER=y" >> $config_host_mak
+fi
if test "$fdatasync" = "yes" ; then
echo "CONFIG_FDATASYNC=y" >> $config_host_mak
fi
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index 24d75a5801..fa5813192a 100644
--- a/tests/tcg/Makefile.target
+++ b/tests/tcg/Makefile.target
@@ -77,8 +77,10 @@ LDFLAGS=
QEMU_OPTS=
-# If TCG debugging is enabled things are a lot slower
-ifeq ($(CONFIG_DEBUG_TCG),y)
+# If TCG debugging, or TCI is enabled things are a lot slower
+ifneq ($(CONFIG_TCG_INTERPRETER),)
+TIMEOUT=90
+else ifneq ($(CONFIG_DEBUG_TCG),)
TIMEOUT=60
else
TIMEOUT=15
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v4 71/71] gitlab: Enable cross-i386 builds of TCI
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (69 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 70/71] tests/tcg: Increase timeout for TCI Richard Henderson
@ 2021-02-17 20:20 ` Richard Henderson
2021-02-18 6:19 ` Thomas Huth
2021-02-17 21:37 ` [PATCH v4 00/71] TCI fixes and cleanups no-reply
71 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-17 20:20 UTC (permalink / raw)
To: qemu-devel; +Cc: sw, alex.bennee, f4bug
We're currently only testing TCI with a 64-bit host -- also test
with a 32-bit host. Enable a selection of softmmu and user-only
targets, 32-bit LE, 64-bit LE, 32-bit BE, as there are ifdefs for each.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
.gitlab-ci.d/crossbuilds.yml | 17 ++++++++++++++---
.../docker/dockerfiles/fedora-i386-cross.docker | 1 +
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
index 66547b6683..99300f786b 100644
--- a/.gitlab-ci.d/crossbuilds.yml
+++ b/.gitlab-ci.d/crossbuilds.yml
@@ -6,7 +6,8 @@
- mkdir build
- cd build
- PKG_CONFIG_PATH=$PKG_CONFIG_PATH
- ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-user
+ ../configure --enable-werror $QEMU_CONFIGURE_OPTS $ACCEL_CONFIGURE_OPTS
+ --disable-user
--target-list-exclude="arm-softmmu cris-softmmu i386-softmmu
microblaze-softmmu mips-softmmu mipsel-softmmu mips64-softmmu
ppc-softmmu sh4-softmmu xtensa-softmmu"
@@ -27,7 +28,7 @@
- PKG_CONFIG_PATH=$PKG_CONFIG_PATH
../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-tools
--enable-${ACCEL:-kvm} $ACCEL_CONFIGURE_OPTS
- - make -j$(expr $(nproc) + 1) all check-build
+ - make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS
.cross_user_build_job:
stage: build
@@ -36,7 +37,8 @@
- mkdir build
- cd build
- PKG_CONFIG_PATH=$PKG_CONFIG_PATH
- ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-system
+ ../configure --enable-werror $QEMU_CONFIGURE_OPTS $ACCEL_CONFIGURE_OPTS
+ --disable-system
- make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS
cross-armel-system:
@@ -81,6 +83,15 @@ cross-i386-user:
IMAGE: fedora-i386-cross
MAKE_CHECK_ARGS: check
+cross-i386-tci:
+ extends: .cross_accel_build_job
+ timeout: 60m
+ variables:
+ IMAGE: fedora-i386-cross
+ ACCEL: tcg-interpreter
+ ACCEL_CONFIGURE_OPTS: --target-list=i386-softmmu,i386-linux-user,aarch64-softmmu,aarch64-linux-user,ppc-softmmu,ppc-linux-user
+ MAKE_CHECK_ARGS: check
+
cross-mips-system:
extends: .cross_system_build_job
variables:
diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/docker/dockerfiles/fedora-i386-cross.docker
index a6e411291b..aa66314c65 100644
--- a/tests/docker/dockerfiles/fedora-i386-cross.docker
+++ b/tests/docker/dockerfiles/fedora-i386-cross.docker
@@ -5,6 +5,7 @@ ENV PACKAGES \
findutils \
gcc \
git \
+ libffi-devel.i686 \
libtasn1-devel.i686 \
libzstd-devel.i686 \
make \
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* Re: [PATCH v4 00/71] TCI fixes and cleanups
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
` (70 preceding siblings ...)
2021-02-17 20:20 ` [PATCH v4 71/71] gitlab: Enable cross-i386 builds of TCI Richard Henderson
@ 2021-02-17 21:37 ` no-reply
71 siblings, 0 replies; 92+ messages in thread
From: no-reply @ 2021-02-17 21:37 UTC (permalink / raw)
To: richard.henderson; +Cc: sw, alex.bennee, qemu-devel, f4bug
Patchew URL: https://patchew.org/QEMU/20210217202036.1724901-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210217202036.1724901-1-richard.henderson@linaro.org
Subject: [PATCH v4 00/71] TCI fixes and cleanups
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20210211171945.18313-1-alex.bennee@linaro.org -> patchew/20210211171945.18313-1-alex.bennee@linaro.org
- [tag update] patchew/20210213130325.14781-1-alex.bennee@linaro.org -> patchew/20210213130325.14781-1-alex.bennee@linaro.org
* [new tag] patchew/20210217202036.1724901-1-richard.henderson@linaro.org -> patchew/20210217202036.1724901-1-richard.henderson@linaro.org
Switched to a new branch 'test'
e85d152 gitlab: Enable cross-i386 builds of TCI
e125dfd tests/tcg: Increase timeout for TCI
ad8b717 tcg/tci: Split out tci_qemu_ld, tci_qemu_st
445fd0c tcg/tci: Implement add2, sub2
191eee2 tcg/tci: Implement mulu2, muls2
a35dc19 tcg/tci: Implement clz, ctz, ctpop
e7ab306 tcg/tci: Implement extract, sextract
b83da74 tcg/tci: Implement andc, orc, eqv, nand, nor
4568e34 tcg/tci: Implement movcond
e1ad4f4 tcg/tci: Implement goto_ptr
19bec07 tcg/tci: Change encoding to uint32_t units
6261272 tcg/tci: Remove tci_write_reg
b776dc6 tcg/tci: Emit setcond before brcond
c17b133 tcg/tci: Reserve r13 for a temporary
db6b59f tcg/tci: Split out tcg_out_op_r[iI]
7004982 tcg/tci: Split out tcg_out_op_np
c191fb8 tcg/tci: Split out tcg_out_op_v
1ba20d5 tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm}
e31d965 tcg/tci: Split out tcg_out_op_rrrrcl
410ecb8 tcg/tci: Split out tcg_out_op_rrrr
06327d7 tcg/tci: Split out tcg_out_op_rrrrrr
ab0f94f tcg/tci: Split out tcg_out_op_rrcl
c5ebc4e tcg/tci: Split out tcg_out_op_rrrbb
74efd89 tcg/tci: Split out tcg_out_op_rrrrrc
2e5ce8a tcg/tci: Split out tcg_out_op_rrrc
92262f4 tcg/tci: Split out tcg_out_op_rrr
8a239e2 tcg/tci: Split out tcg_out_op_rr
3e08393 tcg/tci: Split out tcg_out_op_p
de027aa tcg/tci: Split out tcg_out_op_l
158aea5 tcg/tci: Split out tcg_out_op_rrs
a8f550f tcg/tci: Push opcode emit into each case
6b16ed8 tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order
4b276e0 tcg/tci: Improve tcg_target_call_clobber_regs
03fb535 tcg/tci: Use ffi for calls
08630c0 tcg: Build ffi data structures for helpers
110290b tcg/tci: Implement the disassembler properly
af8cf82 tcg/tci: Remove tci_disas
943d70e tcg/tci: Hoist op_size checking into tci_args_*
5614808 tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm}
2869f99 tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits
3582a1c tcg/tci: Clean up deposit operations
f0171b8 tcg/tci: Split out tci_args_rrrr
7f92807 tcg/tci: Split out tci_args_rrrrrr
0b26e05 tcg/tci: Reuse tci_args_l for goto_tb
7c4a274 tcg/tci: Reuse tci_args_l for exit_tb
ab21186 tcg/tci: Reuse tci_args_l for calls.
cf103cc tcg/tci: Split out tci_args_ri and tci_args_rI
e9d843f tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl
2cf21fd tcg/tci: Split out tci_args_rrrrrc
e3d915b tcg/tci: Split out tci_args_l
7de9dbe tcg/tci: Split out tci_args_rrrc
711a66e tcg/tci: Split out tci_args_rrr
fe4f405 tcg/tci: Split out tci_args_rr
aa09a6d tcg/tci: Split out tci_args_rrs
9ecb320 tcg/tci: Rename tci_read_r to tci_read_rval
224c1a8 tcg/tci: Merge mov, not and neg operations
13d8e59 tcg/tci: Merge bswap operations
dd76922 tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64
df3e5ed tcg/tci: Merge extension operations
ba078b9 tcg/tci: Merge basic arithmetic operations
5ddef6d tcg/tci: Reduce use of tci_read_r64
18fcb82 tcg/tci: Remove tci_read_r32s
5654362 tcg/tci: Remove tci_read_r32
61d9e17 tcg/tci: Remove tci_read_r16s
f8a1a9f tcg/tci: Remove tci_read_r16
e9802a3 tcg/tci: Remove tci_read_r8s
45296e6 tcg/tci: Remove tci_read_r8
c18d3ce tcg/tci: Merge identical cases in generation
facfd9b tcg: Manage splitwx in tc_ptr_to_region_tree by hand
a476867 tcg: Split out tcg_raise_tb_overflow
2f8942c tcg/tci: Use exec/cpu_ldst.h interfaces
=== OUTPUT BEGIN ===
1/71 Checking commit 2f8942c11f7a (tcg/tci: Use exec/cpu_ldst.h interfaces)
2/71 Checking commit a4768674a7eb (tcg: Split out tcg_raise_tb_overflow)
3/71 Checking commit facfd9b9fef0 (tcg: Manage splitwx in tc_ptr_to_region_tree by hand)
4/71 Checking commit c18d3ce9381f (tcg/tci: Merge identical cases in generation)
5/71 Checking commit 45296e6a731d (tcg/tci: Remove tci_read_r8)
6/71 Checking commit e9802a3c780d (tcg/tci: Remove tci_read_r8s)
7/71 Checking commit f8a1a9f6fcb7 (tcg/tci: Remove tci_read_r16)
8/71 Checking commit 61d9e175534d (tcg/tci: Remove tci_read_r16s)
9/71 Checking commit 5654362bac78 (tcg/tci: Remove tci_read_r32)
10/71 Checking commit 18fcb82d28ef (tcg/tci: Remove tci_read_r32s)
11/71 Checking commit 5ddef6d22641 (tcg/tci: Reduce use of tci_read_r64)
12/71 Checking commit ba078b9affec (tcg/tci: Merge basic arithmetic operations)
13/71 Checking commit df3e5ed82035 (tcg/tci: Merge extension operations)
14/71 Checking commit dd76922ba15a (tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64)
15/71 Checking commit 13d8e599fb0c (tcg/tci: Merge bswap operations)
16/71 Checking commit 224c1a88d049 (tcg/tci: Merge mov, not and neg operations)
17/71 Checking commit 9ecb320de08f (tcg/tci: Rename tci_read_r to tci_read_rval)
18/71 Checking commit aa09a6dcda41 (tcg/tci: Split out tci_args_rrs)
19/71 Checking commit fe4f405a0f09 (tcg/tci: Split out tci_args_rr)
20/71 Checking commit 711a66e44072 (tcg/tci: Split out tci_args_rrr)
21/71 Checking commit 7de9dbe9e5b5 (tcg/tci: Split out tci_args_rrrc)
22/71 Checking commit e3d915b8deeb (tcg/tci: Split out tci_args_l)
23/71 Checking commit 2cf21fd9b7d4 (tcg/tci: Split out tci_args_rrrrrc)
24/71 Checking commit e9d843fe026d (tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl)
25/71 Checking commit cf103cc55285 (tcg/tci: Split out tci_args_ri and tci_args_rI)
26/71 Checking commit ab211864fc33 (tcg/tci: Reuse tci_args_l for calls.)
27/71 Checking commit 7c4a2742c8e4 (tcg/tci: Reuse tci_args_l for exit_tb)
28/71 Checking commit 0b26e05871d4 (tcg/tci: Reuse tci_args_l for goto_tb)
29/71 Checking commit 7f92807a427f (tcg/tci: Split out tci_args_rrrrrr)
30/71 Checking commit f0171b8f39f2 (tcg/tci: Split out tci_args_rrrr)
31/71 Checking commit 3582a1c54926 (tcg/tci: Clean up deposit operations)
32/71 Checking commit 2869f995d57a (tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits)
33/71 Checking commit 56148088cb2e (tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm})
34/71 Checking commit 943d70e3248c (tcg/tci: Hoist op_size checking into tci_args_*)
35/71 Checking commit af8cf82f60b0 (tcg/tci: Remove tci_disas)
36/71 Checking commit 110290b57736 (tcg/tci: Implement the disassembler properly)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#21:
deleted file mode 100644
total: 0 errors, 1 warnings, 304 lines checked
Patch 36/71 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
37/71 Checking commit 08630c07ee13 (tcg: Build ffi data structures for helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#25:
new file mode 100644
ERROR: Macros with complex values should be enclosed in parenthesis
#40: FILE: include/exec/helper-ffi.h:11:
+#define dh_ffitype_i32 &ffi_type_uint32
ERROR: Macros with complex values should be enclosed in parenthesis
#41: FILE: include/exec/helper-ffi.h:12:
+#define dh_ffitype_s32 &ffi_type_sint32
ERROR: Macros with complex values should be enclosed in parenthesis
#43: FILE: include/exec/helper-ffi.h:14:
+#define dh_ffitype_i64 &ffi_type_uint64
ERROR: Macros with complex values should be enclosed in parenthesis
#44: FILE: include/exec/helper-ffi.h:15:
+#define dh_ffitype_s64 &ffi_type_sint64
ERROR: Macros with complex values should be enclosed in parenthesis
#45: FILE: include/exec/helper-ffi.h:16:
+#define dh_ffitype_f16 &ffi_type_uint32
ERROR: Macros with complex values should be enclosed in parenthesis
#46: FILE: include/exec/helper-ffi.h:17:
+#define dh_ffitype_f32 &ffi_type_uint32
ERROR: Macros with complex values should be enclosed in parenthesis
#47: FILE: include/exec/helper-ffi.h:18:
+#define dh_ffitype_f64 &ffi_type_uint64
ERROR: Macros with complex values should be enclosed in parenthesis
#50: FILE: include/exec/helper-ffi.h:21:
+# define dh_ffitype_tl &ffi_type_uint32
ERROR: Macros with complex values should be enclosed in parenthesis
#52: FILE: include/exec/helper-ffi.h:23:
+# define dh_ffitype_tl &ffi_type_uint64
ERROR: Macros with complex values should be enclosed in parenthesis
#55: FILE: include/exec/helper-ffi.h:26:
+#define dh_ffitype_ptr &ffi_type_pointer
ERROR: Macros with complex values should be enclosed in parenthesis
#56: FILE: include/exec/helper-ffi.h:27:
+#define dh_ffitype_cptr &ffi_type_pointer
ERROR: Macros with complex values should be enclosed in parenthesis
#59: FILE: include/exec/helper-ffi.h:30:
+#define dh_ffitype_env &ffi_type_pointer
ERROR: space required after that ',' (ctx:VxV)
#63: FILE: include/exec/helper-ffi.h:34:
+ static ffi_cif glue(cif_,NAME) = { \
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#67: FILE: include/exec/helper-ffi.h:38:
+#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \
+ static ffi_type *glue(cif_args_,NAME)[1] = { dh_ffitype(t1) }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 1, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
ERROR: spaces required around that '*' (ctx:WxV)
#68: FILE: include/exec/helper-ffi.h:39:
+ static ffi_type *glue(cif_args_,NAME)[1] = { dh_ffitype(t1) }; \
^
ERROR: space required after that ',' (ctx:VxV)
#68: FILE: include/exec/helper-ffi.h:39:
+ static ffi_type *glue(cif_args_,NAME)[1] = { dh_ffitype(t1) }; \
^
ERROR: open brace '{' following function declarations go on the next line
#69: FILE: include/exec/helper-ffi.h:40:
+ static ffi_cif glue(cif_,NAME) = { \
ERROR: space required after that ',' (ctx:VxV)
#69: FILE: include/exec/helper-ffi.h:40:
+ static ffi_cif glue(cif_,NAME) = { \
^
ERROR: space required after that ',' (ctx:VxV)
#71: FILE: include/exec/helper-ffi.h:42:
+ .arg_types = glue(cif_args_,NAME), \
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#74: FILE: include/exec/helper-ffi.h:45:
+#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \
+ static ffi_type *glue(cif_args_,NAME)[2] = { \
+ dh_ffitype(t1), dh_ffitype(t2) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 2, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
ERROR: spaces required around that '*' (ctx:WxV)
#75: FILE: include/exec/helper-ffi.h:46:
+ static ffi_type *glue(cif_args_,NAME)[2] = { \
^
ERROR: space required after that ',' (ctx:VxV)
#75: FILE: include/exec/helper-ffi.h:46:
+ static ffi_type *glue(cif_args_,NAME)[2] = { \
^
ERROR: open brace '{' following function declarations go on the next line
#78: FILE: include/exec/helper-ffi.h:49:
+ static ffi_cif glue(cif_,NAME) = { \
ERROR: space required after that ',' (ctx:VxV)
#78: FILE: include/exec/helper-ffi.h:49:
+ static ffi_cif glue(cif_,NAME) = { \
^
ERROR: space required after that ',' (ctx:VxV)
#80: FILE: include/exec/helper-ffi.h:51:
+ .arg_types = glue(cif_args_,NAME), \
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#83: FILE: include/exec/helper-ffi.h:54:
+#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \
+ static ffi_type *glue(cif_args_,NAME)[3] = { \
+ dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 3, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
ERROR: spaces required around that '*' (ctx:WxV)
#84: FILE: include/exec/helper-ffi.h:55:
+ static ffi_type *glue(cif_args_,NAME)[3] = { \
^
ERROR: space required after that ',' (ctx:VxV)
#84: FILE: include/exec/helper-ffi.h:55:
+ static ffi_type *glue(cif_args_,NAME)[3] = { \
^
ERROR: open brace '{' following function declarations go on the next line
#87: FILE: include/exec/helper-ffi.h:58:
+ static ffi_cif glue(cif_,NAME) = { \
ERROR: space required after that ',' (ctx:VxV)
#87: FILE: include/exec/helper-ffi.h:58:
+ static ffi_cif glue(cif_,NAME) = { \
^
ERROR: space required after that ',' (ctx:VxV)
#89: FILE: include/exec/helper-ffi.h:60:
+ .arg_types = glue(cif_args_,NAME), \
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#92: FILE: include/exec/helper-ffi.h:63:
+#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \
+ static ffi_type *glue(cif_args_,NAME)[4] = { \
+ dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), dh_ffitype(t4) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 4, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
ERROR: spaces required around that '*' (ctx:WxV)
#93: FILE: include/exec/helper-ffi.h:64:
+ static ffi_type *glue(cif_args_,NAME)[4] = { \
^
ERROR: space required after that ',' (ctx:VxV)
#93: FILE: include/exec/helper-ffi.h:64:
+ static ffi_type *glue(cif_args_,NAME)[4] = { \
^
ERROR: open brace '{' following function declarations go on the next line
#96: FILE: include/exec/helper-ffi.h:67:
+ static ffi_cif glue(cif_,NAME) = { \
ERROR: space required after that ',' (ctx:VxV)
#96: FILE: include/exec/helper-ffi.h:67:
+ static ffi_cif glue(cif_,NAME) = { \
^
ERROR: space required after that ',' (ctx:VxV)
#98: FILE: include/exec/helper-ffi.h:69:
+ .arg_types = glue(cif_args_,NAME), \
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#101: FILE: include/exec/helper-ffi.h:72:
+#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \
+ static ffi_type *glue(cif_args_,NAME)[5] = { \
+ dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \
+ dh_ffitype(t4), dh_ffitype(t5) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 5, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
ERROR: spaces required around that '*' (ctx:WxV)
#102: FILE: include/exec/helper-ffi.h:73:
+ static ffi_type *glue(cif_args_,NAME)[5] = { \
^
ERROR: space required after that ',' (ctx:VxV)
#102: FILE: include/exec/helper-ffi.h:73:
+ static ffi_type *glue(cif_args_,NAME)[5] = { \
^
ERROR: open brace '{' following function declarations go on the next line
#106: FILE: include/exec/helper-ffi.h:77:
+ static ffi_cif glue(cif_,NAME) = { \
ERROR: space required after that ',' (ctx:VxV)
#106: FILE: include/exec/helper-ffi.h:77:
+ static ffi_cif glue(cif_,NAME) = { \
^
ERROR: space required after that ',' (ctx:VxV)
#108: FILE: include/exec/helper-ffi.h:79:
+ .arg_types = glue(cif_args_,NAME), \
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#111: FILE: include/exec/helper-ffi.h:82:
+#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \
+ static ffi_type *glue(cif_args_,NAME)[6] = { \
+ dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \
+ dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 6, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
ERROR: spaces required around that '*' (ctx:WxV)
#112: FILE: include/exec/helper-ffi.h:83:
+ static ffi_type *glue(cif_args_,NAME)[6] = { \
^
ERROR: space required after that ',' (ctx:VxV)
#112: FILE: include/exec/helper-ffi.h:83:
+ static ffi_type *glue(cif_args_,NAME)[6] = { \
^
ERROR: open brace '{' following function declarations go on the next line
#116: FILE: include/exec/helper-ffi.h:87:
+ static ffi_cif glue(cif_,NAME) = { \
ERROR: space required after that ',' (ctx:VxV)
#116: FILE: include/exec/helper-ffi.h:87:
+ static ffi_cif glue(cif_,NAME) = { \
^
ERROR: space required after that ',' (ctx:VxV)
#118: FILE: include/exec/helper-ffi.h:89:
+ .arg_types = glue(cif_args_,NAME), \
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#121: FILE: include/exec/helper-ffi.h:92:
+#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
+ static ffi_type *glue(cif_args_,NAME)[7] = { \
+ dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \
+ dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6), dh_ffitype(t7) \
+ }; \
+ static ffi_cif glue(cif_,NAME) = { \
+ .rtype = dh_ffitype(ret), .nargs = 7, \
+ .arg_types = glue(cif_args_,NAME), \
+ };
ERROR: spaces required around that '*' (ctx:WxV)
#122: FILE: include/exec/helper-ffi.h:93:
+ static ffi_type *glue(cif_args_,NAME)[7] = { \
^
ERROR: space required after that ',' (ctx:VxV)
#122: FILE: include/exec/helper-ffi.h:93:
+ static ffi_type *glue(cif_args_,NAME)[7] = { \
^
ERROR: open brace '{' following function declarations go on the next line
#126: FILE: include/exec/helper-ffi.h:97:
+ static ffi_cif glue(cif_,NAME) = { \
ERROR: space required after that ',' (ctx:VxV)
#126: FILE: include/exec/helper-ffi.h:97:
+ static ffi_cif glue(cif_,NAME) = { \
^
ERROR: space required after that ',' (ctx:VxV)
#128: FILE: include/exec/helper-ffi.h:99:
+ .arg_types = glue(cif_args_,NAME), \
^
total: 55 errors, 1 warnings, 309 lines checked
Patch 37/71 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
38/71 Checking commit 03fb53571a97 (tcg/tci: Use ffi for calls)
ERROR: spaces required around that '+' (ctx:VxV)
#93: FILE: tcg/tcg.c:2085:
+ bool is_64bit = sizemask & (1 << (i+1)*2);
^
ERROR: spaces required around that '*' (ctx:VxV)
#93: FILE: tcg/tcg.c:2085:
+ bool is_64bit = sizemask & (1 << (i+1)*2);
^
ERROR: suspect code indent for conditional statements (8, 11)
#122: FILE: tcg/tcg.c:2104:
+ if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
+ /*
total: 3 errors, 0 warnings, 387 lines checked
Patch 38/71 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
39/71 Checking commit 4b276e00585f (tcg/tci: Improve tcg_target_call_clobber_regs)
40/71 Checking commit 6b16ed82c3cb (tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order)
41/71 Checking commit a8f550f73633 (tcg/tci: Push opcode emit into each case)
42/71 Checking commit 158aea50157a (tcg/tci: Split out tcg_out_op_rrs)
43/71 Checking commit de027aa8d54a (tcg/tci: Split out tcg_out_op_l)
44/71 Checking commit 3e08393a2a94 (tcg/tci: Split out tcg_out_op_p)
45/71 Checking commit 8a239e2737b6 (tcg/tci: Split out tcg_out_op_rr)
46/71 Checking commit 92262f4db0a6 (tcg/tci: Split out tcg_out_op_rrr)
47/71 Checking commit 2e5ce8a25bff (tcg/tci: Split out tcg_out_op_rrrc)
48/71 Checking commit 74efd8927ccd (tcg/tci: Split out tcg_out_op_rrrrrc)
49/71 Checking commit c5ebc4e7dad3 (tcg/tci: Split out tcg_out_op_rrrbb)
50/71 Checking commit ab0f94f4c906 (tcg/tci: Split out tcg_out_op_rrcl)
51/71 Checking commit 06327d7aa3ca (tcg/tci: Split out tcg_out_op_rrrrrr)
52/71 Checking commit 410ecb8a8f40 (tcg/tci: Split out tcg_out_op_rrrr)
53/71 Checking commit e31d965631c6 (tcg/tci: Split out tcg_out_op_rrrrcl)
54/71 Checking commit 1ba20d596566 (tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm})
55/71 Checking commit c191fb85d058 (tcg/tci: Split out tcg_out_op_v)
56/71 Checking commit 700498232323 (tcg/tci: Split out tcg_out_op_np)
57/71 Checking commit db6b59ff016d (tcg/tci: Split out tcg_out_op_r[iI])
58/71 Checking commit c17b133aa9e4 (tcg/tci: Reserve r13 for a temporary)
59/71 Checking commit b776dc697813 (tcg/tci: Emit setcond before brcond)
60/71 Checking commit 62612727551d (tcg/tci: Remove tci_write_reg)
61/71 Checking commit 19bec07a5e12 (tcg/tci: Change encoding to uint32_t units)
62/71 Checking commit e1ad4f48baaf (tcg/tci: Implement goto_ptr)
63/71 Checking commit 4568e3455959 (tcg/tci: Implement movcond)
64/71 Checking commit b83da745d3d4 (tcg/tci: Implement andc, orc, eqv, nand, nor)
65/71 Checking commit e7ab3061f755 (tcg/tci: Implement extract, sextract)
66/71 Checking commit a35dc197d225 (tcg/tci: Implement clz, ctz, ctpop)
67/71 Checking commit 191eee2f94e6 (tcg/tci: Implement mulu2, muls2)
68/71 Checking commit 445fd0c7b411 (tcg/tci: Implement add2, sub2)
69/71 Checking commit ad8b71759c36 (tcg/tci: Split out tci_qemu_ld, tci_qemu_st)
70/71 Checking commit e125dfdfdad7 (tests/tcg: Increase timeout for TCI)
71/71 Checking commit e85d15221e70 (gitlab: Enable cross-i386 builds of TCI)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20210217202036.1724901-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
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Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 70/71] tests/tcg: Increase timeout for TCI
2021-02-17 20:20 ` [PATCH v4 70/71] tests/tcg: Increase timeout for TCI Richard Henderson
@ 2021-02-18 6:09 ` Thomas Huth
2021-02-22 6:44 ` Richard Henderson
0 siblings, 1 reply; 92+ messages in thread
From: Thomas Huth @ 2021-02-18 6:09 UTC (permalink / raw)
To: qemu-devel, Richard Henderson
On 17/02/2021 21.20, Richard Henderson wrote:
> The longest test at the moment seems to be a (slower)
> aarch64 host, for which test-mmap takes 64 seconds.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> configure | 3 +++
> tests/tcg/Makefile.target | 6 ++++--
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/configure b/configure
> index a79b3746d4..b8924276bc 100755
> --- a/configure
> +++ b/configure
> @@ -5797,6 +5797,9 @@ fi
> if test "$optreset" = "yes" ; then
> echo "HAVE_OPTRESET=y" >> $config_host_mak
> fi
> +if test "$tcg" = "enabled" -a "$tcg_interpreter" = "true" ; then
> + echo "CONFIG_TCG_INTERPRETER=y" >> $config_host_mak
> +fi
> if test "$fdatasync" = "yes" ; then
> echo "CONFIG_FDATASYNC=y" >> $config_host_mak
> fi
> diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
> index 24d75a5801..fa5813192a 100644
> --- a/tests/tcg/Makefile.target
> +++ b/tests/tcg/Makefile.target
> @@ -77,8 +77,10 @@ LDFLAGS=
> QEMU_OPTS=
>
>
> -# If TCG debugging is enabled things are a lot slower
> -ifeq ($(CONFIG_DEBUG_TCG),y)
> +# If TCG debugging, or TCI is enabled things are a lot slower
> +ifneq ($(CONFIG_TCG_INTERPRETER),)
> +TIMEOUT=90
> +else ifneq ($(CONFIG_DEBUG_TCG),)
> TIMEOUT=60
> else
> TIMEOUT=15
Reviewed-by: Thomas Huth <thuth@redhat.com>
Does it even get slower if you enable both at the same time, TCG debugging
and TCI?
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 71/71] gitlab: Enable cross-i386 builds of TCI
2021-02-17 20:20 ` [PATCH v4 71/71] gitlab: Enable cross-i386 builds of TCI Richard Henderson
@ 2021-02-18 6:19 ` Thomas Huth
0 siblings, 0 replies; 92+ messages in thread
From: Thomas Huth @ 2021-02-18 6:19 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee, f4bug
On 17/02/2021 21.20, Richard Henderson wrote:
> We're currently only testing TCI with a 64-bit host -- also test
> with a 32-bit host. Enable a selection of softmmu and user-only
> targets, 32-bit LE, 64-bit LE, 32-bit BE, as there are ifdefs for each.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> .gitlab-ci.d/crossbuilds.yml | 17 ++++++++++++++---
> .../docker/dockerfiles/fedora-i386-cross.docker | 1 +
> 2 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
> index 66547b6683..99300f786b 100644
> --- a/.gitlab-ci.d/crossbuilds.yml
> +++ b/.gitlab-ci.d/crossbuilds.yml
> @@ -6,7 +6,8 @@
> - mkdir build
> - cd build
> - PKG_CONFIG_PATH=$PKG_CONFIG_PATH
> - ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-user
> + ../configure --enable-werror $QEMU_CONFIGURE_OPTS $ACCEL_CONFIGURE_OPTS
I'd maybe call it EXTRA_CONFIGURE_OPTS instead since it could also be used
for other purposes later.
> + --disable-user
> --target-list-exclude="arm-softmmu cris-softmmu i386-softmmu
> microblaze-softmmu mips-softmmu mipsel-softmmu mips64-softmmu
> ppc-softmmu sh4-softmmu xtensa-softmmu"
> @@ -27,7 +28,7 @@
> - PKG_CONFIG_PATH=$PKG_CONFIG_PATH
> ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-tools
> --enable-${ACCEL:-kvm} $ACCEL_CONFIGURE_OPTS
> - - make -j$(expr $(nproc) + 1) all check-build
> + - make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS
>
> .cross_user_build_job:
> stage: build
> @@ -36,7 +37,8 @@
> - mkdir build
> - cd build
> - PKG_CONFIG_PATH=$PKG_CONFIG_PATH
> - ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-system
> + ../configure --enable-werror $QEMU_CONFIGURE_OPTS $ACCEL_CONFIGURE_OPTS
> + --disable-system
> - make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS
>
> cross-armel-system:
> @@ -81,6 +83,15 @@ cross-i386-user:
> IMAGE: fedora-i386-cross
> MAKE_CHECK_ARGS: check
>
> +cross-i386-tci:
> + extends: .cross_accel_build_job
> + timeout: 60m
> + variables:
> + IMAGE: fedora-i386-cross
> + ACCEL: tcg-interpreter
> + ACCEL_CONFIGURE_OPTS: --target-list=i386-softmmu,i386-linux-user,aarch64-softmmu,aarch64-linux-user,ppc-softmmu,ppc-linux-user
> + MAKE_CHECK_ARGS: check
Don't you want to run "check-tcg" here, too? (IIRC it's not included in "check")
> cross-mips-system:
> extends: .cross_system_build_job
> variables:
> diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/docker/dockerfiles/fedora-i386-cross.docker
> index a6e411291b..aa66314c65 100644
> --- a/tests/docker/dockerfiles/fedora-i386-cross.docker
> +++ b/tests/docker/dockerfiles/fedora-i386-cross.docker
> @@ -5,6 +5,7 @@ ENV PACKAGES \
> findutils \
> gcc \
> git \
> + libffi-devel.i686 \
> libtasn1-devel.i686 \
> libzstd-devel.i686 \
> make \
>
Anyway,
Acked-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 02/71] tcg: Split out tcg_raise_tb_overflow
2021-02-17 20:19 ` [PATCH v4 02/71] tcg: Split out tcg_raise_tb_overflow Richard Henderson
@ 2021-02-18 22:22 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-18 22:22 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> Allow other places in tcg to restart with a smaller tb.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tcg.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 05/71] tcg/tci: Remove tci_read_r8
2021-02-17 20:19 ` [PATCH v4 05/71] tcg/tci: Remove tci_read_r8 Richard Henderson
@ 2021-02-18 23:11 ` Philippe Mathieu-Daudé
2021-02-18 23:33 ` Richard Henderson
0 siblings, 1 reply; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-18 23:11 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> Use explicit casts for ext8u opcodes, and allow truncation
> to happen with the store for st8 opcodes.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 23 +++++------------------
> 1 file changed, 5 insertions(+), 18 deletions(-)
>
> diff --git a/tcg/tci.c b/tcg/tci.c
> index 1c667537fe..4ade0ccaf9 100644
> --- a/tcg/tci.c
> +++ b/tcg/tci.c
> @@ -78,11 +78,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
> }
> #endif
>
> -static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index)
> -{
> - return (uint8_t)tci_read_reg(regs, index);
> -}
> -
> static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index)
> {
> return (uint16_t)tci_read_reg(regs, index);
> @@ -169,14 +164,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
> return value;
> }
>
> -/* Read indexed register (8 bit) from bytecode. */
> -static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
> -{
> - uint8_t value = tci_read_reg8(regs, **tb_ptr);
> - *tb_ptr += 1;
> - return value;
> -}
> -
> #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
> /* Read indexed register (8 bit signed) from bytecode. */
> static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
> @@ -533,7 +520,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
> break;
> CASE_32_64(st8)
> - t0 = tci_read_r8(regs, &tb_ptr);
> + t0 = tci_read_r(regs, &tb_ptr);
No need for tb_ptr++ here?
> t1 = tci_read_r(regs, &tb_ptr);
> t2 = tci_read_s32(&tb_ptr);
> *(uint8_t *)(t1 + t2) = t0;
> @@ -722,8 +709,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> #if TCG_TARGET_HAS_ext8u_i32
> case INDEX_op_ext8u_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_r8(regs, &tb_ptr);
> - tci_write_reg(regs, t0, t1);
> + t1 = tci_read_r(regs, &tb_ptr);
> + tci_write_reg(regs, t0, (uint8_t)t1);
> break;
> #endif
> #if TCG_TARGET_HAS_ext16u_i32
> @@ -916,8 +903,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> #if TCG_TARGET_HAS_ext8u_i64
> case INDEX_op_ext8u_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_r8(regs, &tb_ptr);
> - tci_write_reg(regs, t0, t1);
> + t1 = tci_read_r(regs, &tb_ptr);
> + tci_write_reg(regs, t0, (uint8_t)t1);
> break;
> #endif
> #if TCG_TARGET_HAS_ext8s_i64
>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 06/71] tcg/tci: Remove tci_read_r8s
2021-02-17 20:19 ` [PATCH v4 06/71] tcg/tci: Remove tci_read_r8s Richard Henderson
@ 2021-02-18 23:12 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-18 23:12 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> Use explicit casts for ext8s opcodes.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 25 ++++---------------------
> 1 file changed, 4 insertions(+), 21 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 08/71] tcg/tci: Remove tci_read_r16s
2021-02-17 20:19 ` [PATCH v4 08/71] tcg/tci: Remove tci_read_r16s Richard Henderson
@ 2021-02-18 23:15 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-18 23:15 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> Use explicit casts for ext16s opcodes.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 26 ++++----------------------
> 1 file changed, 4 insertions(+), 22 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 10/71] tcg/tci: Remove tci_read_r32s
2021-02-17 20:19 ` [PATCH v4 10/71] tcg/tci: Remove tci_read_r32s Richard Henderson
@ 2021-02-18 23:16 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-18 23:16 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> Use explicit casts for ext32s opcodes.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 20 ++------------------
> 1 file changed, 2 insertions(+), 18 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 12/71] tcg/tci: Merge basic arithmetic operations
2021-02-17 20:19 ` [PATCH v4 12/71] tcg/tci: Merge basic arithmetic operations Richard Henderson
@ 2021-02-18 23:17 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-18 23:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> This includes add, sub, mul, and, or, xor.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 83 +++++++++++++++++--------------------------------------
> 1 file changed, 25 insertions(+), 58 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 15/71] tcg/tci: Merge bswap operations
2021-02-17 20:19 ` [PATCH v4 15/71] tcg/tci: Merge bswap operations Richard Henderson
@ 2021-02-18 23:19 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-18 23:19 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> This includes bswap16 and bswap32.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 22 ++++------------------
> 1 file changed, 4 insertions(+), 18 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 16/71] tcg/tci: Merge mov, not and neg operations
2021-02-17 20:19 ` [PATCH v4 16/71] tcg/tci: Merge mov, not and neg operations Richard Henderson
@ 2021-02-18 23:20 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-18 23:20 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 29 +++++------------------------
> 1 file changed, 5 insertions(+), 24 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 13/71] tcg/tci: Merge extension operations
2021-02-17 20:19 ` [PATCH v4 13/71] tcg/tci: Merge extension operations Richard Henderson
@ 2021-02-18 23:22 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-18 23:22 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> This includes ext8s, ext8u, ext16s, ext16u.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 44 ++++++++------------------------------------
> 1 file changed, 8 insertions(+), 36 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 04/71] tcg/tci: Merge identical cases in generation
2021-02-17 20:19 ` [PATCH v4 04/71] tcg/tci: Merge identical cases in generation Richard Henderson
@ 2021-02-18 23:24 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-18 23:24 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
> cases that are identical between 32-bit and 64-bit hosts.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci/tcg-target.c.inc | 204 ++++++++++++++-------------------------
> 1 file changed, 73 insertions(+), 131 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
But I had to split this patch to follow all the changes.
I'll send as a separate series, so if you find it useful you
can replace it.
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 05/71] tcg/tci: Remove tci_read_r8
2021-02-18 23:11 ` Philippe Mathieu-Daudé
@ 2021-02-18 23:33 ` Richard Henderson
2021-02-19 0:03 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 92+ messages in thread
From: Richard Henderson @ 2021-02-18 23:33 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: sw, alex.bennee
On 2/18/21 3:11 PM, Philippe Mathieu-Daudé wrote:
>> @@ -533,7 +520,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
>> tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
>> break;
>> CASE_32_64(st8)
>> - t0 = tci_read_r8(regs, &tb_ptr);
>> + t0 = tci_read_r(regs, &tb_ptr);
>
> No need for tb_ptr++ here?
Done in tcg_read_b, called by tci_read_r.
r~
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 05/71] tcg/tci: Remove tci_read_r8
2021-02-18 23:33 ` Richard Henderson
@ 2021-02-19 0:03 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-19 0:03 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/19/21 12:33 AM, Richard Henderson wrote:
> On 2/18/21 3:11 PM, Philippe Mathieu-Daudé wrote:
>>> @@ -533,7 +520,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
>>> tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
>>> break;
>>> CASE_32_64(st8)
>>> - t0 = tci_read_r8(regs, &tb_ptr);
>>> + t0 = tci_read_r(regs, &tb_ptr);
>>
>> No need for tb_ptr++ here?
>
> Done in tcg_read_b, called by tci_read_r.
Doh I missed it is done in tci_read_r() indeed.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 07/71] tcg/tci: Remove tci_read_r16
2021-02-17 20:19 ` [PATCH v4 07/71] tcg/tci: Remove tci_read_r16 Richard Henderson
@ 2021-02-19 0:03 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-19 0:03 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> Use explicit casts for ext16u opcodes, and allow truncation
> to happen with the store for st16 opcodes, and with the call
> for bswap16 opcodes.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 28 +++++++---------------------
> 1 file changed, 7 insertions(+), 21 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 11/71] tcg/tci: Reduce use of tci_read_r64
2021-02-17 20:19 ` [PATCH v4 11/71] tcg/tci: Reduce use of tci_read_r64 Richard Henderson
@ 2021-02-19 0:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-19 0:05 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> In all cases restricted to 64-bit hosts, tcg_read_r is
> identical. We retain the 64-bit symbol for the single
> case of INDEX_op_qemu_st_i64.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------
> 1 file changed, 42 insertions(+), 51 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 09/71] tcg/tci: Remove tci_read_r32
2021-02-17 20:19 ` [PATCH v4 09/71] tcg/tci: Remove tci_read_r32 Richard Henderson
@ 2021-02-19 0:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-19 0:06 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> Use explicit casts for ext32u opcodes, and allow truncation
> to happen for other users.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 122 ++++++++++++++++++++++++------------------------------
> 1 file changed, 54 insertions(+), 68 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 01/71] tcg/tci: Use exec/cpu_ldst.h interfaces
2021-02-17 20:19 ` [PATCH v4 01/71] tcg/tci: Use exec/cpu_ldst.h interfaces Richard Henderson
@ 2021-02-21 23:00 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 92+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-21 23:00 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: sw, alex.bennee
On 2/17/21 9:19 PM, Richard Henderson wrote:
> Use the provided cpu_ldst.h interfaces. This fixes the build vs
> the unconverted uses of g2h(), adds missed memory trace events,
> and correctly recognizes when a SIGSEGV belongs to the guest via
> set_helper_retaddr().
>
> Fixes: 3e8f1628e864
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 73 +++++++++++++++++++++----------------------------------
> 1 file changed, 28 insertions(+), 45 deletions(-)
Hit that today:
../tcg/tci.c: In function ‘tcg_qemu_tb_exec’:
../tcg/tci.c:379:37: error: passing argument 1 of ‘g2h’ makes pointer
from integer without a cast [-Werror=int-conversion]
379 | # define qemu_ld_ub ldub_p(g2h(taddr))
| ^~~~~
| |
| target_ulong {aka unsigned int}
../tcg/tci.c:1034:25: note: in expansion of macro ‘qemu_ld_ub’
1034 | tmp32 = qemu_ld_ub;
| ^~~~~~~~~~
In file included from ../tcg/tci.c:32:
include/exec/cpu_ldst.h:85:35: note: expected ‘CPUState *’ but argument
is of type ‘target_ulong’ {aka ‘unsigned int’}
85 | static inline void *g2h(CPUState *cs, abi_ptr x)
| ~~~~~~~~~~^~
../tcg/tci.c:379:33: error: too few arguments to function ‘g2h’
379 | # define qemu_ld_ub ldub_p(g2h(taddr))
| ^~~
../tcg/tci.c:1034:25: note: in expansion of macro ‘qemu_ld_ub’
1034 | tmp32 = qemu_ld_ub;
| ^~~~~~~~~~
So:
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v4 70/71] tests/tcg: Increase timeout for TCI
2021-02-18 6:09 ` Thomas Huth
@ 2021-02-22 6:44 ` Richard Henderson
0 siblings, 0 replies; 92+ messages in thread
From: Richard Henderson @ 2021-02-22 6:44 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
On 2/17/21 10:09 PM, Thomas Huth wrote:
>> -ifeq ($(CONFIG_DEBUG_TCG),y)
>> +# If TCG debugging, or TCI is enabled things are a lot slower
>> +ifneq ($(CONFIG_TCG_INTERPRETER),)
>> +TIMEOUT=90
>> +else ifneq ($(CONFIG_DEBUG_TCG),)
>> TIMEOUT=60
>> else
>> TIMEOUT=15
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
>
> Does it even get slower if you enable both at the same time, TCG debugging and
> TCI?
As it happens, my testing was with --enable-debug-tcg.
So, unless you're doing --enable-debug (-O0) testing, we should be fine.
r~
^ permalink raw reply [flat|nested] 92+ messages in thread
end of thread, other threads:[~2021-02-22 6:46 UTC | newest]
Thread overview: 92+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
2021-02-17 20:19 ` [PATCH v4 01/71] tcg/tci: Use exec/cpu_ldst.h interfaces Richard Henderson
2021-02-21 23:00 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 02/71] tcg: Split out tcg_raise_tb_overflow Richard Henderson
2021-02-18 22:22 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 03/71] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Richard Henderson
2021-02-17 20:19 ` [PATCH v4 04/71] tcg/tci: Merge identical cases in generation Richard Henderson
2021-02-18 23:24 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 05/71] tcg/tci: Remove tci_read_r8 Richard Henderson
2021-02-18 23:11 ` Philippe Mathieu-Daudé
2021-02-18 23:33 ` Richard Henderson
2021-02-19 0:03 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 06/71] tcg/tci: Remove tci_read_r8s Richard Henderson
2021-02-18 23:12 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 07/71] tcg/tci: Remove tci_read_r16 Richard Henderson
2021-02-19 0:03 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 08/71] tcg/tci: Remove tci_read_r16s Richard Henderson
2021-02-18 23:15 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 09/71] tcg/tci: Remove tci_read_r32 Richard Henderson
2021-02-19 0:06 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 10/71] tcg/tci: Remove tci_read_r32s Richard Henderson
2021-02-18 23:16 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 11/71] tcg/tci: Reduce use of tci_read_r64 Richard Henderson
2021-02-19 0:05 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 12/71] tcg/tci: Merge basic arithmetic operations Richard Henderson
2021-02-18 23:17 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 13/71] tcg/tci: Merge extension operations Richard Henderson
2021-02-18 23:22 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 14/71] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
2021-02-17 20:19 ` [PATCH v4 15/71] tcg/tci: Merge bswap operations Richard Henderson
2021-02-18 23:19 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 16/71] tcg/tci: Merge mov, not and neg operations Richard Henderson
2021-02-18 23:20 ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 17/71] tcg/tci: Rename tci_read_r to tci_read_rval Richard Henderson
2021-02-17 20:19 ` [PATCH v4 18/71] tcg/tci: Split out tci_args_rrs Richard Henderson
2021-02-17 20:19 ` [PATCH v4 19/71] tcg/tci: Split out tci_args_rr Richard Henderson
2021-02-17 20:19 ` [PATCH v4 20/71] tcg/tci: Split out tci_args_rrr Richard Henderson
2021-02-17 20:19 ` [PATCH v4 21/71] tcg/tci: Split out tci_args_rrrc Richard Henderson
2021-02-17 20:19 ` [PATCH v4 22/71] tcg/tci: Split out tci_args_l Richard Henderson
2021-02-17 20:19 ` [PATCH v4 23/71] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
2021-02-17 20:19 ` [PATCH v4 24/71] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
2021-02-17 20:19 ` [PATCH v4 25/71] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
2021-02-17 20:19 ` [PATCH v4 26/71] tcg/tci: Reuse tci_args_l for calls Richard Henderson
2021-02-17 20:19 ` [PATCH v4 27/71] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
2021-02-17 20:19 ` [PATCH v4 28/71] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
2021-02-17 20:19 ` [PATCH v4 29/71] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
2021-02-17 20:19 ` [PATCH v4 30/71] tcg/tci: Split out tci_args_rrrr Richard Henderson
2021-02-17 20:19 ` [PATCH v4 31/71] tcg/tci: Clean up deposit operations Richard Henderson
2021-02-17 20:19 ` [PATCH v4 32/71] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
2021-02-17 20:19 ` [PATCH v4 33/71] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-17 20:19 ` [PATCH v4 34/71] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
2021-02-17 20:20 ` [PATCH v4 35/71] tcg/tci: Remove tci_disas Richard Henderson
2021-02-17 20:20 ` [PATCH v4 36/71] tcg/tci: Implement the disassembler properly Richard Henderson
2021-02-17 20:20 ` [PATCH v4 37/71] tcg: Build ffi data structures for helpers Richard Henderson
2021-02-17 20:20 ` [PATCH v4 38/71] tcg/tci: Use ffi for calls Richard Henderson
2021-02-17 20:20 ` [PATCH v4 39/71] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-02-17 20:20 ` [PATCH v4 40/71] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-02-17 20:20 ` [PATCH v4 41/71] tcg/tci: Push opcode emit into each case Richard Henderson
2021-02-17 20:20 ` [PATCH v4 42/71] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
2021-02-17 20:20 ` [PATCH v4 43/71] tcg/tci: Split out tcg_out_op_l Richard Henderson
2021-02-17 20:20 ` [PATCH v4 44/71] tcg/tci: Split out tcg_out_op_p Richard Henderson
2021-02-17 20:20 ` [PATCH v4 45/71] tcg/tci: Split out tcg_out_op_rr Richard Henderson
2021-02-17 20:20 ` [PATCH v4 46/71] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
2021-02-17 20:20 ` [PATCH v4 47/71] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
2021-02-17 20:20 ` [PATCH v4 48/71] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
2021-02-17 20:20 ` [PATCH v4 49/71] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
2021-02-17 20:20 ` [PATCH v4 50/71] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
2021-02-17 20:20 ` [PATCH v4 51/71] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
2021-02-17 20:20 ` [PATCH v4 52/71] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
2021-02-17 20:20 ` [PATCH v4 53/71] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
2021-02-17 20:20 ` [PATCH v4 54/71] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-17 20:20 ` [PATCH v4 55/71] tcg/tci: Split out tcg_out_op_v Richard Henderson
2021-02-17 20:20 ` [PATCH v4 56/71] tcg/tci: Split out tcg_out_op_np Richard Henderson
2021-02-17 20:20 ` [PATCH v4 57/71] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
2021-02-17 20:20 ` [PATCH v4 58/71] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-02-17 20:20 ` [PATCH v4 59/71] tcg/tci: Emit setcond before brcond Richard Henderson
2021-02-17 20:20 ` [PATCH v4 60/71] tcg/tci: Remove tci_write_reg Richard Henderson
2021-02-17 20:20 ` [PATCH v4 61/71] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-02-17 20:20 ` [PATCH v4 62/71] tcg/tci: Implement goto_ptr Richard Henderson
2021-02-17 20:20 ` [PATCH v4 63/71] tcg/tci: Implement movcond Richard Henderson
2021-02-17 20:20 ` [PATCH v4 64/71] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-02-17 20:20 ` [PATCH v4 65/71] tcg/tci: Implement extract, sextract Richard Henderson
2021-02-17 20:20 ` [PATCH v4 66/71] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-02-17 20:20 ` [PATCH v4 67/71] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-02-17 20:20 ` [PATCH v4 68/71] tcg/tci: Implement add2, sub2 Richard Henderson
2021-02-17 20:20 ` [PATCH v4 69/71] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
2021-02-17 20:20 ` [PATCH v4 70/71] tests/tcg: Increase timeout for TCI Richard Henderson
2021-02-18 6:09 ` Thomas Huth
2021-02-22 6:44 ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 71/71] gitlab: Enable cross-i386 builds of TCI Richard Henderson
2021-02-18 6:19 ` Thomas Huth
2021-02-17 21:37 ` [PATCH v4 00/71] TCI fixes and cleanups no-reply
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