From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0766C433E0 for ; Thu, 18 Feb 2021 08:31:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B20F64E6F for ; Thu, 18 Feb 2021 08:31:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230223AbhBRIbZ convert rfc822-to-8bit (ORCPT ); Thu, 18 Feb 2021 03:31:25 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:52267 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230493AbhBRI2w (ORCPT ); Thu, 18 Feb 2021 03:28:52 -0500 Received: from xps13 (lfbn-tou-1-972-113.w86-210.abo.wanadoo.fr [86.210.203.113]) (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id D65AB240013; Thu, 18 Feb 2021 08:28:05 +0000 (UTC) Date: Thu, 18 Feb 2021 09:28:04 +0100 From: Miquel Raynal To: Shubhrajyoti Datta Cc: , , , , , Subject: Re: [PATCH v9 1/7] dt-bindings: add documentation of xilinx clocking wizard Message-ID: <20210218092804.6c78c99c@xps13> In-Reply-To: <1613623791-4598-2-git-send-email-shubhrajyoti.datta@xilinx.com> References: <1613623791-4598-1-git-send-email-shubhrajyoti.datta@xilinx.com> <1613623791-4598-2-git-send-email-shubhrajyoti.datta@xilinx.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Shubhrajyoti, Shubhrajyoti Datta wrote on Thu, 18 Feb 2021 10:19:45 +0530: > Add the devicetree binding for the xilinx clocking wizard. > > Signed-off-by: Shubhrajyoti Datta > --- > v6: > Fix a yaml warning > v7: > Add vendor prefix speed-grade > v8: > Fix the warnings > v9: > Fix the warnings > > .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > new file mode 100644 > index 0000000..d209140 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > @@ -0,0 +1,65 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Xilinx clocking wizard > + > +maintainers: > + - Shubhrajyoti Datta > + > +description: > + The clocking wizard is a soft ip clocking block of Xilinx versal. It > + reads required input clock frequencies from the devicetree and acts as clock > + clock output. > + > +properties: > + compatible: > + const: xlnx,clocking-wizard > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + clocks: > + items: > + - description: clock input > + - description: axi clock > + > + clock-names: > + items: > + - const: clk_in1 > + - const: s_axi_aclk > + > + clock-output-names: true > + > + xlnx,speed-grade: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [1, 2, 3] > + description: > + Speed grade of the device. A bit of explanation of what this describes would be welcome. Don't forget that binding are not tied to any driver implementation, these are supposed to be hardware description properties. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - clocks > + - clock-names > + - xlnx,speed-grade > + > +additionalProperties: false > + > +examples: > + - | > + clock-controller { > + compatible = "xlnx,clocking-wizard"; > + reg = <0xb0000000 0x10000>; > + #clock-cells = <1>; > + xlnx,speed-grade = <1>; > + clock-names = "clk_in1", "s_axi_aclk"; > + clocks = <&clkc 15>, <&clkc 15>; > + }; > +... Thanks, Miquèl