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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Paul Burton" <paulburton@kernel.org>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Wainer dos Santos Moschetta" <wainersm@redhat.com>,
	"Cleber Rosa" <crosa@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PULL 32/43] vt82c686: Correct vt82c686-pm I/O size
Date: Sun, 21 Feb 2021 15:34:21 +0100	[thread overview]
Message-ID: <20210221143432.2468220-33-f4bug@amsat.org> (raw)
In-Reply-To: <20210221143432.2468220-1-f4bug@amsat.org>

From: BALATON Zoltan <balaton@eik.bme.hu>

Section "Offset 4B-48 – Power Management I/O Base" describes:

 Port Address for the base of the 128-byte Power
 Management I/O Register block.

Correct the vt82c686-pm I/O region size.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu>
[PMD: Split original patch, this is part 2/4, reduced size to 128B]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/isa/vt82c686.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 7e6a07fca48..fe8ae24c421 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -176,7 +176,7 @@ static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
     apm_init(dev, &s->apm, NULL, s);
 
     memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s,
-                          "vt82c686-pm", 64);
+                          "vt82c686-pm", 128);
     memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io);
     memory_region_set_enabled(&s->io, false);
 
-- 
2.26.2



  parent reply	other threads:[~2021-02-21 14:53 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-21 14:33 [PULL 00/43] MIPS patches for 2021-02-21 Philippe Mathieu-Daudé
2021-02-21 14:33 ` [PULL 01/43] hw/mips: loongson3: Drop 'struct MemmapEntry' Philippe Mathieu-Daudé
2021-02-21 14:33 ` [PULL 02/43] hw/mips: Add a bootloader helper Philippe Mathieu-Daudé
2021-02-21 17:30   ` Philippe Mathieu-Daudé
2021-02-21 14:33 ` [PULL 03/43] hw/mips/fuloong2e: Use bl_gen_kernel_jump to generate bootloaders Philippe Mathieu-Daudé
2021-02-21 14:33 ` [PULL 04/43] hw/mips/boston: " Philippe Mathieu-Daudé
2021-02-21 14:33 ` [PULL 05/43] hw/mips/boston: Use bootloader helper to set GCRs Philippe Mathieu-Daudé
2021-02-21 14:33 ` [PULL 06/43] hw/intc/loongson_liointc: Fix per core ISR handling Philippe Mathieu-Daudé
2021-02-21 14:33 ` [PULL 07/43] tests/acceptance: Test PMON with Loongson-3A1000 CPU Philippe Mathieu-Daudé
2021-02-21 14:33 ` [PULL 08/43] target/mips: fetch code with translator_ld Philippe Mathieu-Daudé
2021-02-21 14:33 ` [PULL 09/43] target/mips: Remove access_type argument from map_address() handler Philippe Mathieu-Daudé
2021-02-21 14:33 ` [PULL 10/43] target/mips: Remove access_type argument from get_seg_physical_address Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 11/43] target/mips: Remove access_type arg from get_segctl_physical_address() Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 12/43] target/mips: Remove access_type argument from get_physical_address() Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 13/43] target/mips: Remove unused MMU definitions Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 14/43] target/mips: Replace magic value by MMU_DATA_LOAD definition Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 15/43] target/mips: Let do_translate_address() take MMUAccessType argument Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 16/43] target/mips: Let cpu_mips_translate_address() take MMUAccessType arg Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 17/43] target/mips: Let raise_mmu_exception() take MMUAccessType argument Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 18/43] target/mips: Let get_physical_address() " Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 19/43] target/mips: Let get_seg*_physical_address() take MMUAccessType arg Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 21/43] target/mips: Remove unused 'rw' argument from page_table_walk_refill() Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 22/43] target/mips: Include missing "tcg/tcg.h" header Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 23/43] target/mips: Make cpu_HI/LO registers public Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 26/43] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 27/43] target/mips: Use GPR move functions in gen_HILO1_tx79() Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 28/43] vt82c686: Move superio memory region to SuperIOConfig struct Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 29/43] vt82c686: Reorganise code Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 30/43] vt82c686: Fix SMBus IO base and configuration registers Philippe Mathieu-Daudé
2021-06-24 15:46   ` Philippe Mathieu-Daudé
2021-06-24 16:01     ` Philippe Mathieu-Daudé
2021-06-24 16:16       ` Philippe Mathieu-Daudé
2021-06-24 16:46         ` Philippe Mathieu-Daudé
2021-06-24 17:00           ` BALATON Zoltan
2021-06-24 17:29             ` Philippe Mathieu-Daudé
2021-06-24 18:01               ` BALATON Zoltan
2021-06-24 18:29                 ` BALATON Zoltan
2021-06-24 19:29                   ` Philippe Mathieu-Daudé
2021-06-24 18:38                 ` Philippe Mathieu-Daudé
2021-06-24 17:18           ` Philippe Mathieu-Daudé
2021-06-24 16:22     ` BALATON Zoltan
2021-06-24 18:37     ` BALATON Zoltan
2021-02-21 14:34 ` [PULL 31/43] vt82c686: Make vt82c686-pm an I/O tracing region Philippe Mathieu-Daudé
2021-02-21 14:34 ` Philippe Mathieu-Daudé [this message]
2021-02-21 14:34 ` [PULL 33/43] vt82c686: Correctly reset all registers to default values on reset Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 34/43] vt82c686: Fix up power management io base and config Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 35/43] vt82c686: Set user_creatable=false for VT82C686B_PM Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 36/43] vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on it Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 37/43] vt82c686: Simplify vt82c686b_realize() Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 38/43] vt82c686: Move creation of ISA devices to the ISA bridge Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 39/43] vt82c686: Remove index field of SuperIOConfig Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 40/43] vt82c686: Reduce indentation by returning early Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 41/43] vt82c686: Simplify by returning earlier Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 42/43] vt82c686: Log superio_cfg unimplemented accesses Philippe Mathieu-Daudé
2021-02-21 14:34 ` [PULL 43/43] vt82c686: Fix superio_cfg_{read,write}() functions Philippe Mathieu-Daudé
2021-02-21 17:34 ` [PULL 00/43] MIPS patches for 2021-02-21 Philippe Mathieu-Daudé

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