* [PATCH 0/8] amdgpu/pm: Powerplay API for smu
@ 2021-02-23 4:20 Darren Powell
2021-02-23 4:20 ` [PATCH 1/8] amdgpu/pm: Powerplay API for smu , added get_performance_level Darren Powell
` (7 more replies)
0 siblings, 8 replies; 14+ messages in thread
From: Darren Powell @ 2021-02-23 4:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
=== Description ===
Patches to add the Powerplay API to smu and simplify dpm/pm calling code
=== Patch Summary ===
linux: (git@gitlab.freedesktop.org:agd5f/linux.git) origin/amd-staging-drm-next @ 317990c7e076
+ linux-d0f58ed28940 0001 amdgpu/pm: Powerplay API for smu , added get_performance_level
+ linux-967cbf5a4913 0002 amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to use API
+ linux-33609db56fc2 0003 amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to use API
+ linux-b0fc029cae9a 0004 amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use API
+ linux-652a3e289f65 0005 amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor functions to use API
+ linux-543e989b1fff 0006 amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functions
+ linux-d41572ad4199 0007 amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
+ linux-6576162aaf40 0008 amdgpu/pm: Powerplay API for smu , updates to some pm functions
=== Versions ===
* Version 3 Updates
0003 Add a wrapper function to set_fan_control_mode for Powerplay API
Resolved context clashes caused by commits cc8f099288eac, 9485ed36411b7, 66727e187083f
0004 Removed smu implementation of powerplay get_power_limit, which clashed with commit dfb3bb7fccb37
Resolved context clashes caused by commits 9485ed36411b7, 766e03739bce7
0006 Updated to include new clocks vclk, dclk, od_vddgfx_offset, od_cclk added in commits 771fc82ffc710 & f40074fde207e
Added forward declaration for function smu_force_smuclk_levels to resolve clash with commit 9485ed36411b7
Resolved context clashes with commit dfb3bb7fccb37 and v3 updates to patches 0003, 0004
0007 Resolved context clashes with v3 updates to patches 0003
0008 Resolved context clashes with v3 updates to patches 0003
* Version 2 Updates
0001: updated the structure name to swsmu_pm_funcs
0003: changed error return value of smu_get_fan_control_mode to AMD_FAN_CTRL_NONE
fixed type in amdgpu_hwmon_get_pwm1_enable() print statement
fixed indent flagged by checkpatch.pl
0004: remove check for error during swsmu amdgpu_dpm_get_pp_num_states() call to match previous powerplay behaviour
0005: add comment to highlight assignment that changes uint32_t value to int
fix errors flagged by checkpatch.pl
0006: fix errors flagged by checkpatch
0007: fix errors and warnings flagged by checkpatch
=== Test System ===
* DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2)
+ ISO(Ubuntu 20.04.2 LTS)
+ Kernel(5.9.0-rc5-custom-01408-g317990c7e076)
=== Tests ===
** 0001
amdgpu_get_power_dpm_force_performance_level() <- /sys/class/drm/card0/device/power_dpm_force_performance_level
** 0002
amdgpu_dpm_set_mp1_state <- systemctl suspend
amdgpu_dpm_mode2_reset <- untested: needs Arctic Islands Hardware (VEGAx, RAVEN)
amdgpu_dpm_switch_power_profile <- untested
amdgpu_dpm_set_xgmi_pstate <- untested: amdgpu_xgmi_set_pstate():411 pstate switching disabled
amdgpu_dpm_set_df_cstate <- untested: needs ras enabled hardware
amdgpu_dpm_enable_mgpu_fan_boost <- untested: needs multi-gpu hardware
** 0003
amdgpu_hwmon_get_pwm1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1_enable
amdgpu_hwmon_set_pwm1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1_enable
amdgpu_hwmon_set_pwm1 <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1
amdgpu_hwmon_get_pwm1 <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1
amdgpu_hwmon_get_fan1_input <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_input
amdgpu_hwmon_get_fan1_target <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_target
amdgpu_hwmon_set_fan1_target <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_target
amdgpu_hwmon_get_fan1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_enable
amdgpu_hwmon_set_fan1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_enable
** 0004
amdgpu_get_power_dpm_state <- /sys/class/drm/card0/device/power_dpm_state
amdgpu_set_power_dpm_force_performance_level <- /sys/class/drm/card0/device/power_dpm_force_performance_level
amdgpu_get_pp_num_states <- /sys/class/drm/card0/device/pp_num_states
amdgpu_get_pp_cur_state <- /sys/class/drm/card0/device/pp_cur_state
amdgpu_get_pp_table <- /sys/class/drm/card0/device/pp_table
amdgpu_get_pp_features <- /sys/class/drm/card0/device/pp_features
amdgpu_hwmon_show_power_cap_max <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap_max
amdgpu_hwmon_show_power_cap <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap
amdgpu_hwmon_set_power_cap <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap
** 0005
amdgpu_dpm_baco_enter <- untested: called from runtime.pm
amdgpu_dpm_baco_exit <- untested: called from runtime.pm
amdgpu_dpm_is_baco_supported <- untested: needs other Hardware(cik, vi, soc15)
amdgpu_dpm_baco_reset <- untested: needs other Hardware(cik, vi, soc15)
** 0006
amdgpu_get_pp_dpm_sclk <- /sys/class/drm/card0/device/pp_dpm_sclk
amdgpu_set_pp_dpm_sclk <- /sys/class/drm/card0/device/pp_dpm_sclk
amdgpu_get_pp_dpm_mclk <- /sys/class/drm/card0/device/pp_dpm_mclk
amdgpu_set_pp_dpm_mclk <- /sys/class/drm/card0/device/pp_dpm_mclk
amdgpu_get_pp_dpm_socclk <- /sys/class/drm/card0/device/pp_dpm_socclk
amdgpu_set_pp_dpm_socclk <- /sys/class/drm/card0/device/pp_dpm_socclk
amdgpu_get_pp_dpm_fclk <- /sys/class/drm/card0/device/pp_dpm_fclk
amdgpu_set_pp_dpm_fclk <- /sys/class/drm/card0/device/pp_dpm_fclk
amdgpu_get_pp_dpm_dcefclk <- /sys/class/drm/card0/device/pp_dpm_dcefclk
amdgpu_set_pp_dpm_dcefclk <- /sys/class/drm/card0/device/pp_dpm_dcefclk
amdgpu_get_pp_dpm_pcie <- /sys/class/drm/card0/device/pp_dpm_pcie
amdgpu_set_pp_dpm_pcie <- /sys/class/drm/card0/device/pp_dpm_pcie
amdgpu_get_pp_dpm_vclk <- /sys/class/drm/card0/device/pp_dpm_vclk
amdgpu_set_pp_dpm_vclk <- /sys/class/drm/card0/device/pp_dpm_vclk
amdgpu_get_pp_dpm_dclk <- /sys/class/drm/card0/device/pp_dpm_dclk
amdgpu_set_pp_dpm_dclk <- /sys/class/drm/card0/device/pp_dpm_dclk
amdgpu_get_pp_power_profile_mode <- /sys/class/drm/card0/device/pp_power_profile_mode
amdgpu_set_pp_power_profile_mode <- /sys/class/drm/card0/device/pp_power_profile_mode
amdgpu_get_gpu_metrics <- /sys/class/drm/card0/device/gpu_metrics
** 0007
amdgpu_pm_compute_clocks <- untested
amdgpu_dpm_set_powergating_by_smu <- untested
amdgpu_dpm_get_mclk <- untested
amdgpu_dpm_get_sclk <- untested
** 0008
amdgpu_get_pp_od_clk_voltage <- /sys/class/drm/card0/device/pp_od_clk_voltage
amdgpu_set_pp_od_clk_voltage <- /sys/class/drm/card0/device/pp_od_clk_voltage
amdgpu_set_pp_table <- /sys/class/drm/card0/device/pp_table
amdgpu_set_power_dpm_force_performance_level <- /sys/class/drm/card0/device/power_dpm_force_performance_level
=== Summary of Untested Functions ===
** 0002
amdgpu_dpm_mode2_reset <- untested: needs Arctic Islands Hardware (VEGAx, RAVEN)
amdgpu_dpm_switch_power_profile <- untested: called during initialization
amdgpu_dpm_set_xgmi_pstate <- untested: amdgpu_xgmi_set_pstate():411 pstate switching disabled
amdgpu_dpm_set_df_cstate <- untested: needs ras enabled hardware
amdgpu_dpm_enable_mgpu_fan_boost <- untested: needs multi-gpu hardware
** 0005
amdgpu_dpm_baco_enter <- untested: called from runtime.pm
amdgpu_dpm_baco_exit <- untested: called from runtime.pm
amdgpu_dpm_is_baco_supported <- untested: needs other Hardware(cik, vi, soc15)
amdgpu_dpm_baco_reset <- untested: needs other Hardware(cik, vi, soc15)
amdgpu_get_pp_dpm_vclk <- untested: needs other Hardware
amdgpu_set_pp_dpm_vclk <- untested: needs other Hardware
amdgpu_get_pp_dpm_dclk <- untested: needs other Hardware
amdgpu_set_pp_dpm_dclk <- untested: needs other Hardware
** 0007
amdgpu_pm_compute_clocks <- untested
amdgpu_dpm_set_powergating_by_smu <- untested
amdgpu_dpm_get_mclk <- untested
amdgpu_dpm_get_sclk <- untested
** 0008
amdgpu_get_pp_od_clk_voltage <- file not found
amdgpu_set_pp_od_clk_voltage <- file not found
amdgpu_set_pp_table <- no binary data to test with
Darren Powell (8):
amdgpu/pm: Powerplay API for smu , added get_performance_level
amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to
use API
amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to
use API
amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use
API
amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor
functions to use API
amdgpu/pm: Powerplay API for smu , changes to clock and profile mode
functions
amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
amdgpu/pm: Powerplay API for smu , updates to some pm functions
.../gpu/drm/amd/include/kgd_pp_interface.h | 4 +
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 228 ++----
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 707 ++++--------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 73 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 366 +++++++--
5 files changed, 557 insertions(+), 821 deletions(-)
base-commit: 317990c7e076a0f4e4f0c3878e7e74f267ee029a
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/8] amdgpu/pm: Powerplay API for smu , added get_performance_level
2021-02-23 4:20 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
@ 2021-02-23 4:20 ` Darren Powell
2021-02-23 4:20 ` [PATCH 2/8] amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to use API Darren Powell
` (6 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Darren Powell @ 2021-02-23 4:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Darren Powell
v2: updated the structure name to swsmu_pm_funcs
Modified Functions
smu_get_performance_level() - modifed arg0 to match Powerplay API get_performance_level
Other Changes
added a new structure swsmu_dpm_funcs to hold smu functions for Powerplay API
removed special smu handling from amdgpu_get_power_dpm_force_performance_level
Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 +---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 2 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 +++++++++++-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 5fa65f191a37..ab26915add47 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -281,9 +281,7 @@ static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev))
- level = smu_get_performance_level(&adev->smu);
- else if (adev->powerplay.pp_funcs->get_performance_level)
+ if (adev->powerplay.pp_funcs->get_performance_level)
level = amdgpu_dpm_get_performance_level(adev);
else
level = adev->pm.dpm.forced_level;
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 10b0624ade65..f41be47fb125 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1320,7 +1320,7 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max);
int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
-enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
+enum amd_dpm_forced_level smu_get_performance_level(void *handle);
int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
int smu_set_display_count(struct smu_context *smu, uint32_t count);
int smu_set_ac_dc(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index d143ef1b460b..1c77444c75b5 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -46,6 +46,8 @@
#undef pr_info
#undef pr_debug
+static const struct amd_pm_funcs swsmu_pm_funcs;
+
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
{
size_t size = 0;
@@ -553,6 +555,9 @@ static int smu_early_init(void *handle)
smu->smu_baco.state = SMU_BACO_STATE_EXIT;
smu->smu_baco.platform_support = false;
+ adev->powerplay.pp_handle = smu;
+ adev->powerplay.pp_funcs = &swsmu_pm_funcs;
+
return smu_set_funcs(adev);
}
@@ -1691,8 +1696,9 @@ int smu_switch_power_profile(struct smu_context *smu,
return 0;
}
-enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
+enum amd_dpm_forced_level smu_get_performance_level(void *handle)
{
+ struct smu_context *smu = handle;
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
enum amd_dpm_forced_level level;
@@ -2723,3 +2729,7 @@ int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state)
return ret;
}
+
+static const struct amd_pm_funcs swsmu_pm_funcs = {
+ .get_performance_level = smu_get_performance_level,
+};
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/8] amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to use API
2021-02-23 4:20 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
2021-02-23 4:20 ` [PATCH 1/8] amdgpu/pm: Powerplay API for smu , added get_performance_level Darren Powell
@ 2021-02-23 4:20 ` Darren Powell
2021-02-23 4:20 ` [PATCH 3/8] amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan " Darren Powell
` (5 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Darren Powell @ 2021-02-23 4:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Darren Powell
Modified Functions
smu_set_xgmi_pstate() - modifed arg0 to match Powerplay API set_xgmi_pstate
smu_mode2_reset() - modifed arg0 to match Powerplay API asic_reset_mode_2
smu_switch_power_profile() - modifed arg0 to match Powerplay API switch_power_profile
smu_set_mp1_state() - modifed arg0 to match Powerplay API set_mp1_state
smu_set_df_cstate() - modifed arg0 to match Powerplay API set_df_cstate
smu_enable_mgpu_fan_boost() - modifed arg0 to match Powerplay API enable_mgpu_fan_boost
Other Changes
added above smu reset Powerplay functions to swsmu_dpm_funcs
removed special smu handling of above functions and called through Powerplay API
Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 46 +++++++----------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 12 +++---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 27 ++++++++++---
3 files changed, 41 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 8fb12afe3c96..df5e7b573428 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -1059,12 +1059,10 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
enum pp_mp1_state mp1_state)
{
int ret = 0;
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- if (is_support_sw_smu(adev)) {
- ret = smu_set_mp1_state(&adev->smu, mp1_state);
- } else if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->set_mp1_state) {
- ret = adev->powerplay.pp_funcs->set_mp1_state(
+ if (pp_funcs && pp_funcs->set_mp1_state) {
+ ret = pp_funcs->set_mp1_state(
adev->powerplay.pp_handle,
mp1_state);
}
@@ -1096,16 +1094,11 @@ int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev)
{
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
void *pp_handle = adev->powerplay.pp_handle;
- struct smu_context *smu = &adev->smu;
- if (is_support_sw_smu(adev)) {
- return smu_mode2_reset(smu);
- } else {
- if (!pp_funcs || !pp_funcs->asic_reset_mode_2)
- return -ENOENT;
+ if (!pp_funcs || !pp_funcs->asic_reset_mode_2)
+ return -ENOENT;
- return pp_funcs->asic_reset_mode_2(pp_handle);
- }
+ return pp_funcs->asic_reset_mode_2(pp_handle);
}
int amdgpu_dpm_baco_reset(struct amdgpu_device *adev)
@@ -1166,16 +1159,14 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
enum PP_SMC_POWER_PROFILE type,
bool en)
{
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int ret = 0;
if (amdgpu_sriov_vf(adev))
return 0;
- if (is_support_sw_smu(adev))
- ret = smu_switch_power_profile(&adev->smu, type, en);
- else if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->switch_power_profile)
- ret = adev->powerplay.pp_funcs->switch_power_profile(
+ if (pp_funcs && pp_funcs->switch_power_profile)
+ ret = pp_funcs->switch_power_profile(
adev->powerplay.pp_handle, type, en);
return ret;
@@ -1184,13 +1175,11 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
uint32_t pstate)
{
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int ret = 0;
- if (is_support_sw_smu(adev))
- ret = smu_set_xgmi_pstate(&adev->smu, pstate);
- else if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->set_xgmi_pstate)
- ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
+ if (pp_funcs && pp_funcs->set_xgmi_pstate)
+ ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
pstate);
return ret;
@@ -1202,12 +1191,8 @@ int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev,
int ret = 0;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
void *pp_handle = adev->powerplay.pp_handle;
- struct smu_context *smu = &adev->smu;
- if (is_support_sw_smu(adev))
- ret = smu_set_df_cstate(smu, cstate);
- else if (pp_funcs &&
- pp_funcs->set_df_cstate)
+ if (pp_funcs && pp_funcs->set_df_cstate)
ret = pp_funcs->set_df_cstate(pp_handle, cstate);
return ret;
@@ -1228,12 +1213,9 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev)
void *pp_handle = adev->powerplay.pp_handle;
const struct amd_pm_funcs *pp_funcs =
adev->powerplay.pp_funcs;
- struct smu_context *smu = &adev->smu;
int ret = 0;
- if (is_support_sw_smu(adev))
- ret = smu_enable_mgpu_fan_boost(smu);
- else if (pp_funcs && pp_funcs->enable_mgpu_fan_boost)
+ if (pp_funcs && pp_funcs->enable_mgpu_fan_boost)
ret = pp_funcs->enable_mgpu_fan_boost(pp_handle);
return ret;
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index f41be47fb125..d96692d9e794 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1271,7 +1271,7 @@ int smu_display_clock_voltage_request(struct smu_context *smu,
struct pp_display_clock_request *clock_req);
int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
-int smu_set_xgmi_pstate(struct smu_context *smu,
+int smu_set_xgmi_pstate(void *handle,
uint32_t pstate);
int smu_set_azalia_d3_pme(struct smu_context *smu);
@@ -1285,7 +1285,7 @@ int smu_baco_exit(struct smu_context *smu);
bool smu_mode1_reset_is_support(struct smu_context *smu);
int smu_mode1_reset(struct smu_context *smu);
-int smu_mode2_reset(struct smu_context *smu);
+int smu_mode2_reset(void *handle);
extern const struct amd_ip_funcs smu_ip_funcs;
@@ -1313,7 +1313,7 @@ extern int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
enum amd_pp_task task_id,
bool lock_needed);
-int smu_switch_power_profile(struct smu_context *smu,
+int smu_switch_power_profile(void *handle,
enum PP_SMC_POWER_PROFILE type,
bool en);
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
@@ -1329,9 +1329,9 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask);
-int smu_set_mp1_state(struct smu_context *smu,
+int smu_set_mp1_state(void *handle,
enum pp_mp1_state mp1_state);
-int smu_set_df_cstate(struct smu_context *smu,
+int smu_set_df_cstate(void *handle,
enum pp_df_cstate state);
int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
@@ -1349,7 +1349,7 @@ int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, void **table);
-int smu_enable_mgpu_fan_boost(struct smu_context *smu);
+int smu_enable_mgpu_fan_boost(void *handle);
int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state);
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 1c77444c75b5..ef1dfd1bb294 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1660,10 +1660,11 @@ int smu_handle_task(struct smu_context *smu,
return ret;
}
-int smu_switch_power_profile(struct smu_context *smu,
+int smu_switch_power_profile(void *handle,
enum PP_SMC_POWER_PROFILE type,
bool en)
{
+ struct smu_context *smu = handle;
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
long workload;
uint32_t index;
@@ -1800,9 +1801,10 @@ int smu_force_clk_levels(struct smu_context *smu,
* However, the mp1 state setting should still be granted
* even if the dpm_enabled cleared.
*/
-int smu_set_mp1_state(struct smu_context *smu,
+int smu_set_mp1_state(void *handle,
enum pp_mp1_state mp1_state)
{
+ struct smu_context *smu = handle;
uint16_t msg;
int ret;
@@ -1839,9 +1841,10 @@ int smu_set_mp1_state(struct smu_context *smu,
return ret;
}
-int smu_set_df_cstate(struct smu_context *smu,
+int smu_set_df_cstate(void *handle,
enum pp_df_cstate state)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2440,9 +2443,10 @@ int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disabl
return ret;
}
-int smu_set_xgmi_pstate(struct smu_context *smu,
+int smu_set_xgmi_pstate(void *handle,
uint32_t pstate)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2589,8 +2593,9 @@ int smu_mode1_reset(struct smu_context *smu)
return ret;
}
-int smu_mode2_reset(struct smu_context *smu)
+int smu_mode2_reset(void *handle)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled)
@@ -2701,8 +2706,9 @@ ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
return size;
}
-int smu_enable_mgpu_fan_boost(struct smu_context *smu)
+int smu_enable_mgpu_fan_boost(void *handle)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2731,5 +2737,14 @@ int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state)
}
static const struct amd_pm_funcs swsmu_pm_funcs = {
+ /* export for sysfs */
.get_performance_level = smu_get_performance_level,
+ .switch_power_profile = smu_switch_power_profile,
+ /* export to amdgpu */
+ .set_mp1_state = smu_set_mp1_state,
+ /* export to DC */
+ .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
+ .asic_reset_mode_2 = smu_mode2_reset,
+ .set_df_cstate = smu_set_df_cstate,
+ .set_xgmi_pstate = smu_set_xgmi_pstate,
};
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/8] amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to use API
2021-02-23 4:20 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
2021-02-23 4:20 ` [PATCH 1/8] amdgpu/pm: Powerplay API for smu , added get_performance_level Darren Powell
2021-02-23 4:20 ` [PATCH 2/8] amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to use API Darren Powell
@ 2021-02-23 4:20 ` Darren Powell
2021-02-23 4:20 ` [PATCH 4/8] amdgpu/pm: Powerplay API for smu , changed 9 pm power " Darren Powell
` (4 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Darren Powell @ 2021-02-23 4:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Darren Powell
v2: changed error return value of smu_get_fan_control_mode to AMD_FAN_CTRL_NONE
fixed type in amdgpu_hwmon_get_pwm1_enable() print statement
fixed indent flagged by checkpatch.pl
Modified Functions
smu_set_fan_speed_rpm() - modifed arg0 to match Powerplay API set_fan_speed_rpm
smu_get_fan_control_mode() - modifed signature to match Powerplay API get_fan_control_mode
smu_set_fan_control_mode() - modifed signature to match Powerplay API set_fan_control_mode
smu_get_fan_speed_percent() - modifed signature to match Powerplay API get_fan_speed_percent
smu_set_fan_speed_percent() - modifed signature to match Powerplay API set_fan_speed_percent
smu_get_fan_speed_rpm() - modifed arg0 to match Powerplay API get_fan_speed_rpm
Other Changes
added 6 above smu fan Powerplay functions to swsmu_dpm_funcs
removed special smu handling of above functions and called through Powerplay API
Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 95 ++++++++---------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 11 +--
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 ++++++--
3 files changed, 63 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index ab26915add47..81ebeff599e2 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2511,22 +2511,18 @@ static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- pwm_mode = smu_get_fan_control_mode(&adev->smu);
- } else {
- if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
- pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
- pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
- return -EINVAL;
- }
-
- pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+ if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
+ pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return -EINVAL;
}
+ pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
- return sprintf(buf, "%i\n", pwm_mode);
+ return sprintf(buf, "%u\n", pwm_mode);
}
static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
@@ -2551,18 +2547,14 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- smu_set_fan_control_mode(&adev->smu, value);
- } else {
- if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
- pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
- pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
- return -EINVAL;
- }
-
- amdgpu_dpm_set_fan_control_mode(adev, value);
+ if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
+ pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return -EINVAL;
}
+ amdgpu_dpm_set_fan_control_mode(adev, value);
+
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -2601,11 +2593,7 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
return err;
}
- if (is_support_sw_smu(adev))
- pwm_mode = smu_get_fan_control_mode(&adev->smu);
- else
- pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
-
+ pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
pr_info("manual fan speed control should be enabled first\n");
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
@@ -2622,9 +2610,7 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
value = (value * 100) / 255;
- if (is_support_sw_smu(adev))
- err = smu_set_fan_speed_percent(&adev->smu, value);
- else if (adev->powerplay.pp_funcs->set_fan_speed_percent)
+ if (adev->powerplay.pp_funcs->set_fan_speed_percent)
err = amdgpu_dpm_set_fan_speed_percent(adev, value);
else
err = -EINVAL;
@@ -2655,9 +2641,7 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
return err;
}
- if (is_support_sw_smu(adev))
- err = smu_get_fan_speed_percent(&adev->smu, &speed);
- else if (adev->powerplay.pp_funcs->get_fan_speed_percent)
+ if (adev->powerplay.pp_funcs->get_fan_speed_percent)
err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
else
err = -EINVAL;
@@ -2690,9 +2674,7 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
return err;
}
- if (is_support_sw_smu(adev))
- err = smu_get_fan_speed_rpm(&adev->smu, &speed);
- else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
+ if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
else
err = -EINVAL;
@@ -2783,9 +2765,7 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
return err;
}
- if (is_support_sw_smu(adev))
- err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
- else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
+ if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
else
err = -EINVAL;
@@ -2817,10 +2797,7 @@ static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
return err;
}
- if (is_support_sw_smu(adev))
- pwm_mode = smu_get_fan_control_mode(&adev->smu);
- else
- pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+ pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
@@ -2835,9 +2812,7 @@ static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
return err;
}
- if (is_support_sw_smu(adev))
- err = smu_set_fan_speed_rpm(&adev->smu, value);
- else if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
+ if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
else
err = -EINVAL;
@@ -2868,18 +2843,14 @@ static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- pwm_mode = smu_get_fan_control_mode(&adev->smu);
- } else {
- if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
- pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
- pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
- return -EINVAL;
- }
-
- pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+ if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
+ pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return -EINVAL;
}
+ pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -2916,16 +2887,12 @@ static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
return err;
}
- if (is_support_sw_smu(adev)) {
- smu_set_fan_control_mode(&adev->smu, pwm_mode);
- } else {
- if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
- pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
- pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
- return -EINVAL;
- }
- amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
+ if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
+ pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return -EINVAL;
}
+ amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index d96692d9e794..81ee621df448 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1233,7 +1233,7 @@ int smu_check_fw_status(struct smu_context *smu);
int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
-int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
+int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
@@ -1255,11 +1255,12 @@ int smu_set_power_profile_mode(struct smu_context *smu,
long *param,
uint32_t param_size,
bool lock_needed);
-int smu_get_fan_control_mode(struct smu_context *smu);
+u32 smu_get_fan_control_mode(void *handle);
int smu_set_fan_control_mode(struct smu_context *smu, int value);
-int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
-int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
-int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
+void smu_pp_set_fan_control_mode(void *handle, u32 value);
+int smu_get_fan_speed_percent(void *handle, u32 *speed);
+int smu_set_fan_speed_percent(void *handle, u32 speed);
+int smu_get_fan_speed_rpm(void *handle, uint32_t *speed);
int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index ef1dfd1bb294..b7fe56b9e33e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2029,8 +2029,9 @@ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
return ret;
}
-int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
+int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
{
+ struct smu_context *smu = handle;
u32 percent;
int ret = 0;
@@ -2265,12 +2266,13 @@ int smu_set_power_profile_mode(struct smu_context *smu,
}
-int smu_get_fan_control_mode(struct smu_context *smu)
+u32 smu_get_fan_control_mode(void *handle)
{
- int ret = 0;
+ struct smu_context *smu = handle;
+ u32 ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
- return -EOPNOTSUPP;
+ return AMD_FAN_CTRL_NONE;
mutex_lock(&smu->mutex);
@@ -2287,7 +2289,7 @@ int smu_set_fan_control_mode(struct smu_context *smu, int value)
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
- return -EOPNOTSUPP;
+ return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
@@ -2307,8 +2309,16 @@ int smu_set_fan_control_mode(struct smu_context *smu, int value)
return ret;
}
-int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
+void smu_pp_set_fan_control_mode(void *handle, u32 value) {
+ struct smu_context *smu = handle;
+
+ smu_set_fan_control_mode(smu, value);
+}
+
+
+int smu_get_fan_speed_percent(void *handle, u32 *speed)
{
+ struct smu_context *smu = handle;
int ret = 0;
uint32_t percent;
@@ -2330,8 +2340,9 @@ int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
return ret;
}
-int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+int smu_set_fan_speed_percent(void *handle, u32 speed)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2352,8 +2363,9 @@ int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
return ret;
}
-int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
+int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
{
+ struct smu_context *smu = handle;
int ret = 0;
u32 percent;
@@ -2738,7 +2750,13 @@ int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state)
static const struct amd_pm_funcs swsmu_pm_funcs = {
/* export for sysfs */
+ .set_fan_control_mode = smu_pp_set_fan_control_mode,
+ .get_fan_control_mode = smu_get_fan_control_mode,
+ .set_fan_speed_percent = smu_set_fan_speed_percent,
+ .get_fan_speed_percent = smu_get_fan_speed_percent,
.get_performance_level = smu_get_performance_level,
+ .get_fan_speed_rpm = smu_get_fan_speed_rpm,
+ .set_fan_speed_rpm = smu_set_fan_speed_rpm,
.switch_power_profile = smu_switch_power_profile,
/* export to amdgpu */
.set_mp1_state = smu_set_mp1_state,
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/8] amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use API
2021-02-23 4:20 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
` (2 preceding siblings ...)
2021-02-23 4:20 ` [PATCH 3/8] amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan " Darren Powell
@ 2021-02-23 4:20 ` Darren Powell
2021-02-23 4:20 ` [PATCH 5/8] amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor " Darren Powell
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Darren Powell @ 2021-02-23 4:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
v2: remove check for error during swsmu amdgpu_dpm_get_pp_num_states() call to match previous powerplay behaviour
v3: removed smu implementation of powerplay get_power_limit, which clashed with commit dfb3bb7fccb37
Resolved context clashes caused by commits 9485ed36411b7, 766e03739bce7
Modified Files
smu_set_power_limit() - modifed arg0 to match Powerplay API set_power_limit
smu_sys_get_pp_table() - modifed signature to match Powerplay API get_pp_table
smu_get_power_num_states() - modifed arg0 to match Powerplay API get_pp_num_states
smu_get_current_power_state() - modifed arg0 to match Powerplay API get_current_power_state
smu_sys_get_pp_feature_mask() - modifed signature to match Powerplay API get_ppfeature_status
smu_sys_set_pp_feature_mask() - modifed arg0 to match Powerplay API set_ppfeature_status
Other Changes
added 6 above smu Powerplay functions to swsmu_dpm_funcs
removed special smu handling of above functions and called through Powerplay API
Signed-off-by: Darren Powell <darren.powell@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 62 ++++++++---------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 12 ++---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 51 +++++++++++--------
3 files changed, 58 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 81ebeff599e2..34e5c4c4f280 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -125,6 +125,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
enum amd_pm_state_type pm;
int ret;
@@ -137,12 +138,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- if (adev->smu.ppt_funcs->get_current_power_state)
- pm = smu_get_current_power_state(&adev->smu);
- else
- pm = adev->pm.dpm.user_state;
- } else if (adev->powerplay.pp_funcs->get_current_power_state) {
+ if (pp_funcs->get_current_power_state) {
pm = amdgpu_dpm_get_current_power_state(adev);
} else {
pm = adev->pm.dpm.user_state;
@@ -308,6 +304,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
enum amd_dpm_forced_level level;
enum amd_dpm_forced_level current_level = 0xff;
int ret = 0;
@@ -343,9 +340,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev))
- current_level = smu_get_performance_level(&adev->smu);
- else if (adev->powerplay.pp_funcs->get_performance_level)
+ if (pp_funcs->get_performance_level)
current_level = amdgpu_dpm_get_performance_level(adev);
if (current_level == level) {
@@ -382,7 +377,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
pm_runtime_put_autosuspend(ddev->dev);
return -EINVAL;
}
- } else if (adev->powerplay.pp_funcs->force_performance_level) {
+ } else if (pp_funcs->force_performance_level) {
mutex_lock(&adev->pm.mutex);
if (adev->pm.dpm.thermal_active) {
mutex_unlock(&adev->pm.mutex);
@@ -413,6 +408,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
struct pp_states_info data;
int i, buf_len, ret;
@@ -425,11 +421,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_get_power_num_states(&adev->smu, &data);
- if (ret)
- return ret;
- } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
+ if (pp_funcs->get_pp_num_states) {
amdgpu_dpm_get_pp_num_states(adev, &data);
} else {
memset(&data, 0, sizeof(data));
@@ -455,8 +447,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
struct pp_states_info data;
- struct smu_context *smu = &adev->smu;
enum amd_pm_state_type pm = 0;
int i = 0, ret = 0;
@@ -469,13 +461,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- pm = smu_get_current_power_state(smu);
- ret = smu_get_power_num_states(smu, &data);
- if (ret)
- return ret;
- } else if (adev->powerplay.pp_funcs->get_current_power_state
- && adev->powerplay.pp_funcs->get_pp_num_states) {
+ if (pp_funcs->get_current_power_state
+ && pp_funcs->get_pp_num_states) {
pm = amdgpu_dpm_get_current_power_state(adev);
amdgpu_dpm_get_pp_num_states(adev, &data);
}
@@ -590,13 +577,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- if (size < 0)
- return size;
- } else if (adev->powerplay.pp_funcs->get_pp_table) {
+ if (adev->powerplay.pp_funcs->get_pp_table) {
size = amdgpu_dpm_get_pp_table(adev, &table);
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@@ -1010,9 +991,7 @@ static ssize_t amdgpu_get_pp_features(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev))
- size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
- else if (adev->powerplay.pp_funcs->get_ppfeature_status)
+ if (adev->powerplay.pp_funcs->get_ppfeature_status)
size = amdgpu_dpm_get_ppfeature_status(adev, buf);
else
size = snprintf(buf, PAGE_SIZE, "\n");
@@ -3024,6 +3003,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
char *buf)
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
uint32_t limit = limit_type << 24;
ssize_t size;
@@ -3041,8 +3021,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
if (is_support_sw_smu(adev)) {
smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
- } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
- adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
+ } else if (pp_funcs && pp_funcs->get_power_limit) {
+ pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
@@ -3059,6 +3039,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
char *buf)
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
uint32_t limit = limit_type << 24;
ssize_t size;
@@ -3076,8 +3057,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
if (is_support_sw_smu(adev)) {
smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
- } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
- adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
+ } else if (pp_funcs && pp_funcs->get_power_limit) {
+ pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
@@ -3105,6 +3086,7 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
size_t count)
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
int err;
u32 value;
@@ -3128,10 +3110,8 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
return err;
}
- if (is_support_sw_smu(adev))
- err = smu_set_power_limit(&adev->smu, value);
- else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit)
- err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
+ if (pp_funcs && pp_funcs->set_power_limit)
+ err = pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
else
err = -EINVAL;
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 81ee621df448..6c0aa38fccba 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1239,7 +1239,7 @@ int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
enum smu_ppt_limit_level limit_level);
-int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
+int smu_set_power_limit(void *handle, uint32_t limit);
int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
int smu_od_edit_dpm_table(struct smu_context *smu,
@@ -1296,10 +1296,10 @@ extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
bool is_support_sw_smu(struct amdgpu_device *adev);
bool is_support_cclk_dpm(struct amdgpu_device *adev);
int smu_reset(struct smu_context *smu);
-int smu_sys_get_pp_table(struct smu_context *smu, void **table);
+int smu_sys_get_pp_table(void *handle, char **table);
int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
-int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
-enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
+int smu_get_power_num_states(void *handle, struct pp_states_info *state_info);
+enum amd_pm_state_type smu_get_current_power_state(void *handle);
int smu_write_watermarks_table(struct smu_context *smu);
int smu_set_watermarks_for_clock_ranges(
struct smu_context *smu,
@@ -1325,8 +1325,8 @@ enum amd_dpm_forced_level smu_get_performance_level(void *handle);
int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
int smu_set_display_count(struct smu_context *smu, uint32_t count);
int smu_set_ac_dc(struct smu_context *smu);
-size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
-int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
+int smu_sys_get_pp_feature_mask(void *handle, char *buf);
+int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index b7fe56b9e33e..e2b885bd23a3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -48,9 +48,10 @@
static const struct amd_pm_funcs swsmu_pm_funcs;
-size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+int smu_sys_get_pp_feature_mask(void *handle, char *buf)
{
- size_t size = 0;
+ struct smu_context *smu = handle;
+ int size = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
@@ -64,8 +65,9 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
return size;
}
-int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -381,7 +383,7 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu)
smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
}
-int smu_get_power_num_states(struct smu_context *smu,
+int smu_get_power_num_states(void *handle,
struct pp_states_info *state_info)
{
if (!state_info)
@@ -417,8 +419,9 @@ bool is_support_cclk_dpm(struct amdgpu_device *adev)
}
-int smu_sys_get_pp_table(struct smu_context *smu, void **table)
+int smu_sys_get_pp_table(void *handle, char **table)
{
+ struct smu_context *smu = handle;
struct smu_table_context *smu_table = &smu->smu_table;
uint32_t powerplay_table_size;
@@ -2085,8 +2088,9 @@ int smu_get_power_limit(struct smu_context *smu,
return ret;
}
-int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
+int smu_set_power_limit(void *handle, uint32_t limit)
{
+ struct smu_context *smu = handle;
uint32_t limit_type = limit >> 24;
int ret = 0;
@@ -2663,8 +2667,9 @@ int smu_get_uclk_dpm_states(struct smu_context *smu,
return ret;
}
-enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
+enum amd_pm_state_type smu_get_current_power_state(void *handle)
{
+ struct smu_context *smu = handle;
enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2750,19 +2755,25 @@ int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state)
static const struct amd_pm_funcs swsmu_pm_funcs = {
/* export for sysfs */
- .set_fan_control_mode = smu_pp_set_fan_control_mode,
- .get_fan_control_mode = smu_get_fan_control_mode,
- .set_fan_speed_percent = smu_set_fan_speed_percent,
- .get_fan_speed_percent = smu_get_fan_speed_percent,
- .get_performance_level = smu_get_performance_level,
- .get_fan_speed_rpm = smu_get_fan_speed_rpm,
- .set_fan_speed_rpm = smu_set_fan_speed_rpm,
- .switch_power_profile = smu_switch_power_profile,
+ .set_fan_control_mode = smu_pp_set_fan_control_mode,
+ .get_fan_control_mode = smu_get_fan_control_mode,
+ .set_fan_speed_percent = smu_set_fan_speed_percent,
+ .get_fan_speed_percent = smu_get_fan_speed_percent,
+ .get_performance_level = smu_get_performance_level,
+ .get_current_power_state = smu_get_current_power_state,
+ .get_fan_speed_rpm = smu_get_fan_speed_rpm,
+ .set_fan_speed_rpm = smu_set_fan_speed_rpm,
+ .get_pp_num_states = smu_get_power_num_states,
+ .get_pp_table = smu_sys_get_pp_table,
+ .switch_power_profile = smu_switch_power_profile,
/* export to amdgpu */
- .set_mp1_state = smu_set_mp1_state,
+ .set_power_limit = smu_set_power_limit,
+ .set_mp1_state = smu_set_mp1_state,
/* export to DC */
- .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
- .asic_reset_mode_2 = smu_mode2_reset,
- .set_df_cstate = smu_set_df_cstate,
- .set_xgmi_pstate = smu_set_xgmi_pstate,
+ .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
+ .get_ppfeature_status = smu_sys_get_pp_feature_mask,
+ .set_ppfeature_status = smu_sys_set_pp_feature_mask,
+ .asic_reset_mode_2 = smu_mode2_reset,
+ .set_df_cstate = smu_set_df_cstate,
+ .set_xgmi_pstate = smu_set_xgmi_pstate,
};
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/8] amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor functions to use API
2021-02-23 4:20 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
` (3 preceding siblings ...)
2021-02-23 4:20 ` [PATCH 4/8] amdgpu/pm: Powerplay API for smu , changed 9 pm power " Darren Powell
@ 2021-02-23 4:20 ` Darren Powell
2021-02-23 4:20 ` [PATCH 6/8] amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functions Darren Powell
` (2 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Darren Powell @ 2021-02-23 4:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Darren Powell
v2: add comment to highlight assignment that changes uint32_t value to int
fix errors flagged by checkpatch.pl
New Functions
smu_get_baco_capability() - Implement Powerplay API get_asic_baco_capability
smu_baco_set_state() - Implement Powerplay API set_asic_baco_state
Modified Functions
smu_read_sensor() - modifed signature to match Powerplay API read_sensor
Other Changes
added 3 above smu Powerplay functions to swsmu_dpm_funcs
removed special smu handling in 5 dpm functions and called through Powerplay API
Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 86 ++++++++---------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 7 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 72 +++++++++++++++++--
3 files changed, 100 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index df5e7b573428..8ae2df82addc 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -1019,18 +1019,13 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev)
{
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
void *pp_handle = adev->powerplay.pp_handle;
- struct smu_context *smu = &adev->smu;
int ret = 0;
- if (is_support_sw_smu(adev)) {
- ret = smu_baco_enter(smu);
- } else {
- if (!pp_funcs || !pp_funcs->set_asic_baco_state)
- return -ENOENT;
+ if (!pp_funcs || !pp_funcs->set_asic_baco_state)
+ return -ENOENT;
- /* enter BACO state */
- ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
- }
+ /* enter BACO state */
+ ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
return ret;
}
@@ -1039,18 +1034,13 @@ int amdgpu_dpm_baco_exit(struct amdgpu_device *adev)
{
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
void *pp_handle = adev->powerplay.pp_handle;
- struct smu_context *smu = &adev->smu;
int ret = 0;
- if (is_support_sw_smu(adev)) {
- ret = smu_baco_exit(smu);
- } else {
- if (!pp_funcs || !pp_funcs->set_asic_baco_state)
- return -ENOENT;
+ if (!pp_funcs || !pp_funcs->set_asic_baco_state)
+ return -ENOENT;
- /* exit BACO state */
- ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
- }
+ /* exit BACO state */
+ ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
return ret;
}
@@ -1074,20 +1064,15 @@ bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev)
{
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
void *pp_handle = adev->powerplay.pp_handle;
- struct smu_context *smu = &adev->smu;
bool baco_cap;
- if (is_support_sw_smu(adev)) {
- return smu_baco_is_support(smu);
- } else {
- if (!pp_funcs || !pp_funcs->get_asic_baco_capability)
- return false;
+ if (!pp_funcs || !pp_funcs->get_asic_baco_capability)
+ return false;
- if (pp_funcs->get_asic_baco_capability(pp_handle, &baco_cap))
- return false;
+ if (pp_funcs->get_asic_baco_capability(pp_handle, &baco_cap))
+ return false;
- return baco_cap ? true : false;
- }
+ return baco_cap;
}
int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev)
@@ -1105,32 +1090,20 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev)
{
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
void *pp_handle = adev->powerplay.pp_handle;
- struct smu_context *smu = &adev->smu;
int ret = 0;
- if (is_support_sw_smu(adev)) {
- ret = smu_baco_enter(smu);
- if (ret)
- return ret;
-
- ret = smu_baco_exit(smu);
- if (ret)
- return ret;
- } else {
- if (!pp_funcs
- || !pp_funcs->set_asic_baco_state)
- return -ENOENT;
+ if (!pp_funcs || !pp_funcs->set_asic_baco_state)
+ return -ENOENT;
- /* enter BACO state */
- ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
- if (ret)
- return ret;
+ /* enter BACO state */
+ ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
+ if (ret)
+ return ret;
- /* exit BACO state */
- ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
- if (ret)
- return ret;
- }
+ /* exit BACO state */
+ ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
+ if (ret)
+ return ret;
return 0;
}
@@ -1272,20 +1245,17 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
void *data, uint32_t *size)
{
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int ret = 0;
if (!data || !size)
return -EINVAL;
- if (is_support_sw_smu(adev))
- ret = smu_read_sensor(&adev->smu, sensor, data, size);
- else {
- if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
- ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
+ if (pp_funcs && pp_funcs->read_sensor)
+ ret = pp_funcs->read_sensor((adev)->powerplay.pp_handle,
sensor, data, size);
- else
- ret = -EINVAL;
- }
+ else
+ ret = -EINVAL;
return ret;
}
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 6c0aa38fccba..1835fce3369e 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1246,9 +1246,7 @@ int smu_od_edit_dpm_table(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size);
-int smu_read_sensor(struct smu_context *smu,
- enum amd_pp_sensors sensor,
- void *data, uint32_t *size);
+int smu_read_sensor(void *handle, int sensor, void *data, int *size);
int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
int smu_set_power_profile_mode(struct smu_context *smu,
@@ -1278,11 +1276,14 @@ int smu_set_xgmi_pstate(void *handle,
int smu_set_azalia_d3_pme(struct smu_context *smu);
bool smu_baco_is_support(struct smu_context *smu);
+int smu_get_baco_capability(void *handle, bool *cap);
int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
int smu_baco_enter(struct smu_context *smu);
int smu_baco_exit(struct smu_context *smu);
+int smu_baco_set_state(void *handle, int state);
+
bool smu_mode1_reset_is_support(struct smu_context *smu);
int smu_mode1_reset(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index e2b885bd23a3..f88c1d2ab9b8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2169,20 +2169,23 @@ int smu_od_edit_dpm_table(struct smu_context *smu,
return ret;
}
-int smu_read_sensor(struct smu_context *smu,
- enum amd_pp_sensors sensor,
- void *data, uint32_t *size)
+int smu_read_sensor(void *handle, int sensor, void *data, int *size_arg)
{
+ struct smu_context *smu = handle;
struct smu_umd_pstate_table *pstate_table =
&smu->pstate_table;
int ret = 0;
+ uint32_t *size, size_val;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
- if (!data || !size)
+ if (!data || !size_arg)
return -EINVAL;
+ size_val = *size_arg;
+ size = &size_val;
+
mutex_lock(&smu->mutex);
if (smu->ppt_funcs->read_sensor)
@@ -2227,6 +2230,9 @@ int smu_read_sensor(struct smu_context *smu,
unlock:
mutex_unlock(&smu->mutex);
+ // assign uint32_t to int
+ *size_arg = size_val;
+
return ret;
}
@@ -2523,6 +2529,27 @@ bool smu_baco_is_support(struct smu_context *smu)
return ret;
}
+int smu_get_baco_capability(void *handle, bool *cap)
+{
+ struct smu_context *smu = handle;
+ int ret = 0;
+
+ *cap = false;
+
+ if (!smu->pm_enabled)
+ return 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
+ *cap = smu->ppt_funcs->baco_is_support(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
{
if (smu->ppt_funcs->baco_get_state)
@@ -2575,6 +2602,40 @@ int smu_baco_exit(struct smu_context *smu)
return ret;
}
+int smu_baco_set_state(void *handle, int state)
+{
+ struct smu_context *smu = handle;
+ int ret = 0;
+
+ if (!smu->pm_enabled)
+ return -EOPNOTSUPP;
+
+ if (state == 0) {
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->baco_exit)
+ ret = smu->ppt_funcs->baco_exit(smu);
+
+ mutex_unlock(&smu->mutex);
+ } else if (state == 1) {
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->baco_enter)
+ ret = smu->ppt_funcs->baco_enter(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ } else {
+ return -EINVAL;
+ }
+
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
+ (state)?"enter":"exit");
+
+ return ret;
+}
+
bool smu_mode1_reset_is_support(struct smu_context *smu)
{
bool ret = false;
@@ -2759,6 +2820,7 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.get_fan_control_mode = smu_get_fan_control_mode,
.set_fan_speed_percent = smu_set_fan_speed_percent,
.get_fan_speed_percent = smu_get_fan_speed_percent,
+ .read_sensor = smu_read_sensor,
.get_performance_level = smu_get_performance_level,
.get_current_power_state = smu_get_current_power_state,
.get_fan_speed_rpm = smu_get_fan_speed_rpm,
@@ -2771,6 +2833,8 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.set_mp1_state = smu_set_mp1_state,
/* export to DC */
.enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
+ .get_asic_baco_capability = smu_get_baco_capability,
+ .set_asic_baco_state = smu_baco_set_state,
.get_ppfeature_status = smu_sys_get_pp_feature_mask,
.set_ppfeature_status = smu_sys_set_pp_feature_mask,
.asic_reset_mode_2 = smu_mode2_reset,
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/8] amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functions
2021-02-23 4:20 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
` (4 preceding siblings ...)
2021-02-23 4:20 ` [PATCH 5/8] amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor " Darren Powell
@ 2021-02-23 4:20 ` Darren Powell
2021-02-23 4:20 ` [PATCH 7/8] amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API Darren Powell
2021-02-23 4:20 ` [PATCH 8/8] amdgpu/pm: Powerplay API for smu , updates to some pm functions Darren Powell
7 siblings, 0 replies; 14+ messages in thread
From: Darren Powell @ 2021-02-23 4:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
v3: updated to include new clocks vclk, dclk, od_vddgfx_offset, od_cclk added in commits 771fc82ffc710 & f40074fde207e
Added forward declaration for function smu_force_smuclk_levels to resolve clash with commit 9485ed36411b7
Resolved context clashes with commit dfb3bb7fccb37 and v3 updates to patches 0003, 0004
v2: fix errors flagged by checkpatch
New Functions
smu_bump_power_profile_mode() - changes profile mode assuming calling function already has mutex
smu_force_ppclk_levels() - accepts Powerplay enum pp_clock_type to specify clock to change
smu_print_ppclk_levels() - accepts Powerplay enum pp_clock_type to request clock levels
amdgpu_get_pp_dpm_clock() - accepts Powerplay enum pp_clock_type to request clock levels and allows
all the amdgpu_get_pp_dpm_$CLK functions to have a single codepath
amdgpu_set_pp_dpm_clock() - accepts Powerplay enum pp_clock_type to set clock levels and allows
all the amdgpu_set_pp_dpm_$CLK functions to have a single codepath
Modified Functions
smu_force_smuclk_levels - changed function name to make clear difference to smu_force_ppclk_levels
smu_force_ppclk_levels() - modifed signature to implement Powerplay API force_clock_level
- calls smu_force_smuclk_levels
smu_print_smuclk_levels - changed function name to make clear difference to smu_print_ppclk_levels
smu_print_ppclk_levels() - modifed signature to implement Powerplay API force_clock_level
- calls smu_print_smuclk_levels
smu_sys_get_gpu_metrics - modifed arg0 to match Powerplay API get_gpu_metrics
smu_get_power_profile_mode - modifed arg0 to match Powerplay API get_power_profile_mode
smu_set_power_profile_mode - modifed arg0 to match Powerplay API set_power_profile_mode
- removed arg lock_needed, mutex always locked, internal functions
can call smu_bump if they already hold lock
smu_switch_power_profile - now calls smu_bump as already holds mutex lock
smu_adjust_power_state_dynamic - now calls smu_bump as already holds mutex lock
amdgpu_get_pp_od_clk_voltage - uses smu_print_ppclk_levels
amdgpu_{set,get}_pp_dpm_$CLK - replace logic with call helper function amdgpu_{set,get}_pp_dpm_clock()
CLK ={sclk, mclk, socclk, fclk, dcefclk, pci, vclkd, dclk}
Other Changes
added 5 smu Powerplay functions to swsmu_dpm_funcs
removed special smu handling in pm functions and called through Powerplay API
Signed-off-by: Darren Powell <darren.powell@amd.com>
---
.../gpu/drm/amd/include/kgd_pp_interface.h | 4 +
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 462 ++----------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 16 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 130 ++++-
4 files changed, 168 insertions(+), 444 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index a41875ac5dfb..7621eaba39f5 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -95,10 +95,14 @@ enum pp_clock_type {
PP_SOCCLK,
PP_FCLK,
PP_DCEFCLK,
+ PP_VCLK,
+ PP_DCLK,
OD_SCLK,
OD_MCLK,
OD_VDDC_CURVE,
OD_RANGE,
+ OD_VDDGFX_OFFSET,
+ OD_CCLK,
};
enum amd_pp_sensors {
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 34e5c4c4f280..ec5277ed74f7 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -893,12 +893,12 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
}
if (is_support_sw_smu(adev)) {
- size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
- size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
- size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
- size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDGFX_OFFSET, buf+size);
- size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
- size += smu_print_clk_levels(&adev->smu, SMU_OD_CCLK, buf+size);
+ size = smu_print_ppclk_levels(&adev->smu, OD_SCLK, buf);
+ size += smu_print_ppclk_levels(&adev->smu, OD_MCLK, buf+size);
+ size += smu_print_ppclk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
+ size += smu_print_ppclk_levels(&adev->smu, OD_VDDGFX_OFFSET, buf+size);
+ size += smu_print_ppclk_levels(&adev->smu, OD_RANGE, buf+size);
+ size += smu_print_ppclk_levels(&adev->smu, OD_CCLK, buf+size);
} else if (adev->powerplay.pp_funcs->print_clock_levels) {
size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
@@ -1032,8 +1032,8 @@ static ssize_t amdgpu_get_pp_features(struct device *dev,
* NOTE: change to the dcefclk max dpm level is not supported now
*/
-static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
- struct device_attribute *attr,
+static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
+ enum pp_clock_type type,
char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
@@ -1050,10 +1050,8 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev))
- size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
- else if (adev->powerplay.pp_funcs->print_clock_levels)
- size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
+ if (adev->powerplay.pp_funcs->print_clock_levels)
+ size = amdgpu_dpm_print_clock_levels(adev, type, buf);
else
size = snprintf(buf, PAGE_SIZE, "\n");
@@ -1098,8 +1096,8 @@ static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
return 0;
}
-static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
- struct device_attribute *attr,
+static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
+ enum pp_clock_type type,
const char *buf,
size_t count)
{
@@ -1121,10 +1119,10 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
- else if (adev->powerplay.pp_funcs->force_clock_level)
- ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+ if (adev->powerplay.pp_funcs->force_clock_level)
+ ret = amdgpu_dpm_force_clock_level(adev, type, mask);
+ else
+ ret = 0;
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@@ -1135,35 +1133,26 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
return count;
}
-static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
+static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- ssize_t size;
- int ret;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
- else if (adev->powerplay.pp_funcs->print_clock_levels)
- size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
- else
- size = snprintf(buf, PAGE_SIZE, "\n");
+ return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
+}
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
+static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
+}
- return size;
+static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
}
static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
@@ -1171,67 +1160,14 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
const char *buf,
size_t count)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- uint32_t mask = 0;
- int ret;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = amdgpu_read_mask(buf, count, &mask);
- if (ret)
- return ret;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
- else if (adev->powerplay.pp_funcs->force_clock_level)
- ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- if (ret)
- return -EINVAL;
-
- return count;
+ return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
}
static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- ssize_t size;
- int ret;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
- else if (adev->powerplay.pp_funcs->print_clock_levels)
- size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
- else
- size = snprintf(buf, PAGE_SIZE, "\n");
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- return size;
+ return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
}
static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
@@ -1239,69 +1175,14 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
const char *buf,
size_t count)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- int ret;
- uint32_t mask = 0;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = amdgpu_read_mask(buf, count, &mask);
- if (ret)
- return ret;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
- else if (adev->powerplay.pp_funcs->force_clock_level)
- ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
- else
- ret = 0;
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- if (ret)
- return -EINVAL;
-
- return count;
+ return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
}
static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- ssize_t size;
- int ret;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
- else if (adev->powerplay.pp_funcs->print_clock_levels)
- size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
- else
- size = snprintf(buf, PAGE_SIZE, "\n");
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- return size;
+ return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
}
static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
@@ -1309,67 +1190,14 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
const char *buf,
size_t count)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- int ret;
- uint32_t mask = 0;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = amdgpu_read_mask(buf, count, &mask);
- if (ret)
- return ret;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
- else if (adev->powerplay.pp_funcs->force_clock_level)
- ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
- else
- ret = 0;
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- if (ret)
- return -EINVAL;
-
- return count;
+ return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
}
static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- ssize_t size;
- int ret;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- size = smu_print_clk_levels(&adev->smu, SMU_VCLK, buf);
- else
- size = snprintf(buf, PAGE_SIZE, "\n");
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- return size;
+ return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
}
static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
@@ -1377,65 +1205,14 @@ static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
const char *buf,
size_t count)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- int ret;
- uint32_t mask = 0;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = amdgpu_read_mask(buf, count, &mask);
- if (ret)
- return ret;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_VCLK, mask);
- else
- ret = 0;
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- if (ret)
- return -EINVAL;
-
- return count;
+ return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
}
static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- ssize_t size;
- int ret;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- size = smu_print_clk_levels(&adev->smu, SMU_DCLK, buf);
- else
- size = snprintf(buf, PAGE_SIZE, "\n");
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- return size;
+ return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
}
static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
@@ -1443,67 +1220,14 @@ static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
const char *buf,
size_t count)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- int ret;
- uint32_t mask = 0;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = amdgpu_read_mask(buf, count, &mask);
- if (ret)
- return ret;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_DCLK, mask);
- else
- ret = 0;
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- if (ret)
- return -EINVAL;
-
- return count;
+ return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
}
static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- ssize_t size;
- int ret;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
- else if (adev->powerplay.pp_funcs->print_clock_levels)
- size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
- else
- size = snprintf(buf, PAGE_SIZE, "\n");
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- return size;
+ return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
}
static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
@@ -1511,69 +1235,14 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
const char *buf,
size_t count)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- int ret;
- uint32_t mask = 0;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = amdgpu_read_mask(buf, count, &mask);
- if (ret)
- return ret;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
- else if (adev->powerplay.pp_funcs->force_clock_level)
- ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
- else
- ret = 0;
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- if (ret)
- return -EINVAL;
-
- return count;
+ return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
}
static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- ssize_t size;
- int ret;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
- else if (adev->powerplay.pp_funcs->print_clock_levels)
- size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
- else
- size = snprintf(buf, PAGE_SIZE, "\n");
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- return size;
+ return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
}
static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
@@ -1581,38 +1250,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
const char *buf,
size_t count)
{
- struct drm_device *ddev = dev_get_drvdata(dev);
- struct amdgpu_device *adev = drm_to_adev(ddev);
- int ret;
- uint32_t mask = 0;
-
- if (amdgpu_in_reset(adev))
- return -EPERM;
-
- ret = amdgpu_read_mask(buf, count, &mask);
- if (ret)
- return ret;
-
- ret = pm_runtime_get_sync(ddev->dev);
- if (ret < 0) {
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
-
- if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
- else if (adev->powerplay.pp_funcs->force_clock_level)
- ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
- else
- ret = 0;
-
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
-
- if (ret)
- return -EINVAL;
-
- return count;
+ return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
}
static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
@@ -1799,9 +1437,7 @@ static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev))
- size = smu_get_power_profile_mode(&adev->smu, buf);
- else if (adev->powerplay.pp_funcs->get_power_profile_mode)
+ if (adev->powerplay.pp_funcs->get_power_profile_mode)
size = amdgpu_dpm_get_power_profile_mode(adev, buf);
else
size = snprintf(buf, PAGE_SIZE, "\n");
@@ -1865,9 +1501,7 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev))
- ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
- else if (adev->powerplay.pp_funcs->set_power_profile_mode)
+ if (adev->powerplay.pp_funcs->set_power_profile_mode)
ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
pm_runtime_mark_last_busy(ddev->dev);
@@ -2124,9 +1758,7 @@ static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev))
- size = smu_sys_get_gpu_metrics(&adev->smu, &gpu_metrics);
- else if (adev->powerplay.pp_funcs->get_gpu_metrics)
+ if (adev->powerplay.pp_funcs->get_gpu_metrics)
size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
if (size <= 0)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 1835fce3369e..20af40b24f66 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1240,19 +1240,15 @@ int smu_get_power_limit(struct smu_context *smu,
enum smu_ppt_limit_level limit_level);
int smu_set_power_limit(void *handle, uint32_t limit);
-int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
+int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf);
int smu_od_edit_dpm_table(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size);
int smu_read_sensor(void *handle, int sensor, void *data, int *size);
-int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
-
-int smu_set_power_profile_mode(struct smu_context *smu,
- long *param,
- uint32_t param_size,
- bool lock_needed);
+int smu_get_power_profile_mode(void *handle, char *buf);
+int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size);
u32 smu_get_fan_control_mode(void *handle);
int smu_set_fan_control_mode(struct smu_context *smu, int value);
void smu_pp_set_fan_control_mode(void *handle, u32 value);
@@ -1328,9 +1324,7 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count);
int smu_set_ac_dc(struct smu_context *smu);
int smu_sys_get_pp_feature_mask(void *handle, char *buf);
int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask);
-int smu_force_clk_levels(struct smu_context *smu,
- enum smu_clk_type clk_type,
- uint32_t mask);
+int smu_force_ppclk_levels(void *handle, enum pp_clock_type type, uint32_t mask);
int smu_set_mp1_state(void *handle,
enum pp_mp1_state mp1_state);
int smu_set_df_cstate(void *handle,
@@ -1349,7 +1343,7 @@ int smu_get_dpm_clock_table(struct smu_context *smu,
int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
-ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, void **table);
+ssize_t smu_sys_get_gpu_metrics(void *handle, void **table);
int smu_enable_mgpu_fan_boost(void *handle);
int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index f88c1d2ab9b8..c760f75ccb54 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -47,6 +47,9 @@
#undef pr_debug
static const struct amd_pm_funcs swsmu_pm_funcs;
+static int smu_force_smuclk_levels(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t mask);
int smu_sys_get_pp_feature_mask(void *handle, char *buf)
{
@@ -355,7 +358,7 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu)
*/
if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
smu->user_dpm_profile.clk_mask[clk_type]) {
- ret = smu_force_clk_levels(smu, clk_type,
+ ret = smu_force_smuclk_levels(smu, clk_type,
smu->user_dpm_profile.clk_mask[clk_type]);
if (ret)
dev_err(smu->adev->dev, "Failed to set clock type = %d\n",
@@ -1574,6 +1577,18 @@ static int smu_enable_umd_pstate(void *handle,
return 0;
}
+static int smu_bump_power_profile_mode(struct smu_context *smu,
+ long *param,
+ uint32_t param_size)
+{
+ int ret = 0;
+
+ if (smu->ppt_funcs->set_power_profile_mode)
+ ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
+
+ return ret;
+}
+
static int smu_adjust_power_state_dynamic(struct smu_context *smu,
enum amd_dpm_forced_level level,
bool skip_display_settings)
@@ -1622,7 +1637,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu,
workload = smu->workload_setting[index];
if (smu->power_profile_mode != workload)
- smu_set_power_profile_mode(smu, &workload, 0, false);
+ smu_bump_power_profile_mode(smu, &workload, 0);
}
return ret;
@@ -1693,7 +1708,7 @@ int smu_switch_power_profile(void *handle,
}
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
- smu_set_power_profile_mode(smu, &workload, 0, false);
+ smu_bump_power_profile_mode(smu, &workload, 0);
mutex_unlock(&smu->mutex);
@@ -1767,7 +1782,7 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
return ret;
}
-int smu_force_clk_levels(struct smu_context *smu,
+static int smu_force_smuclk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask)
{
@@ -1797,6 +1812,43 @@ int smu_force_clk_levels(struct smu_context *smu,
return ret;
}
+int smu_force_ppclk_levels(void *handle, enum pp_clock_type type, uint32_t mask)
+{
+ struct smu_context *smu = handle;
+ enum smu_clk_type clk_type;
+
+ switch (type) {
+ case PP_SCLK:
+ clk_type = SMU_SCLK; break;
+ case PP_MCLK:
+ clk_type = SMU_MCLK; break;
+ case PP_PCIE:
+ clk_type = SMU_PCIE; break;
+ case PP_SOCCLK:
+ clk_type = SMU_SOCCLK; break;
+ case PP_FCLK:
+ clk_type = SMU_FCLK; break;
+ case PP_DCEFCLK:
+ clk_type = SMU_DCEFCLK; break;
+ case PP_VCLK:
+ clk_type = SMU_VCLK; break;
+ case PP_DCLK:
+ clk_type = SMU_DCLK; break;
+ case OD_SCLK:
+ clk_type = SMU_OD_SCLK; break;
+ case OD_MCLK:
+ clk_type = SMU_OD_MCLK; break;
+ case OD_VDDC_CURVE:
+ clk_type = SMU_OD_VDDC_CURVE; break;
+ case OD_RANGE:
+ clk_type = SMU_OD_RANGE; break;
+ default:
+ return -EINVAL;
+ }
+
+ return smu_force_smuclk_levels(smu, clk_type, mask);
+}
+
/*
* On system suspending or resetting, the dpm_enabled
* flag will be cleared. So that those SMU services which
@@ -2127,7 +2179,7 @@ int smu_set_power_limit(void *handle, uint32_t limit)
return ret;
}
-int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
+static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
{
int ret = 0;
@@ -2144,6 +2196,47 @@ int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, ch
return ret;
}
+int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf)
+{
+ struct smu_context *smu = handle;
+ enum smu_clk_type clk_type;
+
+ switch (type) {
+ case PP_SCLK:
+ clk_type = SMU_SCLK; break;
+ case PP_MCLK:
+ clk_type = SMU_MCLK; break;
+ case PP_PCIE:
+ clk_type = SMU_PCIE; break;
+ case PP_SOCCLK:
+ clk_type = SMU_SOCCLK; break;
+ case PP_FCLK:
+ clk_type = SMU_FCLK; break;
+ case PP_DCEFCLK:
+ clk_type = SMU_DCEFCLK; break;
+ case PP_VCLK:
+ clk_type = SMU_VCLK; break;
+ case PP_DCLK:
+ clk_type = SMU_DCLK; break;
+ case OD_SCLK:
+ clk_type = SMU_OD_SCLK; break;
+ case OD_MCLK:
+ clk_type = SMU_OD_MCLK; break;
+ case OD_VDDC_CURVE:
+ clk_type = SMU_OD_VDDC_CURVE; break;
+ case OD_RANGE:
+ clk_type = SMU_OD_RANGE; break;
+ case OD_VDDGFX_OFFSET:
+ clk_type = SMU_OD_VDDGFX_OFFSET; break;
+ case OD_CCLK:
+ clk_type = SMU_OD_CCLK; break;
+ default:
+ return -EINVAL;
+ }
+
+ return smu_print_smuclk_levels(smu, clk_type, buf);
+}
+
int smu_od_edit_dpm_table(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size)
@@ -2236,8 +2329,9 @@ int smu_read_sensor(void *handle, int sensor, void *data, int *size_arg)
return ret;
}
-int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
+int smu_get_power_profile_mode(void *handle, char *buf)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2253,24 +2347,19 @@ int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
return ret;
}
-int smu_set_power_profile_mode(struct smu_context *smu,
- long *param,
- uint32_t param_size,
- bool lock_needed)
+int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
- if (lock_needed)
- mutex_lock(&smu->mutex);
+ mutex_lock(&smu->mutex);
- if (smu->ppt_funcs->set_power_profile_mode)
- ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
+ smu_bump_power_profile_mode(smu, param, param_size);
- if (lock_needed)
- mutex_unlock(&smu->mutex);
+ mutex_unlock(&smu->mutex);
return ret;
}
@@ -2764,9 +2853,9 @@ int smu_get_dpm_clock_table(struct smu_context *smu,
return ret;
}
-ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
- void **table)
+ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
{
+ struct smu_context *smu = handle;
ssize_t size;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2840,4 +2929,9 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.asic_reset_mode_2 = smu_mode2_reset,
.set_df_cstate = smu_set_df_cstate,
.set_xgmi_pstate = smu_set_xgmi_pstate,
+ .get_gpu_metrics = smu_sys_get_gpu_metrics,
+ .set_power_profile_mode = smu_set_power_profile_mode,
+ .get_power_profile_mode = smu_get_power_profile_mode,
+ .force_clock_level = smu_force_ppclk_levels,
+ .print_clock_levels = smu_print_ppclk_levels,
};
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 7/8] amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
2021-02-23 4:20 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
` (5 preceding siblings ...)
2021-02-23 4:20 ` [PATCH 6/8] amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functions Darren Powell
@ 2021-02-23 4:20 ` Darren Powell
2021-02-23 4:20 ` [PATCH 8/8] amdgpu/pm: Powerplay API for smu , updates to some pm functions Darren Powell
7 siblings, 0 replies; 14+ messages in thread
From: Darren Powell @ 2021-02-23 4:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Darren Powell
v2: fix errors and warnings flagged by checkpatch
v3: Context mismatch with revision v3 to patch 0003
New Functions
smu_get_mclk - implementation of the Powerplay API function get_mclk
smu_get_sclk - implementation of the Powerplay API function get_sclk
smu_handle_dpm_task - implementation of the Powerplay API function dispatch_tasks
Modified Functions
smu_dpm_set_power_gate - - modifed arg0 to match Powerplay API set_powergating_by_smu
Other Changes
removed special smu handling in dpm functions and called through Powerplay API
call to smu_dpm_set_power_gate via Powerplay API now locks mutex for UVD and VCE
Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 96 ++++++++---------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 7 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 49 +++++++++++-
3 files changed, 86 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 8ae2df82addc..0a6bb3311f0f 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -911,50 +911,28 @@ amdgpu_get_vce_clock_state(void *handle, u32 idx)
int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
{
- uint32_t clk_freq;
- int ret = 0;
- if (is_support_sw_smu(adev)) {
- ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK,
- low ? &clk_freq : NULL,
- !low ? &clk_freq : NULL);
- if (ret)
- return 0;
- return clk_freq * 100;
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- } else {
- return (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (low));
- }
+ return pp_funcs->get_sclk((adev)->powerplay.pp_handle, (low));
}
int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
{
- uint32_t clk_freq;
- int ret = 0;
- if (is_support_sw_smu(adev)) {
- ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,
- low ? &clk_freq : NULL,
- !low ? &clk_freq : NULL);
- if (ret)
- return 0;
- return clk_freq * 100;
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- } else {
- return (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low));
- }
+ return pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low));
}
int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate)
{
int ret = 0;
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
bool swsmu = is_support_sw_smu(adev);
switch (block_type) {
case AMD_IP_BLOCK_TYPE_UVD:
case AMD_IP_BLOCK_TYPE_VCE:
- if (swsmu) {
- ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate);
- } else if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->set_powergating_by_smu) {
+ if (pp_funcs && pp_funcs->set_powergating_by_smu) {
/*
* TODO: need a better lock mechanism
*
@@ -982,7 +960,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
* amdgpu_set_dpm_forced_performance_level+0x129/0x330 [amdgpu]
*/
mutex_lock(&adev->pm.mutex);
- ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
+ ret = (pp_funcs->set_powergating_by_smu(
(adev)->powerplay.pp_handle, block_type, gate));
mutex_unlock(&adev->pm.mutex);
}
@@ -990,12 +968,10 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
case AMD_IP_BLOCK_TYPE_GFX:
case AMD_IP_BLOCK_TYPE_VCN:
case AMD_IP_BLOCK_TYPE_SDMA:
- if (swsmu)
- ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate);
- else if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->set_powergating_by_smu)
- ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
+ if (pp_funcs && pp_funcs->set_powergating_by_smu) {
+ ret = (pp_funcs->set_powergating_by_smu(
(adev)->powerplay.pp_handle, block_type, gate));
+ }
break;
case AMD_IP_BLOCK_TYPE_JPEG:
if (swsmu)
@@ -1003,10 +979,10 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
break;
case AMD_IP_BLOCK_TYPE_GMC:
case AMD_IP_BLOCK_TYPE_ACP:
- if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->set_powergating_by_smu)
- ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
+ if (pp_funcs && pp_funcs->set_powergating_by_smu) {
+ ret = (pp_funcs->set_powergating_by_smu(
(adev)->powerplay.pp_handle, block_type, gate));
+ }
break;
default:
break;
@@ -1512,36 +1488,30 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
amdgpu_fence_wait_empty(ring);
}
- if (is_support_sw_smu(adev)) {
- struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
- smu_handle_task(&adev->smu,
- smu_dpm->dpm_level,
- AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
- true);
- } else {
- if (adev->powerplay.pp_funcs->dispatch_tasks) {
- if (!amdgpu_device_has_dc_support(adev)) {
- mutex_lock(&adev->pm.mutex);
- amdgpu_dpm_get_active_displays(adev);
- adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
- adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
- adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
- /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
- if (adev->pm.pm_display_cfg.vrefresh > 120)
- adev->pm.pm_display_cfg.min_vblank_time = 0;
- if (adev->powerplay.pp_funcs->display_configuration_change)
- adev->powerplay.pp_funcs->display_configuration_change(
- adev->powerplay.pp_handle,
- &adev->pm.pm_display_cfg);
- mutex_unlock(&adev->pm.mutex);
- }
- amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
- } else {
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ if (!amdgpu_device_has_dc_support(adev)) {
mutex_lock(&adev->pm.mutex);
amdgpu_dpm_get_active_displays(adev);
- amdgpu_dpm_change_power_state_locked(adev);
+ adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
+ adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
+ adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
+ /* we have issues with mclk switching with
+ * refresh rates over 120 hz on the non-DC code.
+ */
+ if (adev->pm.pm_display_cfg.vrefresh > 120)
+ adev->pm.pm_display_cfg.min_vblank_time = 0;
+ if (adev->powerplay.pp_funcs->display_configuration_change)
+ adev->powerplay.pp_funcs->display_configuration_change(
+ adev->powerplay.pp_handle,
+ &adev->pm.pm_display_cfg);
mutex_unlock(&adev->pm.mutex);
}
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
+ } else {
+ mutex_lock(&adev->pm.mutex);
+ amdgpu_dpm_get_active_displays(adev);
+ amdgpu_dpm_change_power_state_locked(adev);
+ mutex_unlock(&adev->pm.mutex);
}
}
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 20af40b24f66..a2f4b8f1db4e 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1306,16 +1306,21 @@ int smu_set_watermarks_for_clock_ranges(
extern int smu_display_configuration_change(struct smu_context *smu, const
struct amd_pp_display_configuration
*display_config);
-extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
+extern int smu_dpm_set_power_gate(void *handle, uint32_t block_type, bool gate);
extern int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
enum amd_pp_task task_id,
bool lock_needed);
+extern int smu_handle_dpm_task(void *handle,
+ enum amd_pp_task task_id,
+ enum amd_pm_state_type *user_state);
int smu_switch_power_profile(void *handle,
enum PP_SMC_POWER_PROFILE type,
bool en);
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max);
+u32 smu_get_mclk(void *handle, bool low);
+u32 smu_get_sclk(void *handle, bool low);
int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
enum amd_dpm_forced_level smu_get_performance_level(void *handle);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index c760f75ccb54..72501d8a80b9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -141,6 +141,34 @@ int smu_get_dpm_freq_range(struct smu_context *smu,
return ret;
}
+u32 smu_get_mclk(void *handle, bool low)
+{
+ struct smu_context *smu = handle;
+ uint32_t clk_freq;
+ int ret = 0;
+
+ ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
+ low ? &clk_freq : NULL,
+ !low ? &clk_freq : NULL);
+ if (ret)
+ return 0;
+ return clk_freq * 100;
+}
+
+u32 smu_get_sclk(void *handle, bool low)
+{
+ struct smu_context *smu = handle;
+ uint32_t clk_freq;
+ int ret = 0;
+
+ ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
+ low ? &clk_freq : NULL,
+ !low ? &clk_freq : NULL);
+ if (ret)
+ return 0;
+ return clk_freq * 100;
+}
+
static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
bool enable)
{
@@ -216,7 +244,7 @@ static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
/**
* smu_dpm_set_power_gate - power gate/ungate the specific IP block
*
- * @smu: smu_context pointer
+ * @handle: smu_context pointer
* @block_type: the IP block to power gate/ungate
* @gate: to power gate if true, ungate otherwise
*
@@ -227,9 +255,10 @@ static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
* Under this case, the smu->mutex lock protection is already enforced on
* the parent API smu_force_performance_level of the call path.
*/
-int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+int smu_dpm_set_power_gate(void *handle, uint32_t block_type,
bool gate)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -1678,6 +1707,18 @@ int smu_handle_task(struct smu_context *smu,
return ret;
}
+int smu_handle_dpm_task(void *handle,
+ enum amd_pp_task task_id,
+ enum amd_pm_state_type *user_state)
+{
+ struct smu_context *smu = handle;
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+
+ return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true);
+
+}
+
+
int smu_switch_power_profile(void *handle,
enum PP_SMC_POWER_PROFILE type,
bool en)
@@ -2918,9 +2959,13 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.get_pp_table = smu_sys_get_pp_table,
.switch_power_profile = smu_switch_power_profile,
/* export to amdgpu */
+ .dispatch_tasks = smu_handle_dpm_task,
+ .set_powergating_by_smu = smu_dpm_set_power_gate,
.set_power_limit = smu_set_power_limit,
.set_mp1_state = smu_set_mp1_state,
/* export to DC */
+ .get_sclk = smu_get_sclk,
+ .get_mclk = smu_get_mclk,
.enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
.get_asic_baco_capability = smu_get_baco_capability,
.set_asic_baco_state = smu_baco_set_state,
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 8/8] amdgpu/pm: Powerplay API for smu , updates to some pm functions
2021-02-23 4:20 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
` (6 preceding siblings ...)
2021-02-23 4:20 ` [PATCH 7/8] amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API Darren Powell
@ 2021-02-23 4:20 ` Darren Powell
2021-02-24 4:17 ` Quan, Evan
7 siblings, 1 reply; 14+ messages in thread
From: Darren Powell @ 2021-02-23 4:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
v3: updated to include new clocks od_vddgfx_offset, od_cclk
Context mismatch with revision v3 to patch 0003
Modified Functions
smu_sys_set_pp_table() - modifed signature to match Powerplay API set_pp_table
smu_force_performance_level() - modifed arg0 to match Powerplay API force_performance_level
smu_od_edit_dpm_table() - modifed arg0 to match Powerplay API odn_edit_dpm_table
Other Changes
smu_od_edit_dpm_table() - removed call to task(READJUST_POWER_STATE) after COMMIT_TABLE,
now handled in calling function
amdgpu_set_power_dpm_force_performance_level() - now checks thermal for swsmu systems before trying to change level
amdgpu_set_pp_od_clk_voltage() - now attempts to set fine_grain_clock_vol before swsmu edit dpm table
Signed-off-by: Darren Powell <darren.powell@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 98 +++++++++--------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 6 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 17 ++--
3 files changed, 48 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index ec5277ed74f7..1675a5e72a0d 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -370,14 +370,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
return -EINVAL;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_force_performance_level(&adev->smu, level);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
- }
- } else if (pp_funcs->force_performance_level) {
+ if (pp_funcs->force_performance_level) {
mutex_lock(&adev->pm.mutex);
if (adev->pm.dpm.thermal_active) {
mutex_unlock(&adev->pm.mutex);
@@ -615,15 +608,12 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
- } else if (adev->powerplay.pp_funcs->set_pp_table)
- amdgpu_dpm_set_pp_table(adev, buf, count);
+ ret = amdgpu_dpm_set_pp_table(adev, buf, count);
+ if (ret) {
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return ret;
+ }
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@@ -821,53 +811,42 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_od_edit_dpm_table(&adev->smu, type,
- parameter, parameter_size);
-
+ if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
+ ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
+ parameter,
+ parameter_size);
if (ret) {
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
return -EINVAL;
}
- } else {
-
- if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
- ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
- parameter,
- parameter_size);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
- }
- }
+ }
- if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
- ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
- parameter, parameter_size);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
- }
+ if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
+ ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
+ parameter, parameter_size);
+ if (ret) {
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return -EINVAL;
}
+ }
- if (type == PP_OD_COMMIT_DPM_TABLE) {
- if (adev->powerplay.pp_funcs->dispatch_tasks) {
- amdgpu_dpm_dispatch_task(adev,
- AMD_PP_TASK_READJUST_POWER_STATE,
- NULL);
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return count;
- } else {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
- }
+ if (type == PP_OD_COMMIT_DPM_TABLE) {
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ amdgpu_dpm_dispatch_task(adev,
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ NULL);
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return count;
+ } else {
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return -EINVAL;
}
}
+
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@@ -892,18 +871,13 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- size = smu_print_ppclk_levels(&adev->smu, OD_SCLK, buf);
- size += smu_print_ppclk_levels(&adev->smu, OD_MCLK, buf+size);
- size += smu_print_ppclk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
- size += smu_print_ppclk_levels(&adev->smu, OD_VDDGFX_OFFSET, buf+size);
- size += smu_print_ppclk_levels(&adev->smu, OD_RANGE, buf+size);
- size += smu_print_ppclk_levels(&adev->smu, OD_CCLK, buf+size);
- } else if (adev->powerplay.pp_funcs->print_clock_levels) {
+ if (adev->powerplay.pp_funcs->print_clock_levels) {
size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
+ size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf+size);
size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
+ size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
}
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index a2f4b8f1db4e..af71c7c6db46 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1242,7 +1242,7 @@ int smu_get_power_limit(struct smu_context *smu,
int smu_set_power_limit(void *handle, uint32_t limit);
int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf);
-int smu_od_edit_dpm_table(struct smu_context *smu,
+int smu_od_edit_dpm_table(void *handle,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size);
@@ -1294,7 +1294,7 @@ bool is_support_sw_smu(struct amdgpu_device *adev);
bool is_support_cclk_dpm(struct amdgpu_device *adev);
int smu_reset(struct smu_context *smu);
int smu_sys_get_pp_table(void *handle, char **table);
-int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
+int smu_sys_set_pp_table(void *handle, const char *buf, size_t size);
int smu_get_power_num_states(void *handle, struct pp_states_info *state_info);
enum amd_pm_state_type smu_get_current_power_state(void *handle);
int smu_write_watermarks_table(struct smu_context *smu);
@@ -1324,7 +1324,7 @@ u32 smu_get_sclk(void *handle, bool low);
int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
enum amd_dpm_forced_level smu_get_performance_level(void *handle);
-int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
+int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level);
int smu_set_display_count(struct smu_context *smu, uint32_t count);
int smu_set_ac_dc(struct smu_context *smu);
int smu_sys_get_pp_feature_mask(void *handle, char *buf);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 72501d8a80b9..f5d9590f2178 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -477,8 +477,9 @@ int smu_sys_get_pp_table(void *handle, char **table)
return powerplay_table_size;
}
-int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
+int smu_sys_set_pp_table(void *handle, const char *buf, size_t size)
{
+ struct smu_context *smu = handle;
struct smu_table_context *smu_table = &smu->smu_table;
ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
int ret = 0;
@@ -1775,8 +1776,9 @@ enum amd_dpm_forced_level smu_get_performance_level(void *handle)
return level;
}
-int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
+int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level)
{
+ struct smu_context *smu = handle;
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int ret = 0;
@@ -2278,10 +2280,11 @@ int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf)
return smu_print_smuclk_levels(smu, clk_type, buf);
}
-int smu_od_edit_dpm_table(struct smu_context *smu,
+int smu_od_edit_dpm_table(void *handle,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2291,11 +2294,6 @@ int smu_od_edit_dpm_table(struct smu_context *smu,
if (smu->ppt_funcs->od_edit_dpm_table) {
ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
- if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
- ret = smu_handle_task(smu,
- smu->smu_dpm.dpm_level,
- AMD_PP_TASK_READJUST_POWER_STATE,
- false);
}
mutex_unlock(&smu->mutex);
@@ -2950,6 +2948,7 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.get_fan_control_mode = smu_get_fan_control_mode,
.set_fan_speed_percent = smu_set_fan_speed_percent,
.get_fan_speed_percent = smu_get_fan_speed_percent,
+ .force_performance_level = smu_force_performance_level,
.read_sensor = smu_read_sensor,
.get_performance_level = smu_get_performance_level,
.get_current_power_state = smu_get_current_power_state,
@@ -2957,11 +2956,13 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.set_fan_speed_rpm = smu_set_fan_speed_rpm,
.get_pp_num_states = smu_get_power_num_states,
.get_pp_table = smu_sys_get_pp_table,
+ .set_pp_table = smu_sys_set_pp_table,
.switch_power_profile = smu_switch_power_profile,
/* export to amdgpu */
.dispatch_tasks = smu_handle_dpm_task,
.set_powergating_by_smu = smu_dpm_set_power_gate,
.set_power_limit = smu_set_power_limit,
+ .odn_edit_dpm_table = smu_od_edit_dpm_table,
.set_mp1_state = smu_set_mp1_state,
/* export to DC */
.get_sclk = smu_get_sclk,
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* RE: [PATCH 8/8] amdgpu/pm: Powerplay API for smu , updates to some pm functions
2021-02-23 4:20 ` [PATCH 8/8] amdgpu/pm: Powerplay API for smu , updates to some pm functions Darren Powell
@ 2021-02-24 4:17 ` Quan, Evan
0 siblings, 0 replies; 14+ messages in thread
From: Quan, Evan @ 2021-02-24 4:17 UTC (permalink / raw)
To: Powell, Darren, amd-gfx; +Cc: Powell, Darren
[AMD Public Use]
Series is reviewed-by: Evan Quan <evan.quan@amd.com>
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Darren Powell
Sent: Tuesday, February 23, 2021 12:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Powell, Darren <Darren.Powell@amd.com>
Subject: [PATCH 8/8] amdgpu/pm: Powerplay API for smu , updates to some pm functions
v3: updated to include new clocks od_vddgfx_offset, od_cclk
Context mismatch with revision v3 to patch 0003
Modified Functions
smu_sys_set_pp_table() - modifed signature to match Powerplay API set_pp_table
smu_force_performance_level() - modifed arg0 to match Powerplay API force_performance_level
smu_od_edit_dpm_table() - modifed arg0 to match Powerplay API odn_edit_dpm_table
Other Changes
smu_od_edit_dpm_table() - removed call to task(READJUST_POWER_STATE) after COMMIT_TABLE,
now handled in calling function
amdgpu_set_power_dpm_force_performance_level() - now checks thermal for swsmu systems before trying to change level
amdgpu_set_pp_od_clk_voltage() - now attempts to set fine_grain_clock_vol before swsmu edit dpm table
Signed-off-by: Darren Powell <darren.powell@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 98 +++++++++--------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 6 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 17 ++--
3 files changed, 48 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index ec5277ed74f7..1675a5e72a0d 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -370,14 +370,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
return -EINVAL;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_force_performance_level(&adev->smu, level);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
- }
- } else if (pp_funcs->force_performance_level) {
+ if (pp_funcs->force_performance_level) {
mutex_lock(&adev->pm.mutex);
if (adev->pm.dpm.thermal_active) {
mutex_unlock(&adev->pm.mutex);
@@ -615,15 +608,12 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
- } else if (adev->powerplay.pp_funcs->set_pp_table)
- amdgpu_dpm_set_pp_table(adev, buf, count);
+ ret = amdgpu_dpm_set_pp_table(adev, buf, count);
+ if (ret) {
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return ret;
+ }
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@@ -821,53 +811,42 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_od_edit_dpm_table(&adev->smu, type,
- parameter, parameter_size);
-
+ if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
+ ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
+ parameter,
+ parameter_size);
if (ret) {
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
return -EINVAL;
}
- } else {
-
- if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
- ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
- parameter,
- parameter_size);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
- }
- }
+ }
- if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
- ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
- parameter, parameter_size);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
- }
+ if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
+ ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
+ parameter, parameter_size);
+ if (ret) {
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return -EINVAL;
}
+ }
- if (type == PP_OD_COMMIT_DPM_TABLE) {
- if (adev->powerplay.pp_funcs->dispatch_tasks) {
- amdgpu_dpm_dispatch_task(adev,
- AMD_PP_TASK_READJUST_POWER_STATE,
- NULL);
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return count;
- } else {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
- }
+ if (type == PP_OD_COMMIT_DPM_TABLE) {
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ amdgpu_dpm_dispatch_task(adev,
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ NULL);
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return count;
+ } else {
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return -EINVAL;
}
}
+
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@@ -892,18 +871,13 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- size = smu_print_ppclk_levels(&adev->smu, OD_SCLK, buf);
- size += smu_print_ppclk_levels(&adev->smu, OD_MCLK, buf+size);
- size += smu_print_ppclk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
- size += smu_print_ppclk_levels(&adev->smu, OD_VDDGFX_OFFSET, buf+size);
- size += smu_print_ppclk_levels(&adev->smu, OD_RANGE, buf+size);
- size += smu_print_ppclk_levels(&adev->smu, OD_CCLK, buf+size);
- } else if (adev->powerplay.pp_funcs->print_clock_levels) {
+ if (adev->powerplay.pp_funcs->print_clock_levels) {
size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
+ size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf+size);
size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
+ size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
}
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index a2f4b8f1db4e..af71c7c6db46 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1242,7 +1242,7 @@ int smu_get_power_limit(struct smu_context *smu,
int smu_set_power_limit(void *handle, uint32_t limit);
int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf);
-int smu_od_edit_dpm_table(struct smu_context *smu,
+int smu_od_edit_dpm_table(void *handle,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size);
@@ -1294,7 +1294,7 @@ bool is_support_sw_smu(struct amdgpu_device *adev);
bool is_support_cclk_dpm(struct amdgpu_device *adev);
int smu_reset(struct smu_context *smu);
int smu_sys_get_pp_table(void *handle, char **table);
-int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
+int smu_sys_set_pp_table(void *handle, const char *buf, size_t size);
int smu_get_power_num_states(void *handle, struct pp_states_info *state_info);
enum amd_pm_state_type smu_get_current_power_state(void *handle);
int smu_write_watermarks_table(struct smu_context *smu);
@@ -1324,7 +1324,7 @@ u32 smu_get_sclk(void *handle, bool low);
int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
enum amd_dpm_forced_level smu_get_performance_level(void *handle);
-int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
+int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level);
int smu_set_display_count(struct smu_context *smu, uint32_t count);
int smu_set_ac_dc(struct smu_context *smu);
int smu_sys_get_pp_feature_mask(void *handle, char *buf);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 72501d8a80b9..f5d9590f2178 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -477,8 +477,9 @@ int smu_sys_get_pp_table(void *handle, char **table)
return powerplay_table_size;
}
-int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
+int smu_sys_set_pp_table(void *handle, const char *buf, size_t size)
{
+ struct smu_context *smu = handle;
struct smu_table_context *smu_table = &smu->smu_table;
ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
int ret = 0;
@@ -1775,8 +1776,9 @@ enum amd_dpm_forced_level smu_get_performance_level(void *handle)
return level;
}
-int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
+int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level)
{
+ struct smu_context *smu = handle;
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int ret = 0;
@@ -2278,10 +2280,11 @@ int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf)
return smu_print_smuclk_levels(smu, clk_type, buf);
}
-int smu_od_edit_dpm_table(struct smu_context *smu,
+int smu_od_edit_dpm_table(void *handle,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2291,11 +2294,6 @@ int smu_od_edit_dpm_table(struct smu_context *smu,
if (smu->ppt_funcs->od_edit_dpm_table) {
ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
- if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
- ret = smu_handle_task(smu,
- smu->smu_dpm.dpm_level,
- AMD_PP_TASK_READJUST_POWER_STATE,
- false);
}
mutex_unlock(&smu->mutex);
@@ -2950,6 +2948,7 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.get_fan_control_mode = smu_get_fan_control_mode,
.set_fan_speed_percent = smu_set_fan_speed_percent,
.get_fan_speed_percent = smu_get_fan_speed_percent,
+ .force_performance_level = smu_force_performance_level,
.read_sensor = smu_read_sensor,
.get_performance_level = smu_get_performance_level,
.get_current_power_state = smu_get_current_power_state,
@@ -2957,11 +2956,13 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.set_fan_speed_rpm = smu_set_fan_speed_rpm,
.get_pp_num_states = smu_get_power_num_states,
.get_pp_table = smu_sys_get_pp_table,
+ .set_pp_table = smu_sys_set_pp_table,
.switch_power_profile = smu_switch_power_profile,
/* export to amdgpu */
.dispatch_tasks = smu_handle_dpm_task,
.set_powergating_by_smu = smu_dpm_set_power_gate,
.set_power_limit = smu_set_power_limit,
+ .odn_edit_dpm_table = smu_od_edit_dpm_table,
.set_mp1_state = smu_set_mp1_state,
/* export to DC */
.get_sclk = smu_get_sclk,
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cevan.quan%40amd.com%7C032980474b064f959adb08d8d7b28a18%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637496509115947921%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=YPPZTA%2BGtDWywgk3gdw2TOkc1xcoP1M59Qh4%2BBuTy8c%3D&reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 0/8] amdgpu/pm: Powerplay API for smu
2021-01-13 3:27 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
@ 2021-01-14 17:48 ` Alex Deucher
0 siblings, 0 replies; 14+ messages in thread
From: Alex Deucher @ 2021-01-14 17:48 UTC (permalink / raw)
To: Darren Powell; +Cc: amd-gfx list
On Tue, Jan 12, 2021 at 10:28 PM Darren Powell <darren.powell@amd.com> wrote:
>
> === Description ===
> Patches to add the Powerplay API to smu and simplify dpm/pm calling code
>
> * Version 2 Updates
> 0001: updated the structure name to swsmu_pm_funcs
> 0002: No Changes
> 0003: changed error return value of smu_get_fan_control_mode to AMD_FAN_CTRL_NONE
> fixed type in amdgpu_hwmon_get_pwm1_enable() print statement
> fixed indent flagged by checkpatch.pl
> 0004: remove check for error during swsmu amdgpu_dpm_get_pp_num_states() call to match previous powerplay behaviour
> 0005: add comment to highlight assignment that changes uint32_t value to int
> fix errors flagged by checkpatch.pl
> 0006: fix errors flagged by checkpatch
> 0007: fix errors and warnings flagged by checkpatch
> 0008: No Changes
Feel free to pick up the RBs or ABs from the previous review that are
applicable.
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> === Test System ===
> * DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2)
> + ISO(Ubuntu 20.04.1 LTS)
> + Kernel(5.9.0-rc5-custom-pmcallback-00865-gd3b9ec1a13c9)
>
> === Patch Summary ===
> linux: (git://people.freedesktop.org/~agd5f/linux) origin/amd-staging-drm-next @ d3b9ec1a13c9
> + b401b8ff07ca amdgpu/pm: Powerplay API for smu , added get_performance_level
> + 924fb45c2fc9 amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to use API
> + 22459821a119 amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to use API
> + 9a1dff6ed4a4 amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use API
> + eeaf9dad054a amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor functions to use API
> + c10bf38a4250 amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functions
> + 73c150926ef3 amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
> + f840fb27c965 amdgpu/pm: Powerplay API for smu , updates to some pm functions
>
> === Tests ===
> ** 0001
> amdgpu_get_power_dpm_force_performance_level() <- /sys/class/drm/card0/device/power_dpm_force_performance_level
> ** 0002
> amdgpu_dpm_set_mp1_state <- systemctl suspend
> amdgpu_dpm_mode2_reset <- untested: needs Arctic Islands Hardware (VEGAx, RAVEN)
> amdgpu_dpm_switch_power_profile <- untested
> amdgpu_dpm_set_xgmi_pstate <- untested: amdgpu_xgmi_set_pstate():411 pstate switching disabled
> amdgpu_dpm_set_df_cstate <- untested: needs ras enabled hardware
> amdgpu_dpm_enable_mgpu_fan_boost <- untested: needs multi-gpu hardware
> ** 0003
> amdgpu_hwmon_get_pwm1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1_enable
> amdgpu_hwmon_set_pwm1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1_enable
> amdgpu_hwmon_set_pwm1 <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1
> amdgpu_hwmon_get_pwm1 <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1
> amdgpu_hwmon_get_fan1_input <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_input
> amdgpu_hwmon_get_fan1_target <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_target
> amdgpu_hwmon_set_fan1_target <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_target
> amdgpu_hwmon_get_fan1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_enable
> amdgpu_hwmon_set_fan1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_enable
> ** 0004
> amdgpu_get_power_dpm_state <- /sys/class/drm/card0/device/power_dpm_state
> amdgpu_set_power_dpm_force_performance_level <- /sys/class/drm/card0/device/power_dpm_force_performance_level
> amdgpu_get_pp_num_states <- /sys/class/drm/card0/device/pp_num_states
> amdgpu_get_pp_cur_state <- /sys/class/drm/card0/device/pp_cur_state
> amdgpu_get_pp_table <- /sys/class/drm/card0/device/pp_table
> amdgpu_get_pp_features <- /sys/class/drm/card0/device/pp_features
> amdgpu_hwmon_show_power_cap_max <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap_max
> amdgpu_hwmon_show_power_cap <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap
> amdgpu_hwmon_set_power_cap <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap
> ** 0005
> amdgpu_dpm_baco_enter <- untested: called from runtime.pm
> amdgpu_dpm_baco_exit <- untested: called from runtime.pm
> amdgpu_dpm_is_baco_supported <- untested: needs other Hardware(cik, vi, soc15)
> amdgpu_dpm_baco_reset <- untested: needs other Hardware(cik, vi, soc15)
> ** 0006
> amdgpu_get_pp_dpm_sclk <- /sys/class/drm/card0/device/pp_dpm_sclk
> amdgpu_set_pp_dpm_sclk <- /sys/class/drm/card0/device/pp_dpm_sclk
> amdgpu_get_pp_dpm_mclk <- /sys/class/drm/card0/device/pp_dpm_mclk
> amdgpu_set_pp_dpm_mclk <- /sys/class/drm/card0/device/pp_dpm_mclk
> amdgpu_get_pp_dpm_socclk <- /sys/class/drm/card0/device/pp_dpm_socclk
> amdgpu_set_pp_dpm_socclk <- /sys/class/drm/card0/device/pp_dpm_socclk
> amdgpu_get_pp_dpm_fclk <- /sys/class/drm/card0/device/pp_dpm_fclk
> amdgpu_set_pp_dpm_fclk <- /sys/class/drm/card0/device/pp_dpm_fclk
> amdgpu_get_pp_dpm_dcefclk <- /sys/class/drm/card0/device/pp_dpm_dcefclk
> amdgpu_set_pp_dpm_dcefclk <- /sys/class/drm/card0/device/pp_dpm_dcefclk
> amdgpu_get_pp_dpm_pcie <- /sys/class/drm/card0/device/pp_dpm_pcie
> amdgpu_set_pp_dpm_pcie <- /sys/class/drm/card0/device/pp_dpm_pcie
> amdgpu_get_pp_power_profile_mode <- /sys/class/drm/card0/device/pp_power_profile_mode
> amdgpu_set_pp_power_profile_mode <- /sys/class/drm/card0/device/pp_power_profile_mode
> amdgpu_get_gpu_metrics <- /sys/class/drm/card0/device/gpu_metrics
> ** 0007
> amdgpu_pm_compute_clocks <- untested
> amdgpu_dpm_set_powergating_by_smu <- untested
> amdgpu_dpm_get_mclk <- untested
> amdgpu_dpm_get_sclk <- untested
> ** 0008
> amdgpu_get_pp_od_clk_voltage <- /sys/class/drm/card0/device/pp_od_clk_voltage
> amdgpu_set_pp_od_clk_voltage <- /sys/class/drm/card0/device/pp_od_clk_voltage
> amdgpu_set_pp_table <- /sys/class/drm/card0/device/pp_table
> amdgpu_set_power_dpm_force_performance_level <- /sys/class/drm/card0/device/power_dpm_force_performance_level
>
> === Summary of Untested Functions ===
> ** 0002
> amdgpu_dpm_mode2_reset <- untested: needs Arctic Islands Hardware (VEGAx, RAVEN)
> amdgpu_dpm_switch_power_profile <- untested: called during initialization
> amdgpu_dpm_set_xgmi_pstate <- untested: amdgpu_xgmi_set_pstate():411 pstate switching disabled
> amdgpu_dpm_set_df_cstate <- untested: needs ras enabled hardware
> amdgpu_dpm_enable_mgpu_fan_boost <- untested: needs multi-gpu hardware
> ** 0005
> amdgpu_dpm_baco_enter <- untested: called from runtime.pm
> amdgpu_dpm_baco_exit <- untested: called from runtime.pm
> amdgpu_dpm_is_baco_supported <- untested: needs other Hardware(cik, vi, soc15)
> amdgpu_dpm_baco_reset <- untested: needs other Hardware(cik, vi, soc15)
> ** 0007
> amdgpu_pm_compute_clocks <- untested
> amdgpu_dpm_set_powergating_by_smu <- untested
> amdgpu_dpm_get_mclk <- untested
> amdgpu_dpm_get_sclk <- untested
> ** 0008
> amdgpu_get_pp_od_clk_voltage <- file not found
> amdgpu_set_pp_od_clk_voltage <- file not found
> amdgpu_set_pp_table <- no binary data to test with
>
>
> === Cover Letter ===
> Darren Powell (8):
> amdgpu/pm: Powerplay API for smu , added get_performance_level
> amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to
> use API
> amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to
> use API
> amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use
> API
> amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor
> functions to use API
> amdgpu/pm: Powerplay API for smu , changes to clock and profile mode
> functions
> amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
> amdgpu/pm: Powerplay API for smu , updates to some pm functions
>
> drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 228 +++------
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 597 +++++-----------------
> drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 79 ++-
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 358 ++++++++++---
> 4 files changed, 534 insertions(+), 728 deletions(-)
>
> --
> 2.25.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 0/8] amdgpu/pm: Powerplay API for smu
@ 2021-01-13 3:27 Darren Powell
2021-01-14 17:48 ` Alex Deucher
0 siblings, 1 reply; 14+ messages in thread
From: Darren Powell @ 2021-01-13 3:27 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
=== Description ===
Patches to add the Powerplay API to smu and simplify dpm/pm calling code
* Version 2 Updates
0001: updated the structure name to swsmu_pm_funcs
0002: No Changes
0003: changed error return value of smu_get_fan_control_mode to AMD_FAN_CTRL_NONE
fixed type in amdgpu_hwmon_get_pwm1_enable() print statement
fixed indent flagged by checkpatch.pl
0004: remove check for error during swsmu amdgpu_dpm_get_pp_num_states() call to match previous powerplay behaviour
0005: add comment to highlight assignment that changes uint32_t value to int
fix errors flagged by checkpatch.pl
0006: fix errors flagged by checkpatch
0007: fix errors and warnings flagged by checkpatch
0008: No Changes
=== Test System ===
* DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2)
+ ISO(Ubuntu 20.04.1 LTS)
+ Kernel(5.9.0-rc5-custom-pmcallback-00865-gd3b9ec1a13c9)
=== Patch Summary ===
linux: (git://people.freedesktop.org/~agd5f/linux) origin/amd-staging-drm-next @ d3b9ec1a13c9
+ b401b8ff07ca amdgpu/pm: Powerplay API for smu , added get_performance_level
+ 924fb45c2fc9 amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to use API
+ 22459821a119 amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to use API
+ 9a1dff6ed4a4 amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use API
+ eeaf9dad054a amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor functions to use API
+ c10bf38a4250 amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functions
+ 73c150926ef3 amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
+ f840fb27c965 amdgpu/pm: Powerplay API for smu , updates to some pm functions
=== Tests ===
** 0001
amdgpu_get_power_dpm_force_performance_level() <- /sys/class/drm/card0/device/power_dpm_force_performance_level
** 0002
amdgpu_dpm_set_mp1_state <- systemctl suspend
amdgpu_dpm_mode2_reset <- untested: needs Arctic Islands Hardware (VEGAx, RAVEN)
amdgpu_dpm_switch_power_profile <- untested
amdgpu_dpm_set_xgmi_pstate <- untested: amdgpu_xgmi_set_pstate():411 pstate switching disabled
amdgpu_dpm_set_df_cstate <- untested: needs ras enabled hardware
amdgpu_dpm_enable_mgpu_fan_boost <- untested: needs multi-gpu hardware
** 0003
amdgpu_hwmon_get_pwm1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1_enable
amdgpu_hwmon_set_pwm1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1_enable
amdgpu_hwmon_set_pwm1 <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1
amdgpu_hwmon_get_pwm1 <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1
amdgpu_hwmon_get_fan1_input <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_input
amdgpu_hwmon_get_fan1_target <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_target
amdgpu_hwmon_set_fan1_target <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_target
amdgpu_hwmon_get_fan1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_enable
amdgpu_hwmon_set_fan1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_enable
** 0004
amdgpu_get_power_dpm_state <- /sys/class/drm/card0/device/power_dpm_state
amdgpu_set_power_dpm_force_performance_level <- /sys/class/drm/card0/device/power_dpm_force_performance_level
amdgpu_get_pp_num_states <- /sys/class/drm/card0/device/pp_num_states
amdgpu_get_pp_cur_state <- /sys/class/drm/card0/device/pp_cur_state
amdgpu_get_pp_table <- /sys/class/drm/card0/device/pp_table
amdgpu_get_pp_features <- /sys/class/drm/card0/device/pp_features
amdgpu_hwmon_show_power_cap_max <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap_max
amdgpu_hwmon_show_power_cap <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap
amdgpu_hwmon_set_power_cap <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap
** 0005
amdgpu_dpm_baco_enter <- untested: called from runtime.pm
amdgpu_dpm_baco_exit <- untested: called from runtime.pm
amdgpu_dpm_is_baco_supported <- untested: needs other Hardware(cik, vi, soc15)
amdgpu_dpm_baco_reset <- untested: needs other Hardware(cik, vi, soc15)
** 0006
amdgpu_get_pp_dpm_sclk <- /sys/class/drm/card0/device/pp_dpm_sclk
amdgpu_set_pp_dpm_sclk <- /sys/class/drm/card0/device/pp_dpm_sclk
amdgpu_get_pp_dpm_mclk <- /sys/class/drm/card0/device/pp_dpm_mclk
amdgpu_set_pp_dpm_mclk <- /sys/class/drm/card0/device/pp_dpm_mclk
amdgpu_get_pp_dpm_socclk <- /sys/class/drm/card0/device/pp_dpm_socclk
amdgpu_set_pp_dpm_socclk <- /sys/class/drm/card0/device/pp_dpm_socclk
amdgpu_get_pp_dpm_fclk <- /sys/class/drm/card0/device/pp_dpm_fclk
amdgpu_set_pp_dpm_fclk <- /sys/class/drm/card0/device/pp_dpm_fclk
amdgpu_get_pp_dpm_dcefclk <- /sys/class/drm/card0/device/pp_dpm_dcefclk
amdgpu_set_pp_dpm_dcefclk <- /sys/class/drm/card0/device/pp_dpm_dcefclk
amdgpu_get_pp_dpm_pcie <- /sys/class/drm/card0/device/pp_dpm_pcie
amdgpu_set_pp_dpm_pcie <- /sys/class/drm/card0/device/pp_dpm_pcie
amdgpu_get_pp_power_profile_mode <- /sys/class/drm/card0/device/pp_power_profile_mode
amdgpu_set_pp_power_profile_mode <- /sys/class/drm/card0/device/pp_power_profile_mode
amdgpu_get_gpu_metrics <- /sys/class/drm/card0/device/gpu_metrics
** 0007
amdgpu_pm_compute_clocks <- untested
amdgpu_dpm_set_powergating_by_smu <- untested
amdgpu_dpm_get_mclk <- untested
amdgpu_dpm_get_sclk <- untested
** 0008
amdgpu_get_pp_od_clk_voltage <- /sys/class/drm/card0/device/pp_od_clk_voltage
amdgpu_set_pp_od_clk_voltage <- /sys/class/drm/card0/device/pp_od_clk_voltage
amdgpu_set_pp_table <- /sys/class/drm/card0/device/pp_table
amdgpu_set_power_dpm_force_performance_level <- /sys/class/drm/card0/device/power_dpm_force_performance_level
=== Summary of Untested Functions ===
** 0002
amdgpu_dpm_mode2_reset <- untested: needs Arctic Islands Hardware (VEGAx, RAVEN)
amdgpu_dpm_switch_power_profile <- untested: called during initialization
amdgpu_dpm_set_xgmi_pstate <- untested: amdgpu_xgmi_set_pstate():411 pstate switching disabled
amdgpu_dpm_set_df_cstate <- untested: needs ras enabled hardware
amdgpu_dpm_enable_mgpu_fan_boost <- untested: needs multi-gpu hardware
** 0005
amdgpu_dpm_baco_enter <- untested: called from runtime.pm
amdgpu_dpm_baco_exit <- untested: called from runtime.pm
amdgpu_dpm_is_baco_supported <- untested: needs other Hardware(cik, vi, soc15)
amdgpu_dpm_baco_reset <- untested: needs other Hardware(cik, vi, soc15)
** 0007
amdgpu_pm_compute_clocks <- untested
amdgpu_dpm_set_powergating_by_smu <- untested
amdgpu_dpm_get_mclk <- untested
amdgpu_dpm_get_sclk <- untested
** 0008
amdgpu_get_pp_od_clk_voltage <- file not found
amdgpu_set_pp_od_clk_voltage <- file not found
amdgpu_set_pp_table <- no binary data to test with
=== Cover Letter ===
Darren Powell (8):
amdgpu/pm: Powerplay API for smu , added get_performance_level
amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to
use API
amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to
use API
amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use
API
amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor
functions to use API
amdgpu/pm: Powerplay API for smu , changes to clock and profile mode
functions
amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
amdgpu/pm: Powerplay API for smu , updates to some pm functions
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 228 +++------
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 597 +++++-----------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 79 ++-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 358 ++++++++++---
4 files changed, 534 insertions(+), 728 deletions(-)
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 0/8] amdgpu/pm: Powerplay API for smu
2020-12-19 0:48 Darren Powell
@ 2020-12-21 3:04 ` Quan, Evan
0 siblings, 0 replies; 14+ messages in thread
From: Quan, Evan @ 2020-12-21 3:04 UTC (permalink / raw)
To: Powell, Darren, amd-gfx; +Cc: Powell, Darren
[AMD Official Use Only - Internal Distribution Only]
Thanks for these cleaups. The series is acked-by: Evan Quan <evan.quan@amd.com>
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Darren Powell
Sent: Saturday, December 19, 2020 8:48 AM
To: amd-gfx@lists.freedesktop.org
Cc: Powell, Darren <Darren.Powell@amd.com>
Subject: [PATCH 0/8] amdgpu/pm: Powerplay API for smu
=== Description ===
Patches to add the Powerplay API to smu and simplify dpm/pm calling code
=== Test System ===
* DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2) + ISO(Ubuntu 20.04.1 LTS) + Kernel(5.9.0-rc5-custom-pmcallback-00865-gd3b9ec1a13c9)
=== Patch Summary ===
linux: (git://people.freedesktop.org/~agd5f/linux) origin/amd-staging-drm-next @ d3b9ec1a13c9
+ 05e1d87d1cb4 amdgpu/pm: Powerplay API for smu , added get_performance_level
+ b9e2be067f01 amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to use API
+ 9add1d6485a4 amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to use API
+ c02b35074f14 amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use API
+ 483bd1207f2c amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor functions to use API
+ f91c1665e30e amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functions
+ d1400afa4785 amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
+ 2f12f7afa690 amdgpu/pm: Powerplay API for smu , updates to some pm functions
=== Tests ===
** 0001
amdgpu_get_power_dpm_force_performance_level() <- /sys/class/drm/card0/device/power_dpm_force_performance_level
** 0002
amdgpu_dpm_set_mp1_state <- systemctl suspend
amdgpu_dpm_mode2_reset <- untested: needs Arctic Islands Hardware (VEGAx, RAVEN)
amdgpu_dpm_switch_power_profile <- untested
amdgpu_dpm_set_xgmi_pstate <- untested: amdgpu_xgmi_set_pstate():411 pstate switching disabled
amdgpu_dpm_set_df_cstate <- untested: needs ras enabled hardware
amdgpu_dpm_enable_mgpu_fan_boost <- untested: needs multi-gpu hardware
** 0003
amdgpu_hwmon_get_pwm1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1_enable
amdgpu_hwmon_set_pwm1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1_enable
amdgpu_hwmon_set_pwm1 <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1
amdgpu_hwmon_get_pwm1 <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1
amdgpu_hwmon_get_fan1_input <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_input
amdgpu_hwmon_get_fan1_target <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_target
amdgpu_hwmon_set_fan1_target <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_target
amdgpu_hwmon_get_fan1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_enable
amdgpu_hwmon_set_fan1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_enable
** 0004
amdgpu_get_power_dpm_state <- /sys/class/drm/card0/device/power_dpm_state
amdgpu_set_power_dpm_force_performance_level <- /sys/class/drm/card0/device/power_dpm_force_performance_level
amdgpu_get_pp_num_states <- /sys/class/drm/card0/device/pp_num_states
amdgpu_get_pp_cur_state <- /sys/class/drm/card0/device/pp_cur_state
amdgpu_get_pp_table <- /sys/class/drm/card0/device/pp_table
amdgpu_get_pp_features <- /sys/class/drm/card0/device/pp_features
amdgpu_hwmon_show_power_cap_max <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap_max
amdgpu_hwmon_show_power_cap <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap
amdgpu_hwmon_set_power_cap <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap
** 0005
amdgpu_dpm_baco_enter <- untested: called from runtime.pm
amdgpu_dpm_baco_exit <- untested: called from runtime.pm
amdgpu_dpm_is_baco_supported <- untested: needs other Hardware(cik, vi, soc15)
amdgpu_dpm_baco_reset <- untested: needs other Hardware(cik, vi, soc15)
** 0006
amdgpu_get_pp_dpm_sclk <- /sys/class/drm/card0/device/pp_dpm_sclk
amdgpu_set_pp_dpm_sclk <- /sys/class/drm/card0/device/pp_dpm_sclk
amdgpu_get_pp_dpm_mclk <- /sys/class/drm/card0/device/pp_dpm_mclk
amdgpu_set_pp_dpm_mclk <- /sys/class/drm/card0/device/pp_dpm_mclk
amdgpu_get_pp_dpm_socclk <- /sys/class/drm/card0/device/pp_dpm_socclk
amdgpu_set_pp_dpm_socclk <- /sys/class/drm/card0/device/pp_dpm_socclk
amdgpu_get_pp_dpm_fclk <- /sys/class/drm/card0/device/pp_dpm_fclk
amdgpu_set_pp_dpm_fclk <- /sys/class/drm/card0/device/pp_dpm_fclk
amdgpu_get_pp_dpm_dcefclk <- /sys/class/drm/card0/device/pp_dpm_dcefclk
amdgpu_set_pp_dpm_dcefclk <- /sys/class/drm/card0/device/pp_dpm_dcefclk
amdgpu_get_pp_dpm_pcie <- /sys/class/drm/card0/device/pp_dpm_pcie
amdgpu_set_pp_dpm_pcie <- /sys/class/drm/card0/device/pp_dpm_pcie
amdgpu_get_pp_power_profile_mode <- /sys/class/drm/card0/device/pp_power_profile_mode
amdgpu_set_pp_power_profile_mode <- /sys/class/drm/card0/device/pp_power_profile_mode
amdgpu_get_gpu_metrics <- /sys/class/drm/card0/device/gpu_metrics
** 0007
amdgpu_pm_compute_clocks <- untested
amdgpu_dpm_set_powergating_by_smu <- untested
amdgpu_dpm_get_mclk <- untested
amdgpu_dpm_get_sclk <- untested
** 0008
amdgpu_get_pp_od_clk_voltage <- /sys/class/drm/card0/device/pp_od_clk_voltage
amdgpu_set_pp_od_clk_voltage <- /sys/class/drm/card0/device/pp_od_clk_voltage
amdgpu_set_pp_table <- /sys/class/drm/card0/device/pp_table
amdgpu_set_power_dpm_force_performance_level <- /sys/class/drm/card0/device/power_dpm_force_performance_level
=== Summary of Untested Functions ===
** 0002
amdgpu_dpm_mode2_reset <- untested: needs Arctic Islands Hardware (VEGAx, RAVEN)
amdgpu_dpm_switch_power_profile <- untested: called during initialization
amdgpu_dpm_set_xgmi_pstate <- untested: amdgpu_xgmi_set_pstate():411 pstate switching disabled
amdgpu_dpm_set_df_cstate <- untested: needs ras enabled hardware
amdgpu_dpm_enable_mgpu_fan_boost <- untested: needs multi-gpu hardware
** 0005
amdgpu_dpm_baco_enter <- untested: called from runtime.pm
amdgpu_dpm_baco_exit <- untested: called from runtime.pm
amdgpu_dpm_is_baco_supported <- untested: needs other Hardware(cik, vi, soc15)
amdgpu_dpm_baco_reset <- untested: needs other Hardware(cik, vi, soc15)
** 0007
amdgpu_pm_compute_clocks <- untested
amdgpu_dpm_set_powergating_by_smu <- untested
amdgpu_dpm_get_mclk <- untested
amdgpu_dpm_get_sclk <- untested
** 0008
amdgpu_get_pp_od_clk_voltage <- file not found
amdgpu_set_pp_od_clk_voltage <- file not found
amdgpu_set_pp_table <- no binary data to test with
=== Cover Letter ===
Darren Powell (8):
amdgpu/pm: Powerplay API for smu , added get_performance_level
amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to
use API
amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to
use API
amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use
API
amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor
functions to use API
amdgpu/pm: Powerplay API for smu , changes to clock and profile mode
functions
amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
amdgpu/pm: Powerplay API for smu , updates to some pm functions
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 226 +++-----
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 596 +++++-----------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 79 ++-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 334 +++++++++---
4 files changed, 511 insertions(+), 724 deletions(-)
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cevan.quan%40amd.com%7C35efd75734c84eae04bf08d8a3b7df1a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637439357421991565%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=cvVKTf%2FK%2FNuC2SE7H%2F88DRRfWmxVFqETJ%2BlROM6JSGs%3D&reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 0/8] amdgpu/pm: Powerplay API for smu
@ 2020-12-19 0:48 Darren Powell
2020-12-21 3:04 ` Quan, Evan
0 siblings, 1 reply; 14+ messages in thread
From: Darren Powell @ 2020-12-19 0:48 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
=== Description ===
Patches to add the Powerplay API to smu and simplify dpm/pm calling code
=== Test System ===
* DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2)
+ ISO(Ubuntu 20.04.1 LTS)
+ Kernel(5.9.0-rc5-custom-pmcallback-00865-gd3b9ec1a13c9)
=== Patch Summary ===
linux: (git://people.freedesktop.org/~agd5f/linux) origin/amd-staging-drm-next @ d3b9ec1a13c9
+ 05e1d87d1cb4 amdgpu/pm: Powerplay API for smu , added get_performance_level
+ b9e2be067f01 amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to use API
+ 9add1d6485a4 amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to use API
+ c02b35074f14 amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use API
+ 483bd1207f2c amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor functions to use API
+ f91c1665e30e amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functions
+ d1400afa4785 amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
+ 2f12f7afa690 amdgpu/pm: Powerplay API for smu , updates to some pm functions
=== Tests ===
** 0001
amdgpu_get_power_dpm_force_performance_level() <- /sys/class/drm/card0/device/power_dpm_force_performance_level
** 0002
amdgpu_dpm_set_mp1_state <- systemctl suspend
amdgpu_dpm_mode2_reset <- untested: needs Arctic Islands Hardware (VEGAx, RAVEN)
amdgpu_dpm_switch_power_profile <- untested
amdgpu_dpm_set_xgmi_pstate <- untested: amdgpu_xgmi_set_pstate():411 pstate switching disabled
amdgpu_dpm_set_df_cstate <- untested: needs ras enabled hardware
amdgpu_dpm_enable_mgpu_fan_boost <- untested: needs multi-gpu hardware
** 0003
amdgpu_hwmon_get_pwm1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1_enable
amdgpu_hwmon_set_pwm1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1_enable
amdgpu_hwmon_set_pwm1 <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1
amdgpu_hwmon_get_pwm1 <- /sys/class/drm/card0/device/hwmon/hwmon?/pwm1
amdgpu_hwmon_get_fan1_input <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_input
amdgpu_hwmon_get_fan1_target <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_target
amdgpu_hwmon_set_fan1_target <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_target
amdgpu_hwmon_get_fan1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_enable
amdgpu_hwmon_set_fan1_enable <- /sys/class/drm/card0/device/hwmon/hwmon?/fan1_enable
** 0004
amdgpu_get_power_dpm_state <- /sys/class/drm/card0/device/power_dpm_state
amdgpu_set_power_dpm_force_performance_level <- /sys/class/drm/card0/device/power_dpm_force_performance_level
amdgpu_get_pp_num_states <- /sys/class/drm/card0/device/pp_num_states
amdgpu_get_pp_cur_state <- /sys/class/drm/card0/device/pp_cur_state
amdgpu_get_pp_table <- /sys/class/drm/card0/device/pp_table
amdgpu_get_pp_features <- /sys/class/drm/card0/device/pp_features
amdgpu_hwmon_show_power_cap_max <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap_max
amdgpu_hwmon_show_power_cap <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap
amdgpu_hwmon_set_power_cap <- /sys/class/drm/card0/device/hwmon/hwmon?/power1_cap
** 0005
amdgpu_dpm_baco_enter <- untested: called from runtime.pm
amdgpu_dpm_baco_exit <- untested: called from runtime.pm
amdgpu_dpm_is_baco_supported <- untested: needs other Hardware(cik, vi, soc15)
amdgpu_dpm_baco_reset <- untested: needs other Hardware(cik, vi, soc15)
** 0006
amdgpu_get_pp_dpm_sclk <- /sys/class/drm/card0/device/pp_dpm_sclk
amdgpu_set_pp_dpm_sclk <- /sys/class/drm/card0/device/pp_dpm_sclk
amdgpu_get_pp_dpm_mclk <- /sys/class/drm/card0/device/pp_dpm_mclk
amdgpu_set_pp_dpm_mclk <- /sys/class/drm/card0/device/pp_dpm_mclk
amdgpu_get_pp_dpm_socclk <- /sys/class/drm/card0/device/pp_dpm_socclk
amdgpu_set_pp_dpm_socclk <- /sys/class/drm/card0/device/pp_dpm_socclk
amdgpu_get_pp_dpm_fclk <- /sys/class/drm/card0/device/pp_dpm_fclk
amdgpu_set_pp_dpm_fclk <- /sys/class/drm/card0/device/pp_dpm_fclk
amdgpu_get_pp_dpm_dcefclk <- /sys/class/drm/card0/device/pp_dpm_dcefclk
amdgpu_set_pp_dpm_dcefclk <- /sys/class/drm/card0/device/pp_dpm_dcefclk
amdgpu_get_pp_dpm_pcie <- /sys/class/drm/card0/device/pp_dpm_pcie
amdgpu_set_pp_dpm_pcie <- /sys/class/drm/card0/device/pp_dpm_pcie
amdgpu_get_pp_power_profile_mode <- /sys/class/drm/card0/device/pp_power_profile_mode
amdgpu_set_pp_power_profile_mode <- /sys/class/drm/card0/device/pp_power_profile_mode
amdgpu_get_gpu_metrics <- /sys/class/drm/card0/device/gpu_metrics
** 0007
amdgpu_pm_compute_clocks <- untested
amdgpu_dpm_set_powergating_by_smu <- untested
amdgpu_dpm_get_mclk <- untested
amdgpu_dpm_get_sclk <- untested
** 0008
amdgpu_get_pp_od_clk_voltage <- /sys/class/drm/card0/device/pp_od_clk_voltage
amdgpu_set_pp_od_clk_voltage <- /sys/class/drm/card0/device/pp_od_clk_voltage
amdgpu_set_pp_table <- /sys/class/drm/card0/device/pp_table
amdgpu_set_power_dpm_force_performance_level <- /sys/class/drm/card0/device/power_dpm_force_performance_level
=== Summary of Untested Functions ===
** 0002
amdgpu_dpm_mode2_reset <- untested: needs Arctic Islands Hardware (VEGAx, RAVEN)
amdgpu_dpm_switch_power_profile <- untested: called during initialization
amdgpu_dpm_set_xgmi_pstate <- untested: amdgpu_xgmi_set_pstate():411 pstate switching disabled
amdgpu_dpm_set_df_cstate <- untested: needs ras enabled hardware
amdgpu_dpm_enable_mgpu_fan_boost <- untested: needs multi-gpu hardware
** 0005
amdgpu_dpm_baco_enter <- untested: called from runtime.pm
amdgpu_dpm_baco_exit <- untested: called from runtime.pm
amdgpu_dpm_is_baco_supported <- untested: needs other Hardware(cik, vi, soc15)
amdgpu_dpm_baco_reset <- untested: needs other Hardware(cik, vi, soc15)
** 0007
amdgpu_pm_compute_clocks <- untested
amdgpu_dpm_set_powergating_by_smu <- untested
amdgpu_dpm_get_mclk <- untested
amdgpu_dpm_get_sclk <- untested
** 0008
amdgpu_get_pp_od_clk_voltage <- file not found
amdgpu_set_pp_od_clk_voltage <- file not found
amdgpu_set_pp_table <- no binary data to test with
=== Cover Letter ===
Darren Powell (8):
amdgpu/pm: Powerplay API for smu , added get_performance_level
amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to
use API
amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to
use API
amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use
API
amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor
functions to use API
amdgpu/pm: Powerplay API for smu , changes to clock and profile mode
functions
amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API
amdgpu/pm: Powerplay API for smu , updates to some pm functions
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 226 +++-----
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 596 +++++-----------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 79 ++-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 334 +++++++++---
4 files changed, 511 insertions(+), 724 deletions(-)
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-02-24 4:17 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-23 4:20 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
2021-02-23 4:20 ` [PATCH 1/8] amdgpu/pm: Powerplay API for smu , added get_performance_level Darren Powell
2021-02-23 4:20 ` [PATCH 2/8] amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to use API Darren Powell
2021-02-23 4:20 ` [PATCH 3/8] amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan " Darren Powell
2021-02-23 4:20 ` [PATCH 4/8] amdgpu/pm: Powerplay API for smu , changed 9 pm power " Darren Powell
2021-02-23 4:20 ` [PATCH 5/8] amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor " Darren Powell
2021-02-23 4:20 ` [PATCH 6/8] amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functions Darren Powell
2021-02-23 4:20 ` [PATCH 7/8] amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use API Darren Powell
2021-02-23 4:20 ` [PATCH 8/8] amdgpu/pm: Powerplay API for smu , updates to some pm functions Darren Powell
2021-02-24 4:17 ` Quan, Evan
-- strict thread matches above, loose matches on Subject: below --
2021-01-13 3:27 [PATCH 0/8] amdgpu/pm: Powerplay API for smu Darren Powell
2021-01-14 17:48 ` Alex Deucher
2020-12-19 0:48 Darren Powell
2020-12-21 3:04 ` Quan, Evan
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.