* [PATCH v2] selftests/powerpc: Fix L1D flushing tests for Power10
@ 2021-02-23 7:02 Russell Currey
2021-02-24 0:42 ` Daniel Axtens
2021-03-31 1:09 ` Michael Ellerman
0 siblings, 2 replies; 3+ messages in thread
From: Russell Currey @ 2021-02-23 7:02 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Russell Currey, dja
The rfi_flush and entry_flush selftests work by using the PM_LD_MISS_L1
perf event to count L1D misses. The value of this event has changed
over time:
- Power7 uses 0x400f0
- Power8 and Power9 use both 0x400f0 and 0x3e054
- Power10 uses only 0x3e054
Rather than relying on raw values, configure perf to count L1D read
misses in the most explicit way available.
This fixes the selftests to work on systems without 0x400f0 as
PM_LD_MISS_L1, and should change no behaviour for systems that the tests
already worked on.
The only potential downside is that referring to a specific perf event
requires PMU support implemented in the kernel for that platform.
Signed-off-by: Russell Currey <ruscur@russell.cc>
---
v2: Move away from raw events as suggested by mpe
tools/testing/selftests/powerpc/security/entry_flush.c | 2 +-
tools/testing/selftests/powerpc/security/flush_utils.h | 4 ++++
tools/testing/selftests/powerpc/security/rfi_flush.c | 2 +-
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/powerpc/security/entry_flush.c b/tools/testing/selftests/powerpc/security/entry_flush.c
index 78cf914fa321..68ce377b205e 100644
--- a/tools/testing/selftests/powerpc/security/entry_flush.c
+++ b/tools/testing/selftests/powerpc/security/entry_flush.c
@@ -53,7 +53,7 @@ int entry_flush_test(void)
entry_flush = entry_flush_orig;
- fd = perf_event_open_counter(PERF_TYPE_RAW, /* L1d miss */ 0x400f0, -1);
+ fd = perf_event_open_counter(PERF_TYPE_HW_CACHE, PERF_L1D_READ_MISS_CONFIG, -1);
FAIL_IF(fd < 0);
p = (char *)memalign(zero_size, CACHELINE_SIZE);
diff --git a/tools/testing/selftests/powerpc/security/flush_utils.h b/tools/testing/selftests/powerpc/security/flush_utils.h
index 07a5eb301466..7a3d60292916 100644
--- a/tools/testing/selftests/powerpc/security/flush_utils.h
+++ b/tools/testing/selftests/powerpc/security/flush_utils.h
@@ -9,6 +9,10 @@
#define CACHELINE_SIZE 128
+#define PERF_L1D_READ_MISS_CONFIG ((PERF_COUNT_HW_CACHE_L1D) | \
+ (PERF_COUNT_HW_CACHE_OP_READ << 8) | \
+ (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))
+
void syscall_loop(char *p, unsigned long iterations,
unsigned long zero_size);
diff --git a/tools/testing/selftests/powerpc/security/rfi_flush.c b/tools/testing/selftests/powerpc/security/rfi_flush.c
index 7565fd786640..f73484a6470f 100644
--- a/tools/testing/selftests/powerpc/security/rfi_flush.c
+++ b/tools/testing/selftests/powerpc/security/rfi_flush.c
@@ -54,7 +54,7 @@ int rfi_flush_test(void)
rfi_flush = rfi_flush_orig;
- fd = perf_event_open_counter(PERF_TYPE_RAW, /* L1d miss */ 0x400f0, -1);
+ fd = perf_event_open_counter(PERF_TYPE_HW_CACHE, PERF_L1D_READ_MISS_CONFIG, -1);
FAIL_IF(fd < 0);
p = (char *)memalign(zero_size, CACHELINE_SIZE);
--
2.30.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] selftests/powerpc: Fix L1D flushing tests for Power10
2021-02-23 7:02 [PATCH v2] selftests/powerpc: Fix L1D flushing tests for Power10 Russell Currey
@ 2021-02-24 0:42 ` Daniel Axtens
2021-03-31 1:09 ` Michael Ellerman
1 sibling, 0 replies; 3+ messages in thread
From: Daniel Axtens @ 2021-02-24 0:42 UTC (permalink / raw)
To: Russell Currey, linuxppc-dev
Russell Currey <ruscur@russell.cc> writes:
> The rfi_flush and entry_flush selftests work by using the PM_LD_MISS_L1
> perf event to count L1D misses. The value of this event has changed
> over time:
>
> - Power7 uses 0x400f0
> - Power8 and Power9 use both 0x400f0 and 0x3e054
> - Power10 uses only 0x3e054
>
> Rather than relying on raw values, configure perf to count L1D read
> misses in the most explicit way available.
>
> This fixes the selftests to work on systems without 0x400f0 as
> PM_LD_MISS_L1, and should change no behaviour for systems that the tests
> already worked on.
>
> The only potential downside is that referring to a specific perf event
> requires PMU support implemented in the kernel for that platform.
So, IIUC:
- if you used raw events and ran the binary on a P10 system using an
older kernel that did not support P10 PMU events, you would still get
valid results
- but, if the HW perf event changes again, we have the same issue with
failing tests
vs
- if you use symbolic events and run the binary on a P10 system using
an older kernel that does not support P10 PMU events, you would not
be able to run the test.
- but, if the HW perf event changes again, the test will continue to
work.
This seems like the correct tradeoff to make.
Having spent some quality time with these tests in the past:
Acked-by: Daniel Axtens <dja@axtens.net>
Kind regards,
Daniel
>
> Signed-off-by: Russell Currey <ruscur@russell.cc>
> ---
> v2: Move away from raw events as suggested by mpe
>
> tools/testing/selftests/powerpc/security/entry_flush.c | 2 +-
> tools/testing/selftests/powerpc/security/flush_utils.h | 4 ++++
> tools/testing/selftests/powerpc/security/rfi_flush.c | 2 +-
> 3 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/tools/testing/selftests/powerpc/security/entry_flush.c b/tools/testing/selftests/powerpc/security/entry_flush.c
> index 78cf914fa321..68ce377b205e 100644
> --- a/tools/testing/selftests/powerpc/security/entry_flush.c
> +++ b/tools/testing/selftests/powerpc/security/entry_flush.c
> @@ -53,7 +53,7 @@ int entry_flush_test(void)
>
> entry_flush = entry_flush_orig;
>
> - fd = perf_event_open_counter(PERF_TYPE_RAW, /* L1d miss */ 0x400f0, -1);
> + fd = perf_event_open_counter(PERF_TYPE_HW_CACHE, PERF_L1D_READ_MISS_CONFIG, -1);
> FAIL_IF(fd < 0);
>
> p = (char *)memalign(zero_size, CACHELINE_SIZE);
> diff --git a/tools/testing/selftests/powerpc/security/flush_utils.h b/tools/testing/selftests/powerpc/security/flush_utils.h
> index 07a5eb301466..7a3d60292916 100644
> --- a/tools/testing/selftests/powerpc/security/flush_utils.h
> +++ b/tools/testing/selftests/powerpc/security/flush_utils.h
> @@ -9,6 +9,10 @@
>
> #define CACHELINE_SIZE 128
>
> +#define PERF_L1D_READ_MISS_CONFIG ((PERF_COUNT_HW_CACHE_L1D) | \
> + (PERF_COUNT_HW_CACHE_OP_READ << 8) | \
> + (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))
> +
> void syscall_loop(char *p, unsigned long iterations,
> unsigned long zero_size);
>
> diff --git a/tools/testing/selftests/powerpc/security/rfi_flush.c b/tools/testing/selftests/powerpc/security/rfi_flush.c
> index 7565fd786640..f73484a6470f 100644
> --- a/tools/testing/selftests/powerpc/security/rfi_flush.c
> +++ b/tools/testing/selftests/powerpc/security/rfi_flush.c
> @@ -54,7 +54,7 @@ int rfi_flush_test(void)
>
> rfi_flush = rfi_flush_orig;
>
> - fd = perf_event_open_counter(PERF_TYPE_RAW, /* L1d miss */ 0x400f0, -1);
> + fd = perf_event_open_counter(PERF_TYPE_HW_CACHE, PERF_L1D_READ_MISS_CONFIG, -1);
> FAIL_IF(fd < 0);
>
> p = (char *)memalign(zero_size, CACHELINE_SIZE);
> --
> 2.30.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] selftests/powerpc: Fix L1D flushing tests for Power10
2021-02-23 7:02 [PATCH v2] selftests/powerpc: Fix L1D flushing tests for Power10 Russell Currey
2021-02-24 0:42 ` Daniel Axtens
@ 2021-03-31 1:09 ` Michael Ellerman
1 sibling, 0 replies; 3+ messages in thread
From: Michael Ellerman @ 2021-03-31 1:09 UTC (permalink / raw)
To: Russell Currey, linuxppc-dev; +Cc: dja
On Tue, 23 Feb 2021 17:02:27 +1000, Russell Currey wrote:
> The rfi_flush and entry_flush selftests work by using the PM_LD_MISS_L1
> perf event to count L1D misses. The value of this event has changed
> over time:
>
> - Power7 uses 0x400f0
> - Power8 and Power9 use both 0x400f0 and 0x3e054
> - Power10 uses only 0x3e054
>
> [...]
Applied to powerpc/next.
[1/1] selftests/powerpc: Fix L1D flushing tests for Power10
https://git.kernel.org/powerpc/c/3a72c94ebfb1f171eba0715998010678a09ec796
cheers
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-02-24 0:42 ` Daniel Axtens
2021-03-31 1:09 ` Michael Ellerman
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