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* [PATCH 1/3] powernv/memtrace: Allow mmaping trace buffers
@ 2021-02-25  3:21 Jordan Niethe
  2021-02-25  3:21 ` [PATCH 2/3] selftests/powerpc: Suggest memtrace instead of /dev/mem for ci memory Jordan Niethe
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Jordan Niethe @ 2021-02-25  3:21 UTC (permalink / raw)
  To: linuxppc-dev; +Cc: Jordan Niethe

Let the memory removed from the linear mapping to be used for the trace
buffers be mmaped. This is a useful way of providing cache-inhibited
memory for the alignment_handler selftest.

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
---
 arch/powerpc/platforms/powernv/memtrace.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/platforms/powernv/memtrace.c b/arch/powerpc/platforms/powernv/memtrace.c
index 5fc9408bb0b3..8a1df39305e9 100644
--- a/arch/powerpc/platforms/powernv/memtrace.c
+++ b/arch/powerpc/platforms/powernv/memtrace.c
@@ -45,10 +45,26 @@ static ssize_t memtrace_read(struct file *filp, char __user *ubuf,
 	return simple_read_from_buffer(ubuf, count, ppos, ent->mem, ent->size);
 }
 
+int memtrace_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	struct memtrace_entry *ent = filp->private_data;
+
+	if (ent->size < vma->vm_end - vma->vm_start)
+		return -EINVAL;
+
+	if (vma->vm_pgoff << PAGE_SHIFT >= ent->size)
+		return -EINVAL;
+
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+	return remap_pfn_range(vma, vma->vm_start, PHYS_PFN(ent->start) + vma->vm_pgoff,
+			       vma->vm_end - vma->vm_start, vma->vm_page_prot);
+}
+
 static const struct file_operations memtrace_fops = {
 	.llseek = default_llseek,
 	.read	= memtrace_read,
 	.open	= simple_open,
+	.mmap   = memtrace_mmap,
 };
 
 static void memtrace_clear_range(unsigned long start_pfn,
@@ -158,7 +174,7 @@ static int memtrace_init_debugfs(void)
 		dir = debugfs_create_dir(ent->name, memtrace_debugfs_dir);
 
 		ent->dir = dir;
-		debugfs_create_file("trace", 0400, dir, ent, &memtrace_fops);
+		debugfs_create_file_unsafe("trace", 0600, dir, ent, &memtrace_fops);
 		debugfs_create_x64("start", 0400, dir, &ent->start);
 		debugfs_create_x64("size", 0400, dir, &ent->size);
 	}
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 2/3] selftests/powerpc: Suggest memtrace instead of /dev/mem for ci memory
  2021-02-25  3:21 [PATCH 1/3] powernv/memtrace: Allow mmaping trace buffers Jordan Niethe
@ 2021-02-25  3:21 ` Jordan Niethe
  2021-02-25  3:21 ` [PATCH 3/3] powerpc/sstep: Always test lmw and stmw Jordan Niethe
  2021-04-10 14:28 ` [PATCH 1/3] powernv/memtrace: Allow mmaping trace buffers Michael Ellerman
  2 siblings, 0 replies; 6+ messages in thread
From: Jordan Niethe @ 2021-02-25  3:21 UTC (permalink / raw)
  To: linuxppc-dev; +Cc: Jordan Niethe

The suggested alternative for getting cache-inhibited memory with 'mem='
and /dev/mem is pretty hacky. Also, PAPR guests do not allow system
memory to be mapped cache-inhibited so despite /dev/mem being available
this will not work which can cause confusion.  Instead recommend using
the memtrace buffers. memtrace is only available on powernv so there
will not be any chance of trying to do this in a guest.

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
---
 .../selftests/powerpc/alignment/alignment_handler.c   | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/tools/testing/selftests/powerpc/alignment/alignment_handler.c b/tools/testing/selftests/powerpc/alignment/alignment_handler.c
index cb53a8b777e6..f5eb5b85a2cf 100644
--- a/tools/testing/selftests/powerpc/alignment/alignment_handler.c
+++ b/tools/testing/selftests/powerpc/alignment/alignment_handler.c
@@ -10,16 +10,7 @@
  *
  * We create two sets of source and destination buffers, one in regular memory,
  * the other cache-inhibited (by default we use /dev/fb0 for this, but an
- * alterative path for cache-inhibited memory may be provided).
- *
- * One way to get cache-inhibited memory is to use the "mem" kernel parameter
- * to limit the kernel to less memory than actually exists.  Addresses above
- * the limit may still be accessed but will be treated as cache-inhibited. For
- * example, if there is actually 4GB of memory and the parameter "mem=3GB" is
- * used, memory from address 0xC0000000 onwards is treated as cache-inhibited.
- * To access this region /dev/mem is used. The kernel should be configured
- * without CONFIG_STRICT_DEVMEM. In this case use:
- *         ./alignment_handler /dev/mem 0xc0000000
+ * alterative path for cache-inhibited memory may be provided, e.g. memtrace).
  *
  * We initialise the source buffers, then use whichever set of load/store
  * instructions is under test to copy bytes from the source buffers to the
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 3/3] powerpc/sstep: Always test lmw and stmw
  2021-02-25  3:21 [PATCH 1/3] powernv/memtrace: Allow mmaping trace buffers Jordan Niethe
  2021-02-25  3:21 ` [PATCH 2/3] selftests/powerpc: Suggest memtrace instead of /dev/mem for ci memory Jordan Niethe
@ 2021-02-25  3:21 ` Jordan Niethe
  2021-04-01 13:39   ` Michael Ellerman
  2021-04-10 14:28 ` [PATCH 1/3] powernv/memtrace: Allow mmaping trace buffers Michael Ellerman
  2 siblings, 1 reply; 6+ messages in thread
From: Jordan Niethe @ 2021-02-25  3:21 UTC (permalink / raw)
  To: linuxppc-dev; +Cc: Jordan Niethe

Load Multiple Word (lmw) and Store Multiple Word (stmw) will raise an
Alignment Exception:
  - Little Endian mode: always
  - Big Endian mode: address not word aligned

These conditions do not depend on cache inhibited memory. Test the
alignment handler emulation of these instructions regardless of if there
is cache inhibited memory available or not.

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
---
 .../powerpc/alignment/alignment_handler.c     | 96 ++++++++++++++++++-
 1 file changed, 94 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/powerpc/alignment/alignment_handler.c b/tools/testing/selftests/powerpc/alignment/alignment_handler.c
index f5eb5b85a2cf..c3003f95e043 100644
--- a/tools/testing/selftests/powerpc/alignment/alignment_handler.c
+++ b/tools/testing/selftests/powerpc/alignment/alignment_handler.c
@@ -45,6 +45,7 @@
 #include <getopt.h>
 #include <setjmp.h>
 #include <signal.h>
+#include <errno.h>
 
 #include "utils.h"
 #include "instructions.h"
@@ -434,7 +435,6 @@ int test_alignment_handler_integer(void)
 	LOAD_DFORM_TEST(ldu);
 	LOAD_XFORM_TEST(ldx);
 	LOAD_XFORM_TEST(ldux);
-	LOAD_DFORM_TEST(lmw);
 	STORE_DFORM_TEST(stb);
 	STORE_XFORM_TEST(stbx);
 	STORE_DFORM_TEST(stbu);
@@ -453,7 +453,6 @@ int test_alignment_handler_integer(void)
 	STORE_XFORM_TEST(stdx);
 	STORE_DFORM_TEST(stdu);
 	STORE_XFORM_TEST(stdux);
-	STORE_DFORM_TEST(stmw);
 
 	return rc;
 }
@@ -599,6 +598,97 @@ int test_alignment_handler_fp_prefix(void)
 	return rc;
 }
 
+int test_alignment_handler_multiple(void)
+{
+	int offset, width, r, rc = 0;
+	void *src1, *dst1, *src2, *dst2;
+
+	rc = posix_memalign(&src1, bufsize, bufsize);
+	if (rc) {
+		printf("\n");
+		return rc;
+	}
+
+	rc = posix_memalign(&dst1, bufsize, bufsize);
+	if (rc) {
+		printf("\n");
+		free(src1);
+		return rc;
+	}
+
+	src2 = malloc(bufsize);
+	if (!src2) {
+		printf("\n");
+		free(src1);
+		free(dst1);
+		return -ENOMEM;
+	}
+
+	dst2 = malloc(bufsize);
+	if (!dst2) {
+		printf("\n");
+		free(src1);
+		free(dst1);
+		free(src2);
+		return -ENOMEM;
+	}
+
+	/* lmw */
+	width = 4;
+	printf("\tDoing lmw:\t");
+	for (offset = 0; offset < width; offset++) {
+		preload_data(src1, offset, width);
+		preload_data(src2, offset, width);
+
+		asm volatile("lmw  31, 0(%0) ; std 31, 0(%1)"
+			     :: "r"(src1 + offset), "r"(dst1 + offset), "r"(0)
+			     : "memory", "r31");
+
+		memcpy(dst2 + offset, src1 + offset, width);
+
+		r = test_memcmp(dst1, dst2, width, offset, "test_lmw");
+		if (r && !debug) {
+			printf("FAILED: Wrong Data\n");
+			break;
+		}
+	}
+
+	if (!r)
+		printf("PASSED\n");
+	else
+		rc |= 1;
+
+	/* stmw */
+	width = 4;
+	printf("\tDoing stmw:\t");
+	for (offset = 0; offset < width; offset++) {
+		preload_data(src1, offset, width);
+		preload_data(src2, offset, width);
+
+		asm volatile("ld  31, 0(%0) ; stmw 31, 0(%1)"
+			     :: "r"(src1 + offset), "r"(dst1 + offset), "r"(0)
+			     : "memory", "r31");
+
+		memcpy(dst2 + offset, src1 + offset, width);
+
+		r = test_memcmp(dst1, dst2, width, offset, "test_stmw");
+		if (r && !debug) {
+			printf("FAILED: Wrong Data\n");
+			break;
+		}
+	}
+	if (!r)
+		printf("PASSED\n");
+	else
+		rc |= 1;
+
+	free(src1);
+	free(src2);
+	free(dst1);
+	free(dst2);
+	return rc;
+}
+
 void usage(char *prog)
 {
 	printf("Usage: %s [options] [path [offset]]\n", prog);
@@ -673,5 +763,7 @@ int main(int argc, char *argv[])
 			   "test_alignment_handler_fp_206");
 	rc |= test_harness(test_alignment_handler_fp_prefix,
 			   "test_alignment_handler_fp_prefix");
+	rc |= test_harness(test_alignment_handler_multiple,
+			   "test_alignment_handler_multiple");
 	return rc;
 }
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH 3/3] powerpc/sstep: Always test lmw and stmw
  2021-02-25  3:21 ` [PATCH 3/3] powerpc/sstep: Always test lmw and stmw Jordan Niethe
@ 2021-04-01 13:39   ` Michael Ellerman
  2021-04-06  2:04     ` Jordan Niethe
  0 siblings, 1 reply; 6+ messages in thread
From: Michael Ellerman @ 2021-04-01 13:39 UTC (permalink / raw)
  To: Jordan Niethe, linuxppc-dev; +Cc: Jordan Niethe

Hi Jordan,

Jordan Niethe <jniethe5@gmail.com> writes:
> Load Multiple Word (lmw) and Store Multiple Word (stmw) will raise an
> Alignment Exception:
>   - Little Endian mode: always
>   - Big Endian mode: address not word aligned
>
> These conditions do not depend on cache inhibited memory. Test the
> alignment handler emulation of these instructions regardless of if there
> is cache inhibited memory available or not.
>
> Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> ---
>  .../powerpc/alignment/alignment_handler.c     | 96 ++++++++++++++++++-
>  1 file changed, 94 insertions(+), 2 deletions(-)

Because of dd3a44c06f7b ("selftests/powerpc: Only test lwm/stmw on big endian")
this will need a respin sorry.

You'll need to add macros to generate lmw/stmw using .long, to avoid the
bug fixed in that commit.

cheers

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 3/3] powerpc/sstep: Always test lmw and stmw
  2021-04-01 13:39   ` Michael Ellerman
@ 2021-04-06  2:04     ` Jordan Niethe
  0 siblings, 0 replies; 6+ messages in thread
From: Jordan Niethe @ 2021-04-06  2:04 UTC (permalink / raw)
  To: Michael Ellerman; +Cc: linuxppc-dev

On Fri, Apr 2, 2021 at 12:39 AM Michael Ellerman <mpe@ellerman.id.au> wrote:
>
> Hi Jordan,
>
> Jordan Niethe <jniethe5@gmail.com> writes:
> > Load Multiple Word (lmw) and Store Multiple Word (stmw) will raise an
> > Alignment Exception:
> >   - Little Endian mode: always
> >   - Big Endian mode: address not word aligned
> >
> > These conditions do not depend on cache inhibited memory. Test the
> > alignment handler emulation of these instructions regardless of if there
> > is cache inhibited memory available or not.
> >
> > Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> > ---
> >  .../powerpc/alignment/alignment_handler.c     | 96 ++++++++++++++++++-
> >  1 file changed, 94 insertions(+), 2 deletions(-)
>
> Because of dd3a44c06f7b ("selftests/powerpc: Only test lwm/stmw on big endian")
> this will need a respin sorry.
>
> You'll need to add macros to generate lmw/stmw using .long, to avoid the
> bug fixed in that commit.
Thanks, I will resend.
>
> cheers

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/3] powernv/memtrace: Allow mmaping trace buffers
  2021-02-25  3:21 [PATCH 1/3] powernv/memtrace: Allow mmaping trace buffers Jordan Niethe
  2021-02-25  3:21 ` [PATCH 2/3] selftests/powerpc: Suggest memtrace instead of /dev/mem for ci memory Jordan Niethe
  2021-02-25  3:21 ` [PATCH 3/3] powerpc/sstep: Always test lmw and stmw Jordan Niethe
@ 2021-04-10 14:28 ` Michael Ellerman
  2 siblings, 0 replies; 6+ messages in thread
From: Michael Ellerman @ 2021-04-10 14:28 UTC (permalink / raw)
  To: Jordan Niethe, linuxppc-dev

On Thu, 25 Feb 2021 14:21:06 +1100, Jordan Niethe wrote:
> Let the memory removed from the linear mapping to be used for the trace
> buffers be mmaped. This is a useful way of providing cache-inhibited
> memory for the alignment_handler selftest.

Patches 1 & 2 applied to powerpc/next.

[1/3] powernv/memtrace: Allow mmaping trace buffers
      https://git.kernel.org/powerpc/c/08a022ad3dfafc7e33d4529015e14bb75179cacc
[2/3] selftests/powerpc: Suggest memtrace instead of /dev/mem for ci memory
      https://git.kernel.org/powerpc/c/812aa68ef7d4d71bed996468ead665092a3f8de9

cheers

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-04-10 14:31 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-25  3:21 [PATCH 1/3] powernv/memtrace: Allow mmaping trace buffers Jordan Niethe
2021-02-25  3:21 ` [PATCH 2/3] selftests/powerpc: Suggest memtrace instead of /dev/mem for ci memory Jordan Niethe
2021-02-25  3:21 ` [PATCH 3/3] powerpc/sstep: Always test lmw and stmw Jordan Niethe
2021-04-01 13:39   ` Michael Ellerman
2021-04-06  2:04     ` Jordan Niethe
2021-04-10 14:28 ` [PATCH 1/3] powernv/memtrace: Allow mmaping trace buffers Michael Ellerman

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