[PATCH 0/2] A64/R40 DRAM controller dual-rank-related changes

[Icenowy Zheng <icenowy@aosc.io>]

This patchset contains two patches.

The first one enables asymmetric dual rank DRAM on A64. This is needed
for 3GiB PinePhone, which has 2GiB rank 0 and 1GiB rank 1. This patch is
already used by the firmware flashed to PinePhone by factory.

The second one enables dual rank (and asymmetric dual rank, although not
tested because of lack of real board) on R40. In order to support single
rank and dual rank at the same time, a new rank detection code is
implemented (because PIR_QSGATE-based one does not work on R40). The
code enables some error report facility of the DRAM controller, and
then tries to access rank 1 and then check for error. It's placed at 2nd
patch because it depends on the function that calculates rank 0 size
(and rank 1 base address) introduced in PATCH 1.

Icenowy Zheng (2):
  sunxi: support asymmetric dual rank DRAM on A64/R40
  sunxi: enable dual rank memory on R40

 .../include/asm/arch-sunxi/dram_sunxi_dw.h    |  11 +-
 arch/arm/mach-sunxi/dram_sunxi_dw.c           | 149 +++++++++++++++---
 2 files changed, 131 insertions(+), 29 deletions(-)

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2.30.0