From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5116AC433DB for ; Mon, 1 Mar 2021 09:40:29 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id C8D54600EF for ; Mon, 1 Mar 2021 09:40:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C8D54600EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 295821CC4D4; Mon, 1 Mar 2021 10:40:15 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 519301CC3B1 for ; Mon, 1 Mar 2021 10:40:12 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from lizh@nvidia.com) with SMTP; 1 Mar 2021 11:40:07 +0200 Received: from nvidia.com (c-235-17-1-009.mtl.labs.mlnx [10.235.17.9]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 1219e4VP020473; Mon, 1 Mar 2021 11:40:07 +0200 From: Li Zhang To: dekelp@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com, matan@nvidia.com Cc: dev@dpdk.org, thomas@monjalon.net, rasland@nvidia.com, mb@smartsharesystems.com, ajit.khaparde@broadcom.com Date: Mon, 1 Mar 2021 11:39:58 +0200 Message-Id: <20210301094000.183002-3-lizh@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210301094000.183002-1-lizh@nvidia.com> References: <20210125012023.1769769-2-lizh@nvidia.com> <20210301094000.183002-1-lizh@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [RFC v3 2/4] common/mlx5: add meter mode definition in PRM file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add meter mode definition in PRM file Signed-off-by: Li Zhang --- drivers/common/mlx5/mlx5_prm.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index e3d4120849..609b1c3951 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2177,6 +2177,13 @@ struct mlx5_ifc_flow_meter_parameters_bits { #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 +enum { + MLX5_METER_MODE_IP_LEN = 0x0, + MLX5_METER_MODE_L2_LEN = 0x1, + MLX5_METER_MODE_L2_IPG_LEN = 0x2, + MLX5_METER_MODE_PKT = 0x3, +}; + enum { MLX5_CQE_SIZE_64B = 0x0, MLX5_CQE_SIZE_128B = 0x1, @@ -2508,6 +2515,7 @@ struct mlx5_aso_mtr_dseg { #define ASO_DSEG_VALID_OFFSET 31 #define ASO_DSEG_BO_OFFSET 30 #define ASO_DSEG_SC_OFFSET 28 +#define ASO_DSEG_MTR_MODE 24 #define ASO_DSEG_CBS_EXP_OFFSET 24 #define ASO_DSEG_CBS_MAN_OFFSET 16 #define ASO_DSEG_CIR_EXP_MASK 0x1F -- 2.21.0