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04 Mar 2021 06:30:46 -0800 IronPort-SDR: MnyFhpyLSpRZVQolKyVa9mPlv6WFyfYIi0HUh3p8z2Q9Ox7mMGuZzPucE3Un2/a74sZQCiU2bf no3PLJp/sRd75tFxZEzn6BT98rTu6Rw1vwXgzFkV+3Ttz1rFlZ0MfTJhAOxJ+MiLsAT+9IjEab JEjYL9vjVYxpDT1k2JowS9j2RUfub2MI34A5ZueShjj+DBiCbNmCKzxTWNNE6MFCFqwo1vF+dj ZkpGf3jOIdmBS4mkdni+lGHs3hFJVwazioCfKiHoyxx3WWKEvpk0AvwNvjXLQb3AWZWg9Rk5jZ CQU= WDCIronportException: Internal Received: from cnf008142.ad.shared (HELO alistair-risc6-laptop.hgst.com) ([10.86.48.109]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Mar 2021 06:47:46 -0800 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 00/19] riscv-to-apply queue Date: Thu, 4 Mar 2021 09:46:32 -0500 Message-Id: <20210304144651.310037-1-alistair.francis@wdc.com> X-Mailer: git-send-email 2.30.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=690dc056c=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit cb90ecf9349198558569f6c86c4c27d215406095: Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210304' into staging (2021-03-04 10:42:46 +0000) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210304 for you to fetch changes up to 19800265d407f09f333cf80dba3e975eb7bc1872: hw/riscv: virt: Map high mmio for PCIe (2021-03-04 09:43:29 -0500) ---------------------------------------------------------------- RISC-V PR for 6.0 This PR is a collection of RISC-V patches: - Improvements to SiFive U OTP - Upgrade OpenSBI to v0.9 - Support the QMP dump-guest-memory - Add support for the SiFive SPI controller (sifive_u) - Initial RISC-V system documentation - A fix for the Goldfish RTC - MAINTAINERS updates - Support for high PCIe memory in the virt machine ---------------------------------------------------------------- Alistair Francis (1): MAINTAINERS: Add a SiFive machine section Bin Meng (16): target/riscv: Declare csr_ops[] with a known size hw/misc: sifive_u_otp: Use error_report() when block operation fails roms/opensbi: Upgrade from v0.8 to v0.9 hw/block: m25p80: Add ISSI SPI flash support hw/block: m25p80: Add various ISSI flash information hw/ssi: Add SiFive SPI controller support hw/riscv: sifive_u: Add QSPI0 controller and connect a flash hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value docs/system: Sort targets in alphabetical order docs/system: Add RISC-V documentation docs/system: riscv: Add documentation for sifive_u machine hw/riscv: Drop 'struct MemmapEntry' hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() hw/riscv: virt: Limit RAM size in a 32-bit system hw/riscv: virt: Map high mmio for PCIe Laurent Vivier (1): goldfish_rtc: re-arm the alarm after migration Yifei Jiang (1): target-riscv: support QMP dump-guest-memory docs/system/riscv/sifive_u.rst | 336 +++++++++++++++++++++++ docs/system/target-riscv.rst | 72 +++++ docs/system/targets.rst | 20 +- include/hw/riscv/sifive_u.h | 9 +- include/hw/ssi/sifive_spi.h | 47 ++++ target/riscv/cpu.h | 6 +- target/riscv/cpu_bits.h | 1 + hw/block/m25p80.c | 57 +++- hw/misc/sifive_u_otp.c | 13 +- hw/riscv/microchip_pfsoc.c | 9 +- hw/riscv/opentitan.c | 9 +- hw/riscv/sifive_e.c | 9 +- hw/riscv/sifive_u.c | 102 ++++++- hw/riscv/spike.c | 9 +- hw/riscv/virt.c | 68 +++-- hw/rtc/goldfish_rtc.c | 2 + hw/ssi/sifive_spi.c | 358 +++++++++++++++++++++++++ target/riscv/arch_dump.c | 202 ++++++++++++++ target/riscv/cpu.c | 2 + MAINTAINERS | 9 + hw/riscv/Kconfig | 3 + hw/ssi/Kconfig | 4 + hw/ssi/meson.build | 1 + pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 62144 -> 78680 bytes pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 558668 -> 727464 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 70792 -> 75096 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 620424 -> 781264 bytes roms/opensbi | 2 +- target/riscv/meson.build | 1 + 29 files changed, 1286 insertions(+), 65 deletions(-) create mode 100644 docs/system/riscv/sifive_u.rst create mode 100644 docs/system/target-riscv.rst create mode 100644 include/hw/ssi/sifive_spi.h create mode 100644 hw/ssi/sifive_spi.c create mode 100644 target/riscv/arch_dump.c