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* [RFC PATCH v2 0/8] cpu: Move CPUClass::has_work() to TCGCPUOps
@ 2021-03-04 22:23 ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Philippe Mathieu-Daudé,
	Cornelia Huck, Richard Henderson, Laurent Vivier, Greg Kurz,
	qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
	David Gibson

Hi,

cpu_has_work() isn't used out of TCG, so restrict it to it.
RFC because maybe it could?

Since v1:
- finished PPC
- check cc->tcg_ops->has_work non-null (thuth)

Based-on: <20210227232519.222663-1-richard.henderson@linaro.org>

Philippe Mathieu-Daudé (8):
  sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
  sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG
  target/arm: Directly use arm_cpu_has_work instead of
    CPUClass::has_work
  target/s390x: Move s390_cpu_has_work to excp_helper.c
  target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs
  cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
  cpu: Move CPUClass::has_work() to TCGCPUOps
  target/arm: Restrict arm_cpu_has_work() to TCG

 include/hw/core/cpu.h           | 27 -----------
 include/hw/core/tcg-cpu-ops.h   |  4 ++
 include/sysemu/tcg.h            | 30 +++++++++++--
 target/arm/internals.h          |  1 +
 target/s390x/internal.h         |  1 +
 accel/tcg/cpu-exec.c            | 12 +++++
 hw/core/cpu.c                   |  6 ---
 softmmu/cpus.c                  |  1 +
 target/alpha/cpu.c              |  2 +-
 target/arm/cpu.c                |  6 +--
 target/arm/op_helper.c          |  2 +-
 target/avr/cpu.c                |  2 +-
 target/cris/cpu.c               |  3 +-
 target/hexagon/cpu.c            |  2 +-
 target/hppa/cpu.c               |  2 +-
 target/i386/cpu.c               |  7 +--
 target/i386/tcg/tcg-cpu.c       |  6 +++
 target/lm32/cpu.c               |  2 +-
 target/m68k/cpu.c               |  2 +-
 target/microblaze/cpu.c         |  2 +-
 target/mips/cpu.c               |  2 +-
 target/moxie/cpu.c              |  2 +-
 target/nios2/cpu.c              |  2 +-
 target/openrisc/cpu.c           |  2 +-
 target/riscv/cpu.c              |  2 +-
 target/rx/cpu.c                 |  2 +-
 target/s390x/cpu.c              | 19 +-------
 target/s390x/excp_helper.c      | 18 ++++++++
 target/sh4/cpu.c                |  2 +-
 target/sparc/cpu.c              |  2 +-
 target/tilegx/cpu.c             |  2 +-
 target/tricore/cpu.c            |  2 +-
 target/unicore32/cpu.c          |  2 +-
 target/xtensa/cpu.c             |  2 +-
 tcg/tcg.c                       |  1 +
 target/ppc/translate_init.c.inc | 79 ++++++++++++++++++++++++++++++---
 36 files changed, 171 insertions(+), 90 deletions(-)

-- 
2.26.2



^ permalink raw reply	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 0/8] cpu: Move CPUClass::has_work() to TCGCPUOps
@ 2021-03-04 22:23 ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Claudio Fontana,
	Philippe Mathieu-Daudé

Hi,

cpu_has_work() isn't used out of TCG, so restrict it to it.
RFC because maybe it could?

Since v1:
- finished PPC
- check cc->tcg_ops->has_work non-null (thuth)

Based-on: <20210227232519.222663-1-richard.henderson@linaro.org>

Philippe Mathieu-Daudé (8):
  sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
  sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG
  target/arm: Directly use arm_cpu_has_work instead of
    CPUClass::has_work
  target/s390x: Move s390_cpu_has_work to excp_helper.c
  target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs
  cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
  cpu: Move CPUClass::has_work() to TCGCPUOps
  target/arm: Restrict arm_cpu_has_work() to TCG

 include/hw/core/cpu.h           | 27 -----------
 include/hw/core/tcg-cpu-ops.h   |  4 ++
 include/sysemu/tcg.h            | 30 +++++++++++--
 target/arm/internals.h          |  1 +
 target/s390x/internal.h         |  1 +
 accel/tcg/cpu-exec.c            | 12 +++++
 hw/core/cpu.c                   |  6 ---
 softmmu/cpus.c                  |  1 +
 target/alpha/cpu.c              |  2 +-
 target/arm/cpu.c                |  6 +--
 target/arm/op_helper.c          |  2 +-
 target/avr/cpu.c                |  2 +-
 target/cris/cpu.c               |  3 +-
 target/hexagon/cpu.c            |  2 +-
 target/hppa/cpu.c               |  2 +-
 target/i386/cpu.c               |  7 +--
 target/i386/tcg/tcg-cpu.c       |  6 +++
 target/lm32/cpu.c               |  2 +-
 target/m68k/cpu.c               |  2 +-
 target/microblaze/cpu.c         |  2 +-
 target/mips/cpu.c               |  2 +-
 target/moxie/cpu.c              |  2 +-
 target/nios2/cpu.c              |  2 +-
 target/openrisc/cpu.c           |  2 +-
 target/riscv/cpu.c              |  2 +-
 target/rx/cpu.c                 |  2 +-
 target/s390x/cpu.c              | 19 +-------
 target/s390x/excp_helper.c      | 18 ++++++++
 target/sh4/cpu.c                |  2 +-
 target/sparc/cpu.c              |  2 +-
 target/tilegx/cpu.c             |  2 +-
 target/tricore/cpu.c            |  2 +-
 target/unicore32/cpu.c          |  2 +-
 target/xtensa/cpu.c             |  2 +-
 tcg/tcg.c                       |  1 +
 target/ppc/translate_init.c.inc | 79 ++++++++++++++++++++++++++++++---
 36 files changed, 171 insertions(+), 90 deletions(-)

-- 
2.26.2



^ permalink raw reply	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
  2021-03-04 22:23 ` Philippe Mathieu-Daudé
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Philippe Mathieu-Daudé,
	Cornelia Huck, Richard Henderson, Laurent Vivier, Greg Kurz,
	qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
	David Gibson

Invert the #ifdef'ry to easily restrict tcg_exec_init() declaration
to CONFIG_TCG.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/sysemu/tcg.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
index 00349fb18a7..fddde2b6b9a 100644
--- a/include/sysemu/tcg.h
+++ b/include/sysemu/tcg.h
@@ -8,13 +8,15 @@
 #ifndef SYSEMU_TCG_H
 #define SYSEMU_TCG_H
 
+#ifndef CONFIG_TCG
+#define tcg_enabled() 0
+#else
+
 void tcg_exec_init(unsigned long tb_size, int splitwx);
 
-#ifdef CONFIG_TCG
 extern bool tcg_allowed;
 #define tcg_enabled() (tcg_allowed)
-#else
-#define tcg_enabled() 0
-#endif
+
+#endif /* CONFIG_TCG */
 
 #endif
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Claudio Fontana,
	Philippe Mathieu-Daudé

Invert the #ifdef'ry to easily restrict tcg_exec_init() declaration
to CONFIG_TCG.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/sysemu/tcg.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
index 00349fb18a7..fddde2b6b9a 100644
--- a/include/sysemu/tcg.h
+++ b/include/sysemu/tcg.h
@@ -8,13 +8,15 @@
 #ifndef SYSEMU_TCG_H
 #define SYSEMU_TCG_H
 
+#ifndef CONFIG_TCG
+#define tcg_enabled() 0
+#else
+
 void tcg_exec_init(unsigned long tb_size, int splitwx);
 
-#ifdef CONFIG_TCG
 extern bool tcg_allowed;
 #define tcg_enabled() (tcg_allowed)
-#else
-#define tcg_enabled() 0
-#endif
+
+#endif /* CONFIG_TCG */
 
 #endif
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 2/8] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG
  2021-03-04 22:23 ` Philippe Mathieu-Daudé
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Philippe Mathieu-Daudé,
	Cornelia Huck, Richard Henderson, Laurent Vivier, Greg Kurz,
	qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
	David Gibson

qemu_tcg_mttcg_enabled() shouldn't not be used outside of TCG,
restrict its declaration.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/core/cpu.h | 9 ---------
 include/sysemu/tcg.h  | 9 +++++++++
 accel/tcg/cpu-exec.c  | 1 +
 tcg/tcg.c             | 1 +
 4 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e3648338dfe..1376e496a3f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -454,15 +454,6 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
     }
 }
 
-/**
- * qemu_tcg_mttcg_enabled:
- * Check whether we are running MultiThread TCG or not.
- *
- * Returns: %true if we are in MTTCG mode %false otherwise.
- */
-extern bool mttcg_enabled;
-#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
-
 /**
  * cpu_paging_enabled:
  * @cpu: The CPU whose state is to be inspected.
diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
index fddde2b6b9a..c16c13c3c69 100644
--- a/include/sysemu/tcg.h
+++ b/include/sysemu/tcg.h
@@ -17,6 +17,15 @@ void tcg_exec_init(unsigned long tb_size, int splitwx);
 extern bool tcg_allowed;
 #define tcg_enabled() (tcg_allowed)
 
+/**
+ * qemu_tcg_mttcg_enabled:
+ * Check whether we are running MultiThread TCG or not.
+ *
+ * Returns: %true if we are in MTTCG mode %false otherwise.
+ */
+extern bool mttcg_enabled;
+#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
+
 #endif /* CONFIG_TCG */
 
 #endif
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 16e4fe3ccd8..7e67ade35b9 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -39,6 +39,7 @@
 #include "hw/i386/apic.h"
 #endif
 #include "sysemu/cpus.h"
+#include "sysemu/tcg.h"
 #include "exec/cpu-all.h"
 #include "sysemu/cpu-timers.h"
 #include "sysemu/replay.h"
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 63a12b197bf..4a4dac0bb3e 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -65,6 +65,7 @@
 #include "elf.h"
 #include "exec/log.h"
 #include "sysemu/sysemu.h"
+#include "sysemu/tcg.h"
 
 /* Forward declarations for functions declared in tcg-target.c.inc and
    used here. */
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 2/8] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Claudio Fontana,
	Philippe Mathieu-Daudé,
	Marcel Apfelbaum

qemu_tcg_mttcg_enabled() shouldn't not be used outside of TCG,
restrict its declaration.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/core/cpu.h | 9 ---------
 include/sysemu/tcg.h  | 9 +++++++++
 accel/tcg/cpu-exec.c  | 1 +
 tcg/tcg.c             | 1 +
 4 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e3648338dfe..1376e496a3f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -454,15 +454,6 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
     }
 }
 
-/**
- * qemu_tcg_mttcg_enabled:
- * Check whether we are running MultiThread TCG or not.
- *
- * Returns: %true if we are in MTTCG mode %false otherwise.
- */
-extern bool mttcg_enabled;
-#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
-
 /**
  * cpu_paging_enabled:
  * @cpu: The CPU whose state is to be inspected.
diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
index fddde2b6b9a..c16c13c3c69 100644
--- a/include/sysemu/tcg.h
+++ b/include/sysemu/tcg.h
@@ -17,6 +17,15 @@ void tcg_exec_init(unsigned long tb_size, int splitwx);
 extern bool tcg_allowed;
 #define tcg_enabled() (tcg_allowed)
 
+/**
+ * qemu_tcg_mttcg_enabled:
+ * Check whether we are running MultiThread TCG or not.
+ *
+ * Returns: %true if we are in MTTCG mode %false otherwise.
+ */
+extern bool mttcg_enabled;
+#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
+
 #endif /* CONFIG_TCG */
 
 #endif
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 16e4fe3ccd8..7e67ade35b9 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -39,6 +39,7 @@
 #include "hw/i386/apic.h"
 #endif
 #include "sysemu/cpus.h"
+#include "sysemu/tcg.h"
 #include "exec/cpu-all.h"
 #include "sysemu/cpu-timers.h"
 #include "sysemu/replay.h"
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 63a12b197bf..4a4dac0bb3e 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -65,6 +65,7 @@
 #include "elf.h"
 #include "exec/log.h"
 #include "sysemu/sysemu.h"
+#include "sysemu/tcg.h"
 
 /* Forward declarations for functions declared in tcg-target.c.inc and
    used here. */
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 3/8] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work
  2021-03-04 22:23 ` Philippe Mathieu-Daudé
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Philippe Mathieu-Daudé,
	Cornelia Huck, Richard Henderson, Laurent Vivier, Greg Kurz,
	qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
	David Gibson

There is only one CPUClass::has_work() ARM handler: arm_cpu_has_work().

Avoid a dereference by declaring it in "internals.h" and call it
directly  in the WFI helper.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/internals.h | 1 +
 target/arm/cpu.c       | 2 +-
 target/arm/op_helper.c | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 05cebc8597c..1930be08828 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -172,6 +172,7 @@ static inline int r14_bank_number(int mode)
 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 void arm_translate_init(void);
 
+bool arm_cpu_has_work(CPUState *cs);
 #ifdef CONFIG_TCG
 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
 #endif /* CONFIG_TCG */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5e018b2a732..6d2d9f2100f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -76,7 +76,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
 }
 #endif /* CONFIG_TCG */
 
-static bool arm_cpu_has_work(CPUState *cs)
+bool arm_cpu_has_work(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
 
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 65cb37d088f..a4da6f4fde8 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -289,7 +289,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
     CPUState *cs = env_cpu(env);
     int target_el = check_wfx_trap(env, false);
 
-    if (cpu_has_work(cs)) {
+    if (arm_cpu_has_work(cs)) {
         /* Don't bother to go into our "low power state" if
          * we would just wake up immediately.
          */
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 3/8] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Claudio Fontana,
	Philippe Mathieu-Daudé

There is only one CPUClass::has_work() ARM handler: arm_cpu_has_work().

Avoid a dereference by declaring it in "internals.h" and call it
directly  in the WFI helper.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/internals.h | 1 +
 target/arm/cpu.c       | 2 +-
 target/arm/op_helper.c | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 05cebc8597c..1930be08828 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -172,6 +172,7 @@ static inline int r14_bank_number(int mode)
 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 void arm_translate_init(void);
 
+bool arm_cpu_has_work(CPUState *cs);
 #ifdef CONFIG_TCG
 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
 #endif /* CONFIG_TCG */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5e018b2a732..6d2d9f2100f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -76,7 +76,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
 }
 #endif /* CONFIG_TCG */
 
-static bool arm_cpu_has_work(CPUState *cs)
+bool arm_cpu_has_work(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
 
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 65cb37d088f..a4da6f4fde8 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -289,7 +289,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
     CPUState *cs = env_cpu(env);
     int target_el = check_wfx_trap(env, false);
 
-    if (cpu_has_work(cs)) {
+    if (arm_cpu_has_work(cs)) {
         /* Don't bother to go into our "low power state" if
          * we would just wake up immediately.
          */
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 4/8] target/s390x: Move s390_cpu_has_work to excp_helper.c
  2021-03-04 22:23 ` Philippe Mathieu-Daudé
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Philippe Mathieu-Daudé,
	Cornelia Huck, Richard Henderson, Laurent Vivier, Greg Kurz,
	qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
	David Gibson

We will restrict the s390_cpu_has_work() function to TCG.
First declare it in "internal.h" and move it to excp_helper.c.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/s390x/internal.h    |  1 +
 target/s390x/cpu.c         | 17 -----------------
 target/s390x/excp_helper.c | 18 ++++++++++++++++++
 3 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index 11515bb6173..7184e38631c 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -263,6 +263,7 @@ ObjectClass *s390_cpu_class_by_name(const char *name);
 
 
 /* excp_helper.c */
+bool s390_cpu_has_work(CPUState *cs);
 void s390x_cpu_debug_excp_handler(CPUState *cs);
 void s390_cpu_do_interrupt(CPUState *cpu);
 bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index feaf2a6d08f..d57f69e7f7d 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -56,23 +56,6 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.psw.addr = value;
 }
 
-static bool s390_cpu_has_work(CPUState *cs)
-{
-    S390CPU *cpu = S390_CPU(cs);
-
-    /* STOPPED cpus can never wake up */
-    if (s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD &&
-        s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING) {
-        return false;
-    }
-
-    if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
-        return false;
-    }
-
-    return s390_cpu_has_int(cpu);
-}
-
 #if !defined(CONFIG_USER_ONLY)
 /* S390CPUClass::load_normal() */
 static void s390_cpu_load_normal(CPUState *s)
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index ce16af394b1..64923ffb83a 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -28,12 +28,30 @@
 #include "hw/s390x/ioinst.h"
 #include "exec/address-spaces.h"
 #include "tcg_s390x.h"
+#include "qapi/qapi-types-machine.h"
 #ifndef CONFIG_USER_ONLY
 #include "sysemu/sysemu.h"
 #include "hw/s390x/s390_flic.h"
 #include "hw/boards.h"
 #endif
 
+bool s390_cpu_has_work(CPUState *cs)
+{
+    S390CPU *cpu = S390_CPU(cs);
+
+    /* STOPPED cpus can never wake up */
+    if (s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD &&
+        s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING) {
+        return false;
+    }
+
+    if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
+        return false;
+    }
+
+    return s390_cpu_has_int(cpu);
+}
+
 void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env,
                                               uint32_t code, uintptr_t ra)
 {
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 4/8] target/s390x: Move s390_cpu_has_work to excp_helper.c
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Claudio Fontana,
	Philippe Mathieu-Daudé

We will restrict the s390_cpu_has_work() function to TCG.
First declare it in "internal.h" and move it to excp_helper.c.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/s390x/internal.h    |  1 +
 target/s390x/cpu.c         | 17 -----------------
 target/s390x/excp_helper.c | 18 ++++++++++++++++++
 3 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index 11515bb6173..7184e38631c 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -263,6 +263,7 @@ ObjectClass *s390_cpu_class_by_name(const char *name);
 
 
 /* excp_helper.c */
+bool s390_cpu_has_work(CPUState *cs);
 void s390x_cpu_debug_excp_handler(CPUState *cs);
 void s390_cpu_do_interrupt(CPUState *cpu);
 bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index feaf2a6d08f..d57f69e7f7d 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -56,23 +56,6 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.psw.addr = value;
 }
 
-static bool s390_cpu_has_work(CPUState *cs)
-{
-    S390CPU *cpu = S390_CPU(cs);
-
-    /* STOPPED cpus can never wake up */
-    if (s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD &&
-        s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING) {
-        return false;
-    }
-
-    if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
-        return false;
-    }
-
-    return s390_cpu_has_int(cpu);
-}
-
 #if !defined(CONFIG_USER_ONLY)
 /* S390CPUClass::load_normal() */
 static void s390_cpu_load_normal(CPUState *s)
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index ce16af394b1..64923ffb83a 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -28,12 +28,30 @@
 #include "hw/s390x/ioinst.h"
 #include "exec/address-spaces.h"
 #include "tcg_s390x.h"
+#include "qapi/qapi-types-machine.h"
 #ifndef CONFIG_USER_ONLY
 #include "sysemu/sysemu.h"
 #include "hw/s390x/s390_flic.h"
 #include "hw/boards.h"
 #endif
 
+bool s390_cpu_has_work(CPUState *cs)
+{
+    S390CPU *cpu = S390_CPU(cs);
+
+    /* STOPPED cpus can never wake up */
+    if (s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD &&
+        s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING) {
+        return false;
+    }
+
+    if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
+        return false;
+    }
+
+    return s390_cpu_has_int(cpu);
+}
+
 void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env,
                                               uint32_t code, uintptr_t ra)
 {
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs
  2021-03-04 22:23 ` Philippe Mathieu-Daudé
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Philippe Mathieu-Daudé,
	Cornelia Huck, Richard Henderson, Laurent Vivier, Greg Kurz,
	qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
	David Gibson

POWER CPUs have specific CPUClass::has_work() handlers.
In preparation of moving this field to TCGCPUOps, we need
to duplicate the current ppc_tcg_ops structure for the
POWER cpus.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/ppc/translate_init.c.inc | 69 +++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 80239077e0b..fe76d0b3773 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -48,6 +48,11 @@
 /* #define PPC_DUMP_SPR_ACCESSES */
 /* #define USE_APPLE_GDB */
 
+static const struct TCGCPUOps power7_tcg_ops;
+static const struct TCGCPUOps power8_tcg_ops;
+static const struct TCGCPUOps power9_tcg_ops;
+static const struct TCGCPUOps power10_tcg_ops;
+
 /*
  * Generic callbacks:
  * do nothing but store/retrieve spr value
@@ -8685,6 +8690,9 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
     pcc->l1_dcache_size = 0x8000;
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+    cc->tcg_ops = &power7_tcg_ops;
+#endif /* CONFIG_TCG */
 }
 
 static void init_proc_POWER8(CPUPPCState *env)
@@ -8863,6 +8871,9 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
     pcc->l1_dcache_size = 0x8000;
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+    cc->tcg_ops = &power8_tcg_ops;
+#endif /* CONFIG_TCG */
 }
 
 #ifdef CONFIG_SOFTMMU
@@ -9081,6 +9092,9 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
     pcc->l1_dcache_size = 0x8000;
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+    cc->tcg_ops = &power9_tcg_ops;
+#endif /* CONFIG_TCG */
 }
 
 #ifdef CONFIG_SOFTMMU
@@ -9292,6 +9306,9 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
     pcc->l1_dcache_size = 0x8000;
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+    cc->tcg_ops = &power10_tcg_ops;
+#endif /* CONFIG_TCG */
 }
 
 #if !defined(CONFIG_USER_ONLY)
@@ -10851,6 +10868,58 @@ static const struct TCGCPUOps ppc_tcg_ops = {
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
+#ifndef CONFIG_USER_ONLY
+  .do_interrupt = ppc_cpu_do_interrupt,
+  .cpu_exec_enter = ppc_cpu_exec_enter,
+  .cpu_exec_exit = ppc_cpu_exec_exit,
+  .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power7_tcg_ops = {
+  .initialize = ppc_translate_init,
+  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+  .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+  .do_interrupt = ppc_cpu_do_interrupt,
+  .cpu_exec_enter = ppc_cpu_exec_enter,
+  .cpu_exec_exit = ppc_cpu_exec_exit,
+  .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power8_tcg_ops = {
+  .initialize = ppc_translate_init,
+  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+  .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+  .do_interrupt = ppc_cpu_do_interrupt,
+  .cpu_exec_enter = ppc_cpu_exec_enter,
+  .cpu_exec_exit = ppc_cpu_exec_exit,
+  .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power9_tcg_ops = {
+  .initialize = ppc_translate_init,
+  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+  .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+  .do_interrupt = ppc_cpu_do_interrupt,
+  .cpu_exec_enter = ppc_cpu_exec_enter,
+  .cpu_exec_exit = ppc_cpu_exec_exit,
+  .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power10_tcg_ops = {
+  .initialize = ppc_translate_init,
+  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+  .tlb_fill = ppc_cpu_tlb_fill,
+
 #ifndef CONFIG_USER_ONLY
   .do_interrupt = ppc_cpu_do_interrupt,
   .cpu_exec_enter = ppc_cpu_exec_enter,
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Claudio Fontana,
	Philippe Mathieu-Daudé

POWER CPUs have specific CPUClass::has_work() handlers.
In preparation of moving this field to TCGCPUOps, we need
to duplicate the current ppc_tcg_ops structure for the
POWER cpus.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/ppc/translate_init.c.inc | 69 +++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 80239077e0b..fe76d0b3773 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -48,6 +48,11 @@
 /* #define PPC_DUMP_SPR_ACCESSES */
 /* #define USE_APPLE_GDB */
 
+static const struct TCGCPUOps power7_tcg_ops;
+static const struct TCGCPUOps power8_tcg_ops;
+static const struct TCGCPUOps power9_tcg_ops;
+static const struct TCGCPUOps power10_tcg_ops;
+
 /*
  * Generic callbacks:
  * do nothing but store/retrieve spr value
@@ -8685,6 +8690,9 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
     pcc->l1_dcache_size = 0x8000;
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+    cc->tcg_ops = &power7_tcg_ops;
+#endif /* CONFIG_TCG */
 }
 
 static void init_proc_POWER8(CPUPPCState *env)
@@ -8863,6 +8871,9 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
     pcc->l1_dcache_size = 0x8000;
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+    cc->tcg_ops = &power8_tcg_ops;
+#endif /* CONFIG_TCG */
 }
 
 #ifdef CONFIG_SOFTMMU
@@ -9081,6 +9092,9 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
     pcc->l1_dcache_size = 0x8000;
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+    cc->tcg_ops = &power9_tcg_ops;
+#endif /* CONFIG_TCG */
 }
 
 #ifdef CONFIG_SOFTMMU
@@ -9292,6 +9306,9 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
     pcc->l1_dcache_size = 0x8000;
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+    cc->tcg_ops = &power10_tcg_ops;
+#endif /* CONFIG_TCG */
 }
 
 #if !defined(CONFIG_USER_ONLY)
@@ -10851,6 +10868,58 @@ static const struct TCGCPUOps ppc_tcg_ops = {
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
+#ifndef CONFIG_USER_ONLY
+  .do_interrupt = ppc_cpu_do_interrupt,
+  .cpu_exec_enter = ppc_cpu_exec_enter,
+  .cpu_exec_exit = ppc_cpu_exec_exit,
+  .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power7_tcg_ops = {
+  .initialize = ppc_translate_init,
+  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+  .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+  .do_interrupt = ppc_cpu_do_interrupt,
+  .cpu_exec_enter = ppc_cpu_exec_enter,
+  .cpu_exec_exit = ppc_cpu_exec_exit,
+  .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power8_tcg_ops = {
+  .initialize = ppc_translate_init,
+  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+  .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+  .do_interrupt = ppc_cpu_do_interrupt,
+  .cpu_exec_enter = ppc_cpu_exec_enter,
+  .cpu_exec_exit = ppc_cpu_exec_exit,
+  .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power9_tcg_ops = {
+  .initialize = ppc_translate_init,
+  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+  .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+  .do_interrupt = ppc_cpu_do_interrupt,
+  .cpu_exec_enter = ppc_cpu_exec_enter,
+  .cpu_exec_exit = ppc_cpu_exec_exit,
+  .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power10_tcg_ops = {
+  .initialize = ppc_translate_init,
+  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+  .tlb_fill = ppc_cpu_tlb_fill,
+
 #ifndef CONFIG_USER_ONLY
   .do_interrupt = ppc_cpu_do_interrupt,
   .cpu_exec_enter = ppc_cpu_exec_enter,
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
  2021-03-04 22:23 ` Philippe Mathieu-Daudé
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Philippe Mathieu-Daudé,
	Cornelia Huck, Richard Henderson, Laurent Vivier, Greg Kurz,
	qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
	David Gibson

We can only check if a vCPU has work with TCG.
Move the cpu_has_work() prototype to "sysemu/tcg.h".

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
RFC: could another accelerator do that?
     can we rename this tcg_vcpu_has_work()?
---
 include/hw/core/cpu.h | 16 ----------------
 include/sysemu/tcg.h  | 11 +++++++++++
 accel/tcg/cpu-exec.c  |  7 +++++++
 softmmu/cpus.c        |  1 +
 4 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 1376e496a3f..66109bcca35 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename);
  */
 const char *parse_cpu_option(const char *cpu_option);
 
-/**
- * cpu_has_work:
- * @cpu: The vCPU to check.
- *
- * Checks whether the CPU has work to do.
- *
- * Returns: %true if the CPU has work, %false otherwise.
- */
-static inline bool cpu_has_work(CPUState *cpu)
-{
-    CPUClass *cc = CPU_GET_CLASS(cpu);
-
-    g_assert(cc->has_work);
-    return cc->has_work(cpu);
-}
-
 /**
  * qemu_cpu_is_self:
  * @cpu: The vCPU to check against.
diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
index c16c13c3c69..3d46b0a7a93 100644
--- a/include/sysemu/tcg.h
+++ b/include/sysemu/tcg.h
@@ -10,6 +10,7 @@
 
 #ifndef CONFIG_TCG
 #define tcg_enabled() 0
+#define cpu_has_work(cpu) false
 #else
 
 void tcg_exec_init(unsigned long tb_size, int splitwx);
@@ -26,6 +27,16 @@ extern bool tcg_allowed;
 extern bool mttcg_enabled;
 #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
 
+/**
+ * cpu_has_work:
+ * @cpu: The vCPU to check.
+ *
+ * Checks whether the CPU has work to do.
+ *
+ * Returns: %true if the CPU has work, %false otherwise.
+ */
+bool cpu_has_work(CPUState *cpu);
+
 #endif /* CONFIG_TCG */
 
 #endif
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 7e67ade35b9..b9ce36e59e2 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
     return tb;
 }
 
+bool cpu_has_work(CPUState *cpu)
+{
+    CPUClass *cc = CPU_GET_CLASS(cpu);
+
+    return cc->has_work(cpu);
+}
+
 static inline bool cpu_handle_halt(CPUState *cpu)
 {
     if (cpu->halted) {
diff --git a/softmmu/cpus.c b/softmmu/cpus.c
index a7ee431187a..548ab9236f1 100644
--- a/softmmu/cpus.c
+++ b/softmmu/cpus.c
@@ -42,6 +42,7 @@
 #include "sysemu/runstate.h"
 #include "sysemu/cpu-timers.h"
 #include "sysemu/whpx.h"
+#include "sysemu/tcg.h"
 #include "hw/boards.h"
 #include "hw/hw.h"
 
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Claudio Fontana,
	Philippe Mathieu-Daudé,
	Marcel Apfelbaum

We can only check if a vCPU has work with TCG.
Move the cpu_has_work() prototype to "sysemu/tcg.h".

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
RFC: could another accelerator do that?
     can we rename this tcg_vcpu_has_work()?
---
 include/hw/core/cpu.h | 16 ----------------
 include/sysemu/tcg.h  | 11 +++++++++++
 accel/tcg/cpu-exec.c  |  7 +++++++
 softmmu/cpus.c        |  1 +
 4 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 1376e496a3f..66109bcca35 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename);
  */
 const char *parse_cpu_option(const char *cpu_option);
 
-/**
- * cpu_has_work:
- * @cpu: The vCPU to check.
- *
- * Checks whether the CPU has work to do.
- *
- * Returns: %true if the CPU has work, %false otherwise.
- */
-static inline bool cpu_has_work(CPUState *cpu)
-{
-    CPUClass *cc = CPU_GET_CLASS(cpu);
-
-    g_assert(cc->has_work);
-    return cc->has_work(cpu);
-}
-
 /**
  * qemu_cpu_is_self:
  * @cpu: The vCPU to check against.
diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
index c16c13c3c69..3d46b0a7a93 100644
--- a/include/sysemu/tcg.h
+++ b/include/sysemu/tcg.h
@@ -10,6 +10,7 @@
 
 #ifndef CONFIG_TCG
 #define tcg_enabled() 0
+#define cpu_has_work(cpu) false
 #else
 
 void tcg_exec_init(unsigned long tb_size, int splitwx);
@@ -26,6 +27,16 @@ extern bool tcg_allowed;
 extern bool mttcg_enabled;
 #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
 
+/**
+ * cpu_has_work:
+ * @cpu: The vCPU to check.
+ *
+ * Checks whether the CPU has work to do.
+ *
+ * Returns: %true if the CPU has work, %false otherwise.
+ */
+bool cpu_has_work(CPUState *cpu);
+
 #endif /* CONFIG_TCG */
 
 #endif
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 7e67ade35b9..b9ce36e59e2 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
     return tb;
 }
 
+bool cpu_has_work(CPUState *cpu)
+{
+    CPUClass *cc = CPU_GET_CLASS(cpu);
+
+    return cc->has_work(cpu);
+}
+
 static inline bool cpu_handle_halt(CPUState *cpu)
 {
     if (cpu->halted) {
diff --git a/softmmu/cpus.c b/softmmu/cpus.c
index a7ee431187a..548ab9236f1 100644
--- a/softmmu/cpus.c
+++ b/softmmu/cpus.c
@@ -42,6 +42,7 @@
 #include "sysemu/runstate.h"
 #include "sysemu/cpu-timers.h"
 #include "sysemu/whpx.h"
+#include "sysemu/tcg.h"
 #include "hw/boards.h"
 #include "hw/hw.h"
 
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 7/8] cpu: Move CPUClass::has_work() to TCGCPUOps
  2021-03-04 22:23 ` Philippe Mathieu-Daudé
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
	David Hildenbrand, Anthony Green, Mark Cave-Ayland,
	Aleksandar Rikalo, Laurent Vivier, Max Filippov, Taylor Simpson,
	Alistair Francis, Edgar E. Iglesias, Guan Xuetao, Marek Vasut,
	Yoshinori Sato, Claudio Fontana, Palmer Dabbelt,
	Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
	Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
	Michael Rolnik, Stafford Horne, David Gibson, qemu-riscv,
	Bastian Koppelmann, Cornelia Huck, Philippe Mathieu-Daudé,
	Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno

We can only check if a vCPU has work with TCG.
Restrict the has_work() handler to TCG by moving it to
the TCGCPUOps structure, and adapt all the targets.

cpu_common_has_work() is removed as being inlined in
cpu_has_work().

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- finished PPC
- check cc->tcg_ops->has_work non-null (thuth)
---
 include/hw/core/cpu.h           |  2 --
 include/hw/core/tcg-cpu-ops.h   |  4 ++++
 accel/tcg/cpu-exec.c            |  6 +++++-
 hw/core/cpu.c                   |  6 ------
 target/alpha/cpu.c              |  2 +-
 target/arm/cpu.c                |  2 +-
 target/avr/cpu.c                |  2 +-
 target/cris/cpu.c               |  3 ++-
 target/hexagon/cpu.c            |  2 +-
 target/hppa/cpu.c               |  2 +-
 target/i386/cpu.c               |  7 +------
 target/i386/tcg/tcg-cpu.c       |  6 ++++++
 target/lm32/cpu.c               |  2 +-
 target/m68k/cpu.c               |  2 +-
 target/microblaze/cpu.c         |  2 +-
 target/mips/cpu.c               |  2 +-
 target/moxie/cpu.c              |  2 +-
 target/nios2/cpu.c              |  2 +-
 target/openrisc/cpu.c           |  2 +-
 target/riscv/cpu.c              |  2 +-
 target/rx/cpu.c                 |  2 +-
 target/s390x/cpu.c              |  2 +-
 target/sh4/cpu.c                |  2 +-
 target/sparc/cpu.c              |  2 +-
 target/tilegx/cpu.c             |  2 +-
 target/tricore/cpu.c            |  2 +-
 target/unicore32/cpu.c          |  2 +-
 target/xtensa/cpu.c             |  2 +-
 target/ppc/translate_init.c.inc | 10 +++++-----
 29 files changed, 44 insertions(+), 42 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 66109bcca35..8efea289e7e 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -86,7 +86,6 @@ struct AccelCPUClass;
  * instantiatable CPU type.
  * @parse_features: Callback to parse command line arguments.
  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
- * @has_work: Callback for checking if there is work to do.
  * @virtio_is_big_endian: Callback to return %true if a CPU which supports
  * runtime configurable endianness is currently big-endian. Non-configurable
  * CPUs can use the default implementation of this method. This method should
@@ -149,7 +148,6 @@ struct CPUClass {
     void (*parse_features)(const char *typename, char *str, Error **errp);
 
     int reset_dump_flags;
-    bool (*has_work)(CPUState *cpu);
     bool (*virtio_is_big_endian)(CPUState *cpu);
     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
                            uint8_t *buf, int len, bool is_write);
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 72d791438c2..f5d44ba59f3 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -19,6 +19,10 @@ struct TCGCPUOps {
      * Called when the first CPU is realized.
      */
     void (*initialize)(void);
+    /**
+     * @has_work: Callback for checking if there is work to do
+     */
+    bool (*has_work)(CPUState *cpu);
     /**
      * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
      *
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index b9ce36e59e2..4e73550f981 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -451,7 +451,11 @@ bool cpu_has_work(CPUState *cpu)
 {
     CPUClass *cc = CPU_GET_CLASS(cpu);
 
-    return cc->has_work(cpu);
+    if (cc->tcg_ops->has_work) {
+        return cc->tcg_ops->has_work(cpu);
+    }
+
+    return false;
 }
 
 static inline bool cpu_handle_halt(CPUState *cpu)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 00330ba07de..3110867c3a3 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -261,11 +261,6 @@ static void cpu_common_reset(DeviceState *dev)
     }
 }
 
-static bool cpu_common_has_work(CPUState *cs)
-{
-    return false;
-}
-
 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
 {
     CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
@@ -397,7 +392,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
 
     k->parse_features = cpu_common_parse_features;
     k->get_arch_id = cpu_common_get_arch_id;
-    k->has_work = cpu_common_has_work;
     k->get_paging_enabled = cpu_common_get_paging_enabled;
     k->get_memory_mapping = cpu_common_get_memory_mapping;
     k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index e50ae7bef06..57e88bbe7fd 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -210,6 +210,7 @@ static void alpha_cpu_initfn(Object *obj)
 
 static const struct TCGCPUOps alpha_tcg_ops = {
     .initialize = alpha_translate_init,
+    .has_work = alpha_cpu_has_work,
     .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
     .tlb_fill = alpha_cpu_tlb_fill,
 
@@ -230,7 +231,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
                                     &acc->parent_realize);
 
     cc->class_by_name = alpha_cpu_class_by_name;
-    cc->has_work = alpha_cpu_has_work;
     cc->dump_state = alpha_cpu_dump_state;
     cc->set_pc = alpha_cpu_set_pc;
     cc->gdb_read_register = alpha_cpu_gdb_read_register;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 6d2d9f2100f..7181deee84a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2263,6 +2263,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
 #ifdef CONFIG_TCG
 static const struct TCGCPUOps arm_tcg_ops = {
     .initialize = arm_translate_init,
+    .has_work = arm_cpu_has_work,
     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = arm_cpu_exec_interrupt,
     .tlb_fill = arm_cpu_tlb_fill,
@@ -2291,7 +2292,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
 
     cc->class_by_name = arm_cpu_class_by_name;
-    cc->has_work = arm_cpu_has_work;
     cc->dump_state = arm_cpu_dump_state;
     cc->set_pc = arm_cpu_set_pc;
     cc->gdb_read_register = arm_cpu_gdb_read_register;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 7d0ab606ae1..7416aa805d0 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -188,6 +188,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 
 static const struct TCGCPUOps avr_tcg_ops = {
     .initialize = avr_cpu_tcg_init,
+    .has_work = avr_cpu_has_work,
     .synchronize_from_tb = avr_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = avr_cpu_exec_interrupt,
     .tlb_fill = avr_cpu_tlb_fill,
@@ -208,7 +209,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
 
     cc->class_by_name = avr_cpu_class_by_name;
 
-    cc->has_work = avr_cpu_has_work;
     cc->dump_state = avr_cpu_dump_state;
     cc->set_pc = avr_cpu_set_pc;
     cc->memory_rw_debug = avr_cpu_memory_rw_debug;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 4586302ba39..eef76a211f1 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -197,6 +197,7 @@ static void cris_cpu_initfn(Object *obj)
 
 static const struct TCGCPUOps crisv10_tcg_ops = {
     .initialize = cris_initialize_crisv10_tcg,
+    .has_work = cris_cpu_has_work,
     .cpu_exec_interrupt = cris_cpu_exec_interrupt,
     .tlb_fill = cris_cpu_tlb_fill,
 
@@ -207,6 +208,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = {
 
 static const struct TCGCPUOps crisv32_tcg_ops = {
     .initialize = cris_initialize_tcg,
+    .has_work = cris_cpu_has_work,
     .cpu_exec_interrupt = cris_cpu_exec_interrupt,
     .tlb_fill = cris_cpu_tlb_fill,
 
@@ -286,7 +288,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset);
 
     cc->class_by_name = cris_cpu_class_by_name;
-    cc->has_work = cris_cpu_has_work;
     cc->dump_state = cris_cpu_dump_state;
     cc->set_pc = cris_cpu_set_pc;
     cc->gdb_read_register = cris_cpu_gdb_read_register;
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index a13a941ed5b..cda63537d32 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -268,6 +268,7 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
 
 static const struct TCGCPUOps hexagon_tcg_ops = {
     .initialize = hexagon_translate_init,
+    .has_work = hexagon_cpu_has_work,
     .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
     .tlb_fill = hexagon_tlb_fill,
 };
@@ -284,7 +285,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset);
 
     cc->class_by_name = hexagon_cpu_class_by_name;
-    cc->has_work = hexagon_cpu_has_work;
     cc->dump_state = hexagon_dump_state;
     cc->set_pc = hexagon_cpu_set_pc;
     cc->gdb_read_register = hexagon_gdb_read_register;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 5f1822b5fe6..b9437f4c534 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -135,6 +135,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
 
 static const struct TCGCPUOps hppa_tcg_ops = {
     .initialize = hppa_translate_init,
+    .has_work = hppa_cpu_has_work,
     .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
     .tlb_fill = hppa_cpu_tlb_fill,
@@ -155,7 +156,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
                                     &acc->parent_realize);
 
     cc->class_by_name = hppa_cpu_class_by_name;
-    cc->has_work = hppa_cpu_has_work;
     cc->dump_state = hppa_cpu_dump_state;
     cc->set_pc = hppa_cpu_set_pc;
     cc->gdb_read_register = hppa_cpu_gdb_read_register;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 50008431c35..464e136a072 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7171,6 +7171,7 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.eip = value;
 }
 
+/* FIXME TCG only? */
 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
 {
     X86CPU *cpu = X86_CPU(cs);
@@ -7213,11 +7214,6 @@ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
     return 0;
 }
 
-static bool x86_cpu_has_work(CPUState *cs)
-{
-    return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
-}
-
 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
 {
     X86CPU *cpu = X86_CPU(cs);
@@ -7404,7 +7400,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
 
     cc->class_by_name = x86_cpu_class_by_name;
     cc->parse_features = x86_cpu_parse_featurestr;
-    cc->has_work = x86_cpu_has_work;
 
 #ifdef CONFIG_TCG
     tcg_cpu_common_class_init(cc);
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 6a35aa664dc..fee8487135d 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -57,10 +57,16 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
     cpu->env.eip = tb->pc - tb->cs_base;
 }
 
+static bool x86_cpu_has_work(CPUState *cs)
+{
+    return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
+}
+
 #include "hw/core/tcg-cpu-ops.h"
 
 static const struct TCGCPUOps x86_tcg_ops = {
     .initialize = tcg_x86_init,
+    .has_work = x86_cpu_has_work,
     .synchronize_from_tb = x86_cpu_synchronize_from_tb,
     .cpu_exec_enter = x86_cpu_exec_enter,
     .cpu_exec_exit = x86_cpu_exec_exit,
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 4ad253a50ec..5d18255ac83 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -214,6 +214,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
 
 static const struct TCGCPUOps lm32_tcg_ops = {
     .initialize = lm32_translate_init,
+    .has_work = lm32_cpu_has_work,
     .cpu_exec_interrupt = lm32_cpu_exec_interrupt,
     .tlb_fill = lm32_cpu_tlb_fill,
     .debug_excp_handler = lm32_debug_excp_handler,
@@ -234,7 +235,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset);
 
     cc->class_by_name = lm32_cpu_class_by_name;
-    cc->has_work = lm32_cpu_has_work;
     cc->dump_state = lm32_cpu_dump_state;
     cc->set_pc = lm32_cpu_set_pc;
     cc->gdb_read_register = lm32_cpu_gdb_read_register;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 9b2f651213b..9c38138215f 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -506,6 +506,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
 
 static const struct TCGCPUOps m68k_tcg_ops = {
     .initialize = m68k_tcg_init,
+    .has_work = m68k_cpu_has_work,
     .cpu_exec_interrupt = m68k_cpu_exec_interrupt,
     .tlb_fill = m68k_cpu_tlb_fill,
 
@@ -526,7 +527,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset);
 
     cc->class_by_name = m68k_cpu_class_by_name;
-    cc->has_work = m68k_cpu_has_work;
     cc->dump_state = m68k_cpu_dump_state;
     cc->set_pc = m68k_cpu_set_pc;
     cc->gdb_read_register = m68k_cpu_gdb_read_register;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 4e086ab5465..809f42b5e0d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -356,6 +356,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
 
 static const struct TCGCPUOps mb_tcg_ops = {
     .initialize = mb_tcg_init,
+    .has_work = mb_cpu_has_work,
     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = mb_cpu_exec_interrupt,
     .tlb_fill = mb_cpu_tlb_fill,
@@ -378,7 +379,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
 
     cc->class_by_name = mb_cpu_class_by_name;
-    cc->has_work = mb_cpu_has_work;
 
     cc->dump_state = mb_cpu_dump_state;
     cc->set_pc = mb_cpu_set_pc;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 81030c5c407..a189710904a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -688,6 +688,7 @@ static Property mips_cpu_properties[] = {
  */
 static const struct TCGCPUOps mips_tcg_ops = {
     .initialize = mips_tcg_init,
+    .has_work = mips_cpu_has_work,
     .synchronize_from_tb = mips_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = mips_cpu_exec_interrupt,
     .tlb_fill = mips_cpu_tlb_fill,
@@ -713,7 +714,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_props(dc, mips_cpu_properties);
 
     cc->class_by_name = mips_cpu_class_by_name;
-    cc->has_work = mips_cpu_has_work;
     cc->dump_state = mips_cpu_dump_state;
     cc->set_pc = mips_cpu_set_pc;
     cc->gdb_read_register = mips_cpu_gdb_read_register;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index c3de71b82fe..942804de21b 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -98,6 +98,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
 
 static const struct TCGCPUOps moxie_tcg_ops = {
     .initialize = moxie_translate_init,
+    .has_work = moxie_cpu_has_work,
     .tlb_fill = moxie_cpu_tlb_fill,
 
 #ifndef CONFIG_USER_ONLY
@@ -117,7 +118,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
 
     cc->class_by_name = moxie_cpu_class_by_name;
 
-    cc->has_work = moxie_cpu_has_work;
     cc->dump_state = moxie_cpu_dump_state;
     cc->set_pc = moxie_cpu_set_pc;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 0de93cdd98f..cfd9f002436 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -211,6 +211,7 @@ static Property nios2_properties[] = {
 
 static const struct TCGCPUOps nios2_tcg_ops = {
     .initialize = nios2_tcg_init,
+    .has_work = nios2_cpu_has_work,
     .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
     .tlb_fill = nios2_cpu_tlb_fill,
 
@@ -232,7 +233,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset);
 
     cc->class_by_name = nios2_cpu_class_by_name;
-    cc->has_work = nios2_cpu_has_work;
     cc->dump_state = nios2_cpu_dump_state;
     cc->set_pc = nios2_cpu_set_pc;
     cc->disas_set_info = nios2_cpu_disas_set_info;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 52aef277232..674e1ac0d23 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -178,6 +178,7 @@ static void openrisc_any_initfn(Object *obj)
 
 static const struct TCGCPUOps openrisc_tcg_ops = {
     .initialize = openrisc_translate_init,
+    .has_work = openrisc_cpu_has_work,
     .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
     .tlb_fill = openrisc_cpu_tlb_fill,
 
@@ -197,7 +198,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset);
 
     cc->class_by_name = openrisc_cpu_class_by_name;
-    cc->has_work = openrisc_cpu_has_work;
     cc->dump_state = openrisc_cpu_dump_state;
     cc->set_pc = openrisc_cpu_set_pc;
     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6f9822bc0a1..a5de166bb3f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -584,6 +584,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 
 static const struct TCGCPUOps riscv_tcg_ops = {
     .initialize = riscv_translate_init,
+    .has_work = riscv_cpu_has_work,
     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
     .tlb_fill = riscv_cpu_tlb_fill,
@@ -607,7 +608,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 
     cc->class_by_name = riscv_cpu_class_by_name;
-    cc->has_work = riscv_cpu_has_work;
     cc->dump_state = riscv_cpu_dump_state;
     cc->set_pc = riscv_cpu_set_pc;
     cc->gdb_read_register = riscv_cpu_gdb_read_register;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 28d2becc32c..f5f967ff509 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -177,6 +177,7 @@ static void rx_cpu_init(Object *obj)
 
 static const struct TCGCPUOps rx_tcg_ops = {
     .initialize = rx_translate_init,
+    .has_work = rx_cpu_has_work,
     .synchronize_from_tb = rx_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = rx_cpu_exec_interrupt,
     .tlb_fill = rx_cpu_tlb_fill,
@@ -198,7 +199,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
                                   &rcc->parent_reset);
 
     cc->class_by_name = rx_cpu_class_by_name;
-    cc->has_work = rx_cpu_has_work;
     cc->dump_state = rx_cpu_dump_state;
     cc->set_pc = rx_cpu_set_pc;
 
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d57f69e7f7d..d2f897bf41a 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -465,6 +465,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
 
 static const struct TCGCPUOps s390_tcg_ops = {
     .initialize = s390x_translate_init,
+    .has_work = s390_cpu_has_work,
     .tlb_fill = s390_cpu_tlb_fill,
 
 #if !defined(CONFIG_USER_ONLY)
@@ -493,7 +494,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
 #endif
     scc->reset = s390_cpu_reset;
     cc->class_by_name = s390_cpu_class_by_name,
-    cc->has_work = s390_cpu_has_work;
     cc->dump_state = s390_cpu_dump_state;
     cc->set_pc = s390_cpu_set_pc;
     cc->gdb_read_register = s390_cpu_gdb_read_register;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 9d77f9cfdae..8bac001bfa4 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -227,6 +227,7 @@ static const VMStateDescription vmstate_sh_cpu = {
 
 static const struct TCGCPUOps superh_tcg_ops = {
     .initialize = sh4_translate_init,
+    .has_work = superh_cpu_has_work,
     .synchronize_from_tb = superh_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = superh_cpu_exec_interrupt,
     .tlb_fill = superh_cpu_tlb_fill,
@@ -250,7 +251,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset);
 
     cc->class_by_name = superh_cpu_class_by_name;
-    cc->has_work = superh_cpu_has_work;
     cc->dump_state = superh_cpu_dump_state;
     cc->set_pc = superh_cpu_set_pc;
     cc->gdb_read_register = superh_cpu_gdb_read_register;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ccabe189c4a..761813ce96b 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -853,6 +853,7 @@ static Property sparc_cpu_properties[] = {
 
 static const struct TCGCPUOps sparc_tcg_ops = {
     .initialize = sparc_tcg_init,
+    .has_work = sparc_cpu_has_work,
     .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
     .tlb_fill = sparc_cpu_tlb_fill,
@@ -879,7 +880,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
 
     cc->class_by_name = sparc_cpu_class_by_name;
     cc->parse_features = sparc_cpu_parse_features;
-    cc->has_work = sparc_cpu_has_work;
     cc->dump_state = sparc_cpu_dump_state;
 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
     cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index c7f8a898caf..3bc89e736b3 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -138,6 +138,7 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 
 static const struct TCGCPUOps tilegx_tcg_ops = {
     .initialize = tilegx_tcg_init,
+    .has_work = tilegx_cpu_has_work,
     .cpu_exec_interrupt = tilegx_cpu_exec_interrupt,
     .tlb_fill = tilegx_cpu_tlb_fill,
 
@@ -158,7 +159,6 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, tilegx_cpu_reset, &tcc->parent_reset);
 
     cc->class_by_name = tilegx_cpu_class_by_name;
-    cc->has_work = tilegx_cpu_has_work;
     cc->dump_state = tilegx_cpu_dump_state;
     cc->set_pc = tilegx_cpu_set_pc;
     cc->gdb_num_core_regs = 0;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 5b500b575bd..b493e3ede85 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -146,6 +146,7 @@ static void tc27x_initfn(Object *obj)
 
 static const struct TCGCPUOps tricore_tcg_ops = {
     .initialize = tricore_tcg_init,
+    .has_work = tricore_cpu_has_work,
     .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
     .tlb_fill = tricore_cpu_tlb_fill,
 };
@@ -161,7 +162,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
 
     device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset);
     cc->class_by_name = tricore_cpu_class_by_name;
-    cc->has_work = tricore_cpu_has_work;
 
     cc->gdb_read_register = tricore_cpu_gdb_read_register;
     cc->gdb_write_register = tricore_cpu_gdb_write_register;
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index a732b08748d..55569018296 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -124,6 +124,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
 
 static const struct TCGCPUOps uc32_tcg_ops = {
     .initialize = uc32_translate_init,
+    .has_work = uc32_cpu_has_work,
     .cpu_exec_interrupt = uc32_cpu_exec_interrupt,
     .tlb_fill = uc32_cpu_tlb_fill,
 
@@ -142,7 +143,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
                                     &ucc->parent_realize);
 
     cc->class_by_name = uc32_cpu_class_by_name;
-    cc->has_work = uc32_cpu_has_work;
     cc->dump_state = uc32_cpu_dump_state;
     cc->set_pc = uc32_cpu_set_pc;
     cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index badc3a26aa2..849a664a679 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -185,6 +185,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
 
 static const struct TCGCPUOps xtensa_tcg_ops = {
     .initialize = xtensa_translate_init,
+    .has_work = xtensa_cpu_has_work,
     .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
     .tlb_fill = xtensa_cpu_tlb_fill,
     .debug_excp_handler = xtensa_breakpoint_handler,
@@ -208,7 +209,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
 
     cc->class_by_name = xtensa_cpu_class_by_name;
-    cc->has_work = xtensa_cpu_has_work;
     cc->dump_state = xtensa_cpu_dump_state;
     cc->set_pc = xtensa_cpu_set_pc;
     cc->gdb_read_register = xtensa_cpu_gdb_read_register;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index fe76d0b3773..1558de804c9 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -8633,7 +8633,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
     pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER7;
     pcc->check_pow = check_pow_nocheck;
-    cc->has_work = cpu_has_work_POWER7;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -8806,7 +8805,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
     pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER8;
     pcc->check_pow = check_pow_nocheck;
-    cc->has_work = cpu_has_work_POWER8;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -9026,7 +9024,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
                          PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER9;
     pcc->check_pow = check_pow_nocheck;
-    cc->has_work = cpu_has_work_POWER9;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -9241,7 +9238,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
                          PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER10;
     pcc->check_pow = check_pow_nocheck;
-    cc->has_work = cpu_has_work_POWER10;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -10865,6 +10861,7 @@ static Property ppc_cpu_properties[] = {
 
 static const struct TCGCPUOps ppc_tcg_ops = {
   .initialize = ppc_translate_init,
+  .has_work = ppc_cpu_has_work,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
@@ -10878,6 +10875,7 @@ static const struct TCGCPUOps ppc_tcg_ops = {
 
 static const struct TCGCPUOps power7_tcg_ops = {
   .initialize = ppc_translate_init,
+  .has_work = cpu_has_work_POWER7,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
@@ -10891,6 +10889,7 @@ static const struct TCGCPUOps power7_tcg_ops = {
 
 static const struct TCGCPUOps power8_tcg_ops = {
   .initialize = ppc_translate_init,
+  .has_work = cpu_has_work_POWER8,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
@@ -10904,6 +10903,7 @@ static const struct TCGCPUOps power8_tcg_ops = {
 
 static const struct TCGCPUOps power9_tcg_ops = {
   .initialize = ppc_translate_init,
+  .has_work = cpu_has_work_POWER9,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
@@ -10917,6 +10917,7 @@ static const struct TCGCPUOps power9_tcg_ops = {
 
 static const struct TCGCPUOps power10_tcg_ops = {
   .initialize = ppc_translate_init,
+  .has_work = cpu_has_work_POWER10,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
@@ -10946,7 +10947,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
 
     cc->class_by_name = ppc_cpu_class_by_name;
-    cc->has_work = ppc_cpu_has_work;
     cc->dump_state = ppc_cpu_dump_state;
     cc->dump_statistics = ppc_cpu_dump_statistics;
     cc->set_pc = ppc_cpu_set_pc;
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 7/8] cpu: Move CPUClass::has_work() to TCGCPUOps
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Claudio Fontana,
	Philippe Mathieu-Daudé,
	Taylor Simpson, Marcel Apfelbaum, Michael Rolnik, Sarah Harris,
	Edgar E. Iglesias, Michael Walle, Aurelien Jarno, Jiaxun Yang,
	Aleksandar Rikalo, Anthony Green, Chris Wulff, Marek Vasut,
	Stafford Horne, Palmer Dabbelt, Alistair Francis,
	Sagar Karandikar, Bastian Koppelmann, Yoshinori Sato,
	Mark Cave-Ayland, Artyom Tarasenko, Guan Xuetao, Max Filippov

We can only check if a vCPU has work with TCG.
Restrict the has_work() handler to TCG by moving it to
the TCGCPUOps structure, and adapt all the targets.

cpu_common_has_work() is removed as being inlined in
cpu_has_work().

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- finished PPC
- check cc->tcg_ops->has_work non-null (thuth)
---
 include/hw/core/cpu.h           |  2 --
 include/hw/core/tcg-cpu-ops.h   |  4 ++++
 accel/tcg/cpu-exec.c            |  6 +++++-
 hw/core/cpu.c                   |  6 ------
 target/alpha/cpu.c              |  2 +-
 target/arm/cpu.c                |  2 +-
 target/avr/cpu.c                |  2 +-
 target/cris/cpu.c               |  3 ++-
 target/hexagon/cpu.c            |  2 +-
 target/hppa/cpu.c               |  2 +-
 target/i386/cpu.c               |  7 +------
 target/i386/tcg/tcg-cpu.c       |  6 ++++++
 target/lm32/cpu.c               |  2 +-
 target/m68k/cpu.c               |  2 +-
 target/microblaze/cpu.c         |  2 +-
 target/mips/cpu.c               |  2 +-
 target/moxie/cpu.c              |  2 +-
 target/nios2/cpu.c              |  2 +-
 target/openrisc/cpu.c           |  2 +-
 target/riscv/cpu.c              |  2 +-
 target/rx/cpu.c                 |  2 +-
 target/s390x/cpu.c              |  2 +-
 target/sh4/cpu.c                |  2 +-
 target/sparc/cpu.c              |  2 +-
 target/tilegx/cpu.c             |  2 +-
 target/tricore/cpu.c            |  2 +-
 target/unicore32/cpu.c          |  2 +-
 target/xtensa/cpu.c             |  2 +-
 target/ppc/translate_init.c.inc | 10 +++++-----
 29 files changed, 44 insertions(+), 42 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 66109bcca35..8efea289e7e 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -86,7 +86,6 @@ struct AccelCPUClass;
  * instantiatable CPU type.
  * @parse_features: Callback to parse command line arguments.
  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
- * @has_work: Callback for checking if there is work to do.
  * @virtio_is_big_endian: Callback to return %true if a CPU which supports
  * runtime configurable endianness is currently big-endian. Non-configurable
  * CPUs can use the default implementation of this method. This method should
@@ -149,7 +148,6 @@ struct CPUClass {
     void (*parse_features)(const char *typename, char *str, Error **errp);
 
     int reset_dump_flags;
-    bool (*has_work)(CPUState *cpu);
     bool (*virtio_is_big_endian)(CPUState *cpu);
     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
                            uint8_t *buf, int len, bool is_write);
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 72d791438c2..f5d44ba59f3 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -19,6 +19,10 @@ struct TCGCPUOps {
      * Called when the first CPU is realized.
      */
     void (*initialize)(void);
+    /**
+     * @has_work: Callback for checking if there is work to do
+     */
+    bool (*has_work)(CPUState *cpu);
     /**
      * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
      *
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index b9ce36e59e2..4e73550f981 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -451,7 +451,11 @@ bool cpu_has_work(CPUState *cpu)
 {
     CPUClass *cc = CPU_GET_CLASS(cpu);
 
-    return cc->has_work(cpu);
+    if (cc->tcg_ops->has_work) {
+        return cc->tcg_ops->has_work(cpu);
+    }
+
+    return false;
 }
 
 static inline bool cpu_handle_halt(CPUState *cpu)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 00330ba07de..3110867c3a3 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -261,11 +261,6 @@ static void cpu_common_reset(DeviceState *dev)
     }
 }
 
-static bool cpu_common_has_work(CPUState *cs)
-{
-    return false;
-}
-
 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
 {
     CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
@@ -397,7 +392,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
 
     k->parse_features = cpu_common_parse_features;
     k->get_arch_id = cpu_common_get_arch_id;
-    k->has_work = cpu_common_has_work;
     k->get_paging_enabled = cpu_common_get_paging_enabled;
     k->get_memory_mapping = cpu_common_get_memory_mapping;
     k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index e50ae7bef06..57e88bbe7fd 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -210,6 +210,7 @@ static void alpha_cpu_initfn(Object *obj)
 
 static const struct TCGCPUOps alpha_tcg_ops = {
     .initialize = alpha_translate_init,
+    .has_work = alpha_cpu_has_work,
     .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
     .tlb_fill = alpha_cpu_tlb_fill,
 
@@ -230,7 +231,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
                                     &acc->parent_realize);
 
     cc->class_by_name = alpha_cpu_class_by_name;
-    cc->has_work = alpha_cpu_has_work;
     cc->dump_state = alpha_cpu_dump_state;
     cc->set_pc = alpha_cpu_set_pc;
     cc->gdb_read_register = alpha_cpu_gdb_read_register;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 6d2d9f2100f..7181deee84a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2263,6 +2263,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
 #ifdef CONFIG_TCG
 static const struct TCGCPUOps arm_tcg_ops = {
     .initialize = arm_translate_init,
+    .has_work = arm_cpu_has_work,
     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = arm_cpu_exec_interrupt,
     .tlb_fill = arm_cpu_tlb_fill,
@@ -2291,7 +2292,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
 
     cc->class_by_name = arm_cpu_class_by_name;
-    cc->has_work = arm_cpu_has_work;
     cc->dump_state = arm_cpu_dump_state;
     cc->set_pc = arm_cpu_set_pc;
     cc->gdb_read_register = arm_cpu_gdb_read_register;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 7d0ab606ae1..7416aa805d0 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -188,6 +188,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 
 static const struct TCGCPUOps avr_tcg_ops = {
     .initialize = avr_cpu_tcg_init,
+    .has_work = avr_cpu_has_work,
     .synchronize_from_tb = avr_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = avr_cpu_exec_interrupt,
     .tlb_fill = avr_cpu_tlb_fill,
@@ -208,7 +209,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
 
     cc->class_by_name = avr_cpu_class_by_name;
 
-    cc->has_work = avr_cpu_has_work;
     cc->dump_state = avr_cpu_dump_state;
     cc->set_pc = avr_cpu_set_pc;
     cc->memory_rw_debug = avr_cpu_memory_rw_debug;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 4586302ba39..eef76a211f1 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -197,6 +197,7 @@ static void cris_cpu_initfn(Object *obj)
 
 static const struct TCGCPUOps crisv10_tcg_ops = {
     .initialize = cris_initialize_crisv10_tcg,
+    .has_work = cris_cpu_has_work,
     .cpu_exec_interrupt = cris_cpu_exec_interrupt,
     .tlb_fill = cris_cpu_tlb_fill,
 
@@ -207,6 +208,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = {
 
 static const struct TCGCPUOps crisv32_tcg_ops = {
     .initialize = cris_initialize_tcg,
+    .has_work = cris_cpu_has_work,
     .cpu_exec_interrupt = cris_cpu_exec_interrupt,
     .tlb_fill = cris_cpu_tlb_fill,
 
@@ -286,7 +288,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset);
 
     cc->class_by_name = cris_cpu_class_by_name;
-    cc->has_work = cris_cpu_has_work;
     cc->dump_state = cris_cpu_dump_state;
     cc->set_pc = cris_cpu_set_pc;
     cc->gdb_read_register = cris_cpu_gdb_read_register;
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index a13a941ed5b..cda63537d32 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -268,6 +268,7 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
 
 static const struct TCGCPUOps hexagon_tcg_ops = {
     .initialize = hexagon_translate_init,
+    .has_work = hexagon_cpu_has_work,
     .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
     .tlb_fill = hexagon_tlb_fill,
 };
@@ -284,7 +285,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset);
 
     cc->class_by_name = hexagon_cpu_class_by_name;
-    cc->has_work = hexagon_cpu_has_work;
     cc->dump_state = hexagon_dump_state;
     cc->set_pc = hexagon_cpu_set_pc;
     cc->gdb_read_register = hexagon_gdb_read_register;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 5f1822b5fe6..b9437f4c534 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -135,6 +135,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
 
 static const struct TCGCPUOps hppa_tcg_ops = {
     .initialize = hppa_translate_init,
+    .has_work = hppa_cpu_has_work,
     .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
     .tlb_fill = hppa_cpu_tlb_fill,
@@ -155,7 +156,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
                                     &acc->parent_realize);
 
     cc->class_by_name = hppa_cpu_class_by_name;
-    cc->has_work = hppa_cpu_has_work;
     cc->dump_state = hppa_cpu_dump_state;
     cc->set_pc = hppa_cpu_set_pc;
     cc->gdb_read_register = hppa_cpu_gdb_read_register;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 50008431c35..464e136a072 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7171,6 +7171,7 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.eip = value;
 }
 
+/* FIXME TCG only? */
 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
 {
     X86CPU *cpu = X86_CPU(cs);
@@ -7213,11 +7214,6 @@ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
     return 0;
 }
 
-static bool x86_cpu_has_work(CPUState *cs)
-{
-    return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
-}
-
 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
 {
     X86CPU *cpu = X86_CPU(cs);
@@ -7404,7 +7400,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
 
     cc->class_by_name = x86_cpu_class_by_name;
     cc->parse_features = x86_cpu_parse_featurestr;
-    cc->has_work = x86_cpu_has_work;
 
 #ifdef CONFIG_TCG
     tcg_cpu_common_class_init(cc);
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 6a35aa664dc..fee8487135d 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -57,10 +57,16 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
     cpu->env.eip = tb->pc - tb->cs_base;
 }
 
+static bool x86_cpu_has_work(CPUState *cs)
+{
+    return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
+}
+
 #include "hw/core/tcg-cpu-ops.h"
 
 static const struct TCGCPUOps x86_tcg_ops = {
     .initialize = tcg_x86_init,
+    .has_work = x86_cpu_has_work,
     .synchronize_from_tb = x86_cpu_synchronize_from_tb,
     .cpu_exec_enter = x86_cpu_exec_enter,
     .cpu_exec_exit = x86_cpu_exec_exit,
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 4ad253a50ec..5d18255ac83 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -214,6 +214,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
 
 static const struct TCGCPUOps lm32_tcg_ops = {
     .initialize = lm32_translate_init,
+    .has_work = lm32_cpu_has_work,
     .cpu_exec_interrupt = lm32_cpu_exec_interrupt,
     .tlb_fill = lm32_cpu_tlb_fill,
     .debug_excp_handler = lm32_debug_excp_handler,
@@ -234,7 +235,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset);
 
     cc->class_by_name = lm32_cpu_class_by_name;
-    cc->has_work = lm32_cpu_has_work;
     cc->dump_state = lm32_cpu_dump_state;
     cc->set_pc = lm32_cpu_set_pc;
     cc->gdb_read_register = lm32_cpu_gdb_read_register;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 9b2f651213b..9c38138215f 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -506,6 +506,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
 
 static const struct TCGCPUOps m68k_tcg_ops = {
     .initialize = m68k_tcg_init,
+    .has_work = m68k_cpu_has_work,
     .cpu_exec_interrupt = m68k_cpu_exec_interrupt,
     .tlb_fill = m68k_cpu_tlb_fill,
 
@@ -526,7 +527,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset);
 
     cc->class_by_name = m68k_cpu_class_by_name;
-    cc->has_work = m68k_cpu_has_work;
     cc->dump_state = m68k_cpu_dump_state;
     cc->set_pc = m68k_cpu_set_pc;
     cc->gdb_read_register = m68k_cpu_gdb_read_register;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 4e086ab5465..809f42b5e0d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -356,6 +356,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
 
 static const struct TCGCPUOps mb_tcg_ops = {
     .initialize = mb_tcg_init,
+    .has_work = mb_cpu_has_work,
     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = mb_cpu_exec_interrupt,
     .tlb_fill = mb_cpu_tlb_fill,
@@ -378,7 +379,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
 
     cc->class_by_name = mb_cpu_class_by_name;
-    cc->has_work = mb_cpu_has_work;
 
     cc->dump_state = mb_cpu_dump_state;
     cc->set_pc = mb_cpu_set_pc;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 81030c5c407..a189710904a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -688,6 +688,7 @@ static Property mips_cpu_properties[] = {
  */
 static const struct TCGCPUOps mips_tcg_ops = {
     .initialize = mips_tcg_init,
+    .has_work = mips_cpu_has_work,
     .synchronize_from_tb = mips_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = mips_cpu_exec_interrupt,
     .tlb_fill = mips_cpu_tlb_fill,
@@ -713,7 +714,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_props(dc, mips_cpu_properties);
 
     cc->class_by_name = mips_cpu_class_by_name;
-    cc->has_work = mips_cpu_has_work;
     cc->dump_state = mips_cpu_dump_state;
     cc->set_pc = mips_cpu_set_pc;
     cc->gdb_read_register = mips_cpu_gdb_read_register;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index c3de71b82fe..942804de21b 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -98,6 +98,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
 
 static const struct TCGCPUOps moxie_tcg_ops = {
     .initialize = moxie_translate_init,
+    .has_work = moxie_cpu_has_work,
     .tlb_fill = moxie_cpu_tlb_fill,
 
 #ifndef CONFIG_USER_ONLY
@@ -117,7 +118,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
 
     cc->class_by_name = moxie_cpu_class_by_name;
 
-    cc->has_work = moxie_cpu_has_work;
     cc->dump_state = moxie_cpu_dump_state;
     cc->set_pc = moxie_cpu_set_pc;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 0de93cdd98f..cfd9f002436 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -211,6 +211,7 @@ static Property nios2_properties[] = {
 
 static const struct TCGCPUOps nios2_tcg_ops = {
     .initialize = nios2_tcg_init,
+    .has_work = nios2_cpu_has_work,
     .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
     .tlb_fill = nios2_cpu_tlb_fill,
 
@@ -232,7 +233,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset);
 
     cc->class_by_name = nios2_cpu_class_by_name;
-    cc->has_work = nios2_cpu_has_work;
     cc->dump_state = nios2_cpu_dump_state;
     cc->set_pc = nios2_cpu_set_pc;
     cc->disas_set_info = nios2_cpu_disas_set_info;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 52aef277232..674e1ac0d23 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -178,6 +178,7 @@ static void openrisc_any_initfn(Object *obj)
 
 static const struct TCGCPUOps openrisc_tcg_ops = {
     .initialize = openrisc_translate_init,
+    .has_work = openrisc_cpu_has_work,
     .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
     .tlb_fill = openrisc_cpu_tlb_fill,
 
@@ -197,7 +198,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset);
 
     cc->class_by_name = openrisc_cpu_class_by_name;
-    cc->has_work = openrisc_cpu_has_work;
     cc->dump_state = openrisc_cpu_dump_state;
     cc->set_pc = openrisc_cpu_set_pc;
     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6f9822bc0a1..a5de166bb3f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -584,6 +584,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 
 static const struct TCGCPUOps riscv_tcg_ops = {
     .initialize = riscv_translate_init,
+    .has_work = riscv_cpu_has_work,
     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
     .tlb_fill = riscv_cpu_tlb_fill,
@@ -607,7 +608,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 
     cc->class_by_name = riscv_cpu_class_by_name;
-    cc->has_work = riscv_cpu_has_work;
     cc->dump_state = riscv_cpu_dump_state;
     cc->set_pc = riscv_cpu_set_pc;
     cc->gdb_read_register = riscv_cpu_gdb_read_register;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 28d2becc32c..f5f967ff509 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -177,6 +177,7 @@ static void rx_cpu_init(Object *obj)
 
 static const struct TCGCPUOps rx_tcg_ops = {
     .initialize = rx_translate_init,
+    .has_work = rx_cpu_has_work,
     .synchronize_from_tb = rx_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = rx_cpu_exec_interrupt,
     .tlb_fill = rx_cpu_tlb_fill,
@@ -198,7 +199,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
                                   &rcc->parent_reset);
 
     cc->class_by_name = rx_cpu_class_by_name;
-    cc->has_work = rx_cpu_has_work;
     cc->dump_state = rx_cpu_dump_state;
     cc->set_pc = rx_cpu_set_pc;
 
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d57f69e7f7d..d2f897bf41a 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -465,6 +465,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
 
 static const struct TCGCPUOps s390_tcg_ops = {
     .initialize = s390x_translate_init,
+    .has_work = s390_cpu_has_work,
     .tlb_fill = s390_cpu_tlb_fill,
 
 #if !defined(CONFIG_USER_ONLY)
@@ -493,7 +494,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
 #endif
     scc->reset = s390_cpu_reset;
     cc->class_by_name = s390_cpu_class_by_name,
-    cc->has_work = s390_cpu_has_work;
     cc->dump_state = s390_cpu_dump_state;
     cc->set_pc = s390_cpu_set_pc;
     cc->gdb_read_register = s390_cpu_gdb_read_register;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 9d77f9cfdae..8bac001bfa4 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -227,6 +227,7 @@ static const VMStateDescription vmstate_sh_cpu = {
 
 static const struct TCGCPUOps superh_tcg_ops = {
     .initialize = sh4_translate_init,
+    .has_work = superh_cpu_has_work,
     .synchronize_from_tb = superh_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = superh_cpu_exec_interrupt,
     .tlb_fill = superh_cpu_tlb_fill,
@@ -250,7 +251,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset);
 
     cc->class_by_name = superh_cpu_class_by_name;
-    cc->has_work = superh_cpu_has_work;
     cc->dump_state = superh_cpu_dump_state;
     cc->set_pc = superh_cpu_set_pc;
     cc->gdb_read_register = superh_cpu_gdb_read_register;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ccabe189c4a..761813ce96b 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -853,6 +853,7 @@ static Property sparc_cpu_properties[] = {
 
 static const struct TCGCPUOps sparc_tcg_ops = {
     .initialize = sparc_tcg_init,
+    .has_work = sparc_cpu_has_work,
     .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
     .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
     .tlb_fill = sparc_cpu_tlb_fill,
@@ -879,7 +880,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
 
     cc->class_by_name = sparc_cpu_class_by_name;
     cc->parse_features = sparc_cpu_parse_features;
-    cc->has_work = sparc_cpu_has_work;
     cc->dump_state = sparc_cpu_dump_state;
 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
     cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index c7f8a898caf..3bc89e736b3 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -138,6 +138,7 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 
 static const struct TCGCPUOps tilegx_tcg_ops = {
     .initialize = tilegx_tcg_init,
+    .has_work = tilegx_cpu_has_work,
     .cpu_exec_interrupt = tilegx_cpu_exec_interrupt,
     .tlb_fill = tilegx_cpu_tlb_fill,
 
@@ -158,7 +159,6 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, tilegx_cpu_reset, &tcc->parent_reset);
 
     cc->class_by_name = tilegx_cpu_class_by_name;
-    cc->has_work = tilegx_cpu_has_work;
     cc->dump_state = tilegx_cpu_dump_state;
     cc->set_pc = tilegx_cpu_set_pc;
     cc->gdb_num_core_regs = 0;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 5b500b575bd..b493e3ede85 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -146,6 +146,7 @@ static void tc27x_initfn(Object *obj)
 
 static const struct TCGCPUOps tricore_tcg_ops = {
     .initialize = tricore_tcg_init,
+    .has_work = tricore_cpu_has_work,
     .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
     .tlb_fill = tricore_cpu_tlb_fill,
 };
@@ -161,7 +162,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
 
     device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset);
     cc->class_by_name = tricore_cpu_class_by_name;
-    cc->has_work = tricore_cpu_has_work;
 
     cc->gdb_read_register = tricore_cpu_gdb_read_register;
     cc->gdb_write_register = tricore_cpu_gdb_write_register;
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index a732b08748d..55569018296 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -124,6 +124,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
 
 static const struct TCGCPUOps uc32_tcg_ops = {
     .initialize = uc32_translate_init,
+    .has_work = uc32_cpu_has_work,
     .cpu_exec_interrupt = uc32_cpu_exec_interrupt,
     .tlb_fill = uc32_cpu_tlb_fill,
 
@@ -142,7 +143,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
                                     &ucc->parent_realize);
 
     cc->class_by_name = uc32_cpu_class_by_name;
-    cc->has_work = uc32_cpu_has_work;
     cc->dump_state = uc32_cpu_dump_state;
     cc->set_pc = uc32_cpu_set_pc;
     cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index badc3a26aa2..849a664a679 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -185,6 +185,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
 
 static const struct TCGCPUOps xtensa_tcg_ops = {
     .initialize = xtensa_translate_init,
+    .has_work = xtensa_cpu_has_work,
     .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
     .tlb_fill = xtensa_cpu_tlb_fill,
     .debug_excp_handler = xtensa_breakpoint_handler,
@@ -208,7 +209,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
 
     cc->class_by_name = xtensa_cpu_class_by_name;
-    cc->has_work = xtensa_cpu_has_work;
     cc->dump_state = xtensa_cpu_dump_state;
     cc->set_pc = xtensa_cpu_set_pc;
     cc->gdb_read_register = xtensa_cpu_gdb_read_register;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index fe76d0b3773..1558de804c9 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -8633,7 +8633,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
     pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER7;
     pcc->check_pow = check_pow_nocheck;
-    cc->has_work = cpu_has_work_POWER7;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -8806,7 +8805,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
     pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER8;
     pcc->check_pow = check_pow_nocheck;
-    cc->has_work = cpu_has_work_POWER8;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -9026,7 +9024,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
                          PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER9;
     pcc->check_pow = check_pow_nocheck;
-    cc->has_work = cpu_has_work_POWER9;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -9241,7 +9238,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
                          PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER10;
     pcc->check_pow = check_pow_nocheck;
-    cc->has_work = cpu_has_work_POWER10;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -10865,6 +10861,7 @@ static Property ppc_cpu_properties[] = {
 
 static const struct TCGCPUOps ppc_tcg_ops = {
   .initialize = ppc_translate_init,
+  .has_work = ppc_cpu_has_work,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
@@ -10878,6 +10875,7 @@ static const struct TCGCPUOps ppc_tcg_ops = {
 
 static const struct TCGCPUOps power7_tcg_ops = {
   .initialize = ppc_translate_init,
+  .has_work = cpu_has_work_POWER7,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
@@ -10891,6 +10889,7 @@ static const struct TCGCPUOps power7_tcg_ops = {
 
 static const struct TCGCPUOps power8_tcg_ops = {
   .initialize = ppc_translate_init,
+  .has_work = cpu_has_work_POWER8,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
@@ -10904,6 +10903,7 @@ static const struct TCGCPUOps power8_tcg_ops = {
 
 static const struct TCGCPUOps power9_tcg_ops = {
   .initialize = ppc_translate_init,
+  .has_work = cpu_has_work_POWER9,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
@@ -10917,6 +10917,7 @@ static const struct TCGCPUOps power9_tcg_ops = {
 
 static const struct TCGCPUOps power10_tcg_ops = {
   .initialize = ppc_translate_init,
+  .has_work = cpu_has_work_POWER10,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .tlb_fill = ppc_cpu_tlb_fill,
 
@@ -10946,7 +10947,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
 
     cc->class_by_name = ppc_cpu_class_by_name;
-    cc->has_work = ppc_cpu_has_work;
     cc->dump_state = ppc_cpu_dump_state;
     cc->dump_statistics = ppc_cpu_dump_statistics;
     cc->set_pc = ppc_cpu_set_pc;
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 8/8] target/arm: Restrict arm_cpu_has_work() to TCG
  2021-03-04 22:23 ` Philippe Mathieu-Daudé
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Philippe Mathieu-Daudé,
	Cornelia Huck, Richard Henderson, Laurent Vivier, Greg Kurz,
	qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
	David Gibson

arm_cpu_has_work() is only used from TCG.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/internals.h | 2 +-
 target/arm/cpu.c       | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1930be08828..db81db9bf57 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -172,8 +172,8 @@ static inline int r14_bank_number(int mode)
 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 void arm_translate_init(void);
 
-bool arm_cpu_has_work(CPUState *cs);
 #ifdef CONFIG_TCG
+bool arm_cpu_has_work(CPUState *cs);
 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
 #endif /* CONFIG_TCG */
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7181deee84a..02db969c00f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -74,7 +74,6 @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
         env->regs[15] = tb->pc;
     }
 }
-#endif /* CONFIG_TCG */
 
 bool arm_cpu_has_work(CPUState *cs)
 {
@@ -86,6 +85,7 @@ bool arm_cpu_has_work(CPUState *cs)
          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
          | CPU_INTERRUPT_EXITTB);
 }
+#endif /* CONFIG_TCG */
 
 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
                                  void *opaque)
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* [RFC PATCH v2 8/8] target/arm: Restrict arm_cpu_has_work() to TCG
@ 2021-03-04 22:23   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-04 22:23 UTC (permalink / raw)
  To: qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Claudio Fontana,
	Philippe Mathieu-Daudé

arm_cpu_has_work() is only used from TCG.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/internals.h | 2 +-
 target/arm/cpu.c       | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1930be08828..db81db9bf57 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -172,8 +172,8 @@ static inline int r14_bank_number(int mode)
 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 void arm_translate_init(void);
 
-bool arm_cpu_has_work(CPUState *cs);
 #ifdef CONFIG_TCG
+bool arm_cpu_has_work(CPUState *cs);
 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
 #endif /* CONFIG_TCG */
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7181deee84a..02db969c00f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -74,7 +74,6 @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
         env->regs[15] = tb->pc;
     }
 }
-#endif /* CONFIG_TCG */
 
 bool arm_cpu_has_work(CPUState *cs)
 {
@@ -86,6 +85,7 @@ bool arm_cpu_has_work(CPUState *cs)
          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
          | CPU_INTERRUPT_EXITTB);
 }
+#endif /* CONFIG_TCG */
 
 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
                                  void *opaque)
-- 
2.26.2



^ permalink raw reply related	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs
  2021-03-04 22:23   ` Philippe Mathieu-Daudé
@ 2021-03-05  1:05     ` David Gibson
  -1 siblings, 0 replies; 35+ messages in thread
From: David Gibson @ 2021-03-05  1:05 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Cornelia Huck, Richard Henderson,
	Laurent Vivier, qemu-devel, qemu-s390x, qemu-arm, qemu-ppc,
	Claudio Fontana, Paolo Bonzini, Greg Kurz

[-- Attachment #1: Type: text/plain, Size: 4835 bytes --]

On Thu, Mar 04, 2021 at 11:23:20PM +0100, Philippe Mathieu-Daudé wrote:
65;6203;1c> POWER CPUs have specific CPUClass::has_work() handlers.
> In preparation of moving this field to TCGCPUOps, we need
> to duplicate the current ppc_tcg_ops structure for the
> POWER cpus.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Acked-by: David Gibson <david@gibson.dropbear.id.au>

> ---
>  target/ppc/translate_init.c.inc | 69 +++++++++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index 80239077e0b..fe76d0b3773 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -48,6 +48,11 @@
>  /* #define PPC_DUMP_SPR_ACCESSES */
>  /* #define USE_APPLE_GDB */
>  
> +static const struct TCGCPUOps power7_tcg_ops;
> +static const struct TCGCPUOps power8_tcg_ops;
> +static const struct TCGCPUOps power9_tcg_ops;
> +static const struct TCGCPUOps power10_tcg_ops;
> +
>  /*
>   * Generic callbacks:
>   * do nothing but store/retrieve spr value
> @@ -8685,6 +8690,9 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
>      pcc->l1_dcache_size = 0x8000;
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +#ifdef CONFIG_TCG
> +    cc->tcg_ops = &power7_tcg_ops;
> +#endif /* CONFIG_TCG */
>  }
>  
>  static void init_proc_POWER8(CPUPPCState *env)
> @@ -8863,6 +8871,9 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>      pcc->l1_dcache_size = 0x8000;
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +#ifdef CONFIG_TCG
> +    cc->tcg_ops = &power8_tcg_ops;
> +#endif /* CONFIG_TCG */
>  }
>  
>  #ifdef CONFIG_SOFTMMU
> @@ -9081,6 +9092,9 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
>      pcc->l1_dcache_size = 0x8000;
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +#ifdef CONFIG_TCG
> +    cc->tcg_ops = &power9_tcg_ops;
> +#endif /* CONFIG_TCG */
>  }
>  
>  #ifdef CONFIG_SOFTMMU
> @@ -9292,6 +9306,9 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
>      pcc->l1_dcache_size = 0x8000;
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +#ifdef CONFIG_TCG
> +    cc->tcg_ops = &power10_tcg_ops;
> +#endif /* CONFIG_TCG */
>  }
>  
>  #if !defined(CONFIG_USER_ONLY)
> @@ -10851,6 +10868,58 @@ static const struct TCGCPUOps ppc_tcg_ops = {
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> +#ifndef CONFIG_USER_ONLY
> +  .do_interrupt = ppc_cpu_do_interrupt,
> +  .cpu_exec_enter = ppc_cpu_exec_enter,
> +  .cpu_exec_exit = ppc_cpu_exec_exit,
> +  .do_unaligned_access = ppc_cpu_do_unaligned_access,
> +#endif /* !CONFIG_USER_ONLY */
> +};
> +
> +static const struct TCGCPUOps power7_tcg_ops = {
> +  .initialize = ppc_translate_init,
> +  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> +  .tlb_fill = ppc_cpu_tlb_fill,
> +
> +#ifndef CONFIG_USER_ONLY
> +  .do_interrupt = ppc_cpu_do_interrupt,
> +  .cpu_exec_enter = ppc_cpu_exec_enter,
> +  .cpu_exec_exit = ppc_cpu_exec_exit,
> +  .do_unaligned_access = ppc_cpu_do_unaligned_access,
> +#endif /* !CONFIG_USER_ONLY */
> +};
> +
> +static const struct TCGCPUOps power8_tcg_ops = {
> +  .initialize = ppc_translate_init,
> +  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> +  .tlb_fill = ppc_cpu_tlb_fill,
> +
> +#ifndef CONFIG_USER_ONLY
> +  .do_interrupt = ppc_cpu_do_interrupt,
> +  .cpu_exec_enter = ppc_cpu_exec_enter,
> +  .cpu_exec_exit = ppc_cpu_exec_exit,
> +  .do_unaligned_access = ppc_cpu_do_unaligned_access,
> +#endif /* !CONFIG_USER_ONLY */
> +};
> +
> +static const struct TCGCPUOps power9_tcg_ops = {
> +  .initialize = ppc_translate_init,
> +  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> +  .tlb_fill = ppc_cpu_tlb_fill,
> +
> +#ifndef CONFIG_USER_ONLY
> +  .do_interrupt = ppc_cpu_do_interrupt,
> +  .cpu_exec_enter = ppc_cpu_exec_enter,
> +  .cpu_exec_exit = ppc_cpu_exec_exit,
> +  .do_unaligned_access = ppc_cpu_do_unaligned_access,
> +#endif /* !CONFIG_USER_ONLY */
> +};
> +
> +static const struct TCGCPUOps power10_tcg_ops = {
> +  .initialize = ppc_translate_init,
> +  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> +  .tlb_fill = ppc_cpu_tlb_fill,
> +
>  #ifndef CONFIG_USER_ONLY
>    .do_interrupt = ppc_cpu_do_interrupt,
>    .cpu_exec_enter = ppc_cpu_exec_enter,

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs
@ 2021-03-05  1:05     ` David Gibson
  0 siblings, 0 replies; 35+ messages in thread
From: David Gibson @ 2021-03-05  1:05 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé
  Cc: qemu-devel, David Hildenbrand, qemu-ppc, qemu-s390x, Thomas Huth,
	Laurent Vivier, Cornelia Huck, Greg Kurz, Paolo Bonzini,
	qemu-arm, Eduardo Habkost, Peter Maydell, Richard Henderson,
	qemu-riscv, Claudio Fontana

[-- Attachment #1: Type: text/plain, Size: 4835 bytes --]

On Thu, Mar 04, 2021 at 11:23:20PM +0100, Philippe Mathieu-Daudé wrote:
65;6203;1c> POWER CPUs have specific CPUClass::has_work() handlers.
> In preparation of moving this field to TCGCPUOps, we need
> to duplicate the current ppc_tcg_ops structure for the
> POWER cpus.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Acked-by: David Gibson <david@gibson.dropbear.id.au>

> ---
>  target/ppc/translate_init.c.inc | 69 +++++++++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index 80239077e0b..fe76d0b3773 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -48,6 +48,11 @@
>  /* #define PPC_DUMP_SPR_ACCESSES */
>  /* #define USE_APPLE_GDB */
>  
> +static const struct TCGCPUOps power7_tcg_ops;
> +static const struct TCGCPUOps power8_tcg_ops;
> +static const struct TCGCPUOps power9_tcg_ops;
> +static const struct TCGCPUOps power10_tcg_ops;
> +
>  /*
>   * Generic callbacks:
>   * do nothing but store/retrieve spr value
> @@ -8685,6 +8690,9 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
>      pcc->l1_dcache_size = 0x8000;
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +#ifdef CONFIG_TCG
> +    cc->tcg_ops = &power7_tcg_ops;
> +#endif /* CONFIG_TCG */
>  }
>  
>  static void init_proc_POWER8(CPUPPCState *env)
> @@ -8863,6 +8871,9 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>      pcc->l1_dcache_size = 0x8000;
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +#ifdef CONFIG_TCG
> +    cc->tcg_ops = &power8_tcg_ops;
> +#endif /* CONFIG_TCG */
>  }
>  
>  #ifdef CONFIG_SOFTMMU
> @@ -9081,6 +9092,9 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
>      pcc->l1_dcache_size = 0x8000;
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +#ifdef CONFIG_TCG
> +    cc->tcg_ops = &power9_tcg_ops;
> +#endif /* CONFIG_TCG */
>  }
>  
>  #ifdef CONFIG_SOFTMMU
> @@ -9292,6 +9306,9 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
>      pcc->l1_dcache_size = 0x8000;
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +#ifdef CONFIG_TCG
> +    cc->tcg_ops = &power10_tcg_ops;
> +#endif /* CONFIG_TCG */
>  }
>  
>  #if !defined(CONFIG_USER_ONLY)
> @@ -10851,6 +10868,58 @@ static const struct TCGCPUOps ppc_tcg_ops = {
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> +#ifndef CONFIG_USER_ONLY
> +  .do_interrupt = ppc_cpu_do_interrupt,
> +  .cpu_exec_enter = ppc_cpu_exec_enter,
> +  .cpu_exec_exit = ppc_cpu_exec_exit,
> +  .do_unaligned_access = ppc_cpu_do_unaligned_access,
> +#endif /* !CONFIG_USER_ONLY */
> +};
> +
> +static const struct TCGCPUOps power7_tcg_ops = {
> +  .initialize = ppc_translate_init,
> +  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> +  .tlb_fill = ppc_cpu_tlb_fill,
> +
> +#ifndef CONFIG_USER_ONLY
> +  .do_interrupt = ppc_cpu_do_interrupt,
> +  .cpu_exec_enter = ppc_cpu_exec_enter,
> +  .cpu_exec_exit = ppc_cpu_exec_exit,
> +  .do_unaligned_access = ppc_cpu_do_unaligned_access,
> +#endif /* !CONFIG_USER_ONLY */
> +};
> +
> +static const struct TCGCPUOps power8_tcg_ops = {
> +  .initialize = ppc_translate_init,
> +  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> +  .tlb_fill = ppc_cpu_tlb_fill,
> +
> +#ifndef CONFIG_USER_ONLY
> +  .do_interrupt = ppc_cpu_do_interrupt,
> +  .cpu_exec_enter = ppc_cpu_exec_enter,
> +  .cpu_exec_exit = ppc_cpu_exec_exit,
> +  .do_unaligned_access = ppc_cpu_do_unaligned_access,
> +#endif /* !CONFIG_USER_ONLY */
> +};
> +
> +static const struct TCGCPUOps power9_tcg_ops = {
> +  .initialize = ppc_translate_init,
> +  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> +  .tlb_fill = ppc_cpu_tlb_fill,
> +
> +#ifndef CONFIG_USER_ONLY
> +  .do_interrupt = ppc_cpu_do_interrupt,
> +  .cpu_exec_enter = ppc_cpu_exec_enter,
> +  .cpu_exec_exit = ppc_cpu_exec_exit,
> +  .do_unaligned_access = ppc_cpu_do_unaligned_access,
> +#endif /* !CONFIG_USER_ONLY */
> +};
> +
> +static const struct TCGCPUOps power10_tcg_ops = {
> +  .initialize = ppc_translate_init,
> +  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> +  .tlb_fill = ppc_cpu_tlb_fill,
> +
>  #ifndef CONFIG_USER_ONLY
>    .do_interrupt = ppc_cpu_do_interrupt,
>    .cpu_exec_enter = ppc_cpu_exec_enter,

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 7/8] cpu: Move CPUClass::has_work() to TCGCPUOps
  2021-03-04 22:23   ` Philippe Mathieu-Daudé
@ 2021-03-05  1:05     ` David Gibson
  -1 siblings, 0 replies; 35+ messages in thread
From: David Gibson @ 2021-03-05  1:05 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé
  Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
	David Hildenbrand, Anthony Green, Mark Cave-Ayland, qemu-devel,
	Max Filippov, Taylor Simpson, Alistair Francis,
	Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
	Claudio Fontana, Palmer Dabbelt, Artyom Tarasenko, Thomas Huth,
	Eduardo Habkost, Richard Henderson, Greg Kurz, qemu-s390x,
	qemu-arm, Michael Rolnik, Stafford Horne, qemu-riscv,
	Bastian Koppelmann, Cornelia Huck, Laurent Vivier, Michael Walle,
	qemu-ppc, Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno

[-- Attachment #1: Type: text/plain, Size: 30886 bytes --]

On Thu, Mar 04, 2021 at 11:23:22PM +0100, Philippe Mathieu-Daudé wrote:
> We can only check if a vCPU has work with TCG.
> Restrict the has_work() handler to TCG by moving it to
> the TCGCPUOps structure, and adapt all the targets.
> 
> cpu_common_has_work() is removed as being inlined in
> cpu_has_work().
> 
> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

ppc parts
Acked-by: David Gibson <david@gibson.dropbear.id.au>

> ---
> v2:
> - finished PPC
> - check cc->tcg_ops->has_work non-null (thuth)
> ---
>  include/hw/core/cpu.h           |  2 --
>  include/hw/core/tcg-cpu-ops.h   |  4 ++++
>  accel/tcg/cpu-exec.c            |  6 +++++-
>  hw/core/cpu.c                   |  6 ------
>  target/alpha/cpu.c              |  2 +-
>  target/arm/cpu.c                |  2 +-
>  target/avr/cpu.c                |  2 +-
>  target/cris/cpu.c               |  3 ++-
>  target/hexagon/cpu.c            |  2 +-
>  target/hppa/cpu.c               |  2 +-
>  target/i386/cpu.c               |  7 +------
>  target/i386/tcg/tcg-cpu.c       |  6 ++++++
>  target/lm32/cpu.c               |  2 +-
>  target/m68k/cpu.c               |  2 +-
>  target/microblaze/cpu.c         |  2 +-
>  target/mips/cpu.c               |  2 +-
>  target/moxie/cpu.c              |  2 +-
>  target/nios2/cpu.c              |  2 +-
>  target/openrisc/cpu.c           |  2 +-
>  target/riscv/cpu.c              |  2 +-
>  target/rx/cpu.c                 |  2 +-
>  target/s390x/cpu.c              |  2 +-
>  target/sh4/cpu.c                |  2 +-
>  target/sparc/cpu.c              |  2 +-
>  target/tilegx/cpu.c             |  2 +-
>  target/tricore/cpu.c            |  2 +-
>  target/unicore32/cpu.c          |  2 +-
>  target/xtensa/cpu.c             |  2 +-
>  target/ppc/translate_init.c.inc | 10 +++++-----
>  29 files changed, 44 insertions(+), 42 deletions(-)
> 
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 66109bcca35..8efea289e7e 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -86,7 +86,6 @@ struct AccelCPUClass;
>   * instantiatable CPU type.
>   * @parse_features: Callback to parse command line arguments.
>   * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
> - * @has_work: Callback for checking if there is work to do.
>   * @virtio_is_big_endian: Callback to return %true if a CPU which supports
>   * runtime configurable endianness is currently big-endian. Non-configurable
>   * CPUs can use the default implementation of this method. This method should
> @@ -149,7 +148,6 @@ struct CPUClass {
>      void (*parse_features)(const char *typename, char *str, Error **errp);
>  
>      int reset_dump_flags;
> -    bool (*has_work)(CPUState *cpu);
>      bool (*virtio_is_big_endian)(CPUState *cpu);
>      int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
>                             uint8_t *buf, int len, bool is_write);
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 72d791438c2..f5d44ba59f3 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -19,6 +19,10 @@ struct TCGCPUOps {
>       * Called when the first CPU is realized.
>       */
>      void (*initialize)(void);
> +    /**
> +     * @has_work: Callback for checking if there is work to do
> +     */
> +    bool (*has_work)(CPUState *cpu);
>      /**
>       * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
>       *
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index b9ce36e59e2..4e73550f981 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -451,7 +451,11 @@ bool cpu_has_work(CPUState *cpu)
>  {
>      CPUClass *cc = CPU_GET_CLASS(cpu);
>  
> -    return cc->has_work(cpu);
> +    if (cc->tcg_ops->has_work) {
> +        return cc->tcg_ops->has_work(cpu);
> +    }
> +
> +    return false;
>  }
>  
>  static inline bool cpu_handle_halt(CPUState *cpu)
> diff --git a/hw/core/cpu.c b/hw/core/cpu.c
> index 00330ba07de..3110867c3a3 100644
> --- a/hw/core/cpu.c
> +++ b/hw/core/cpu.c
> @@ -261,11 +261,6 @@ static void cpu_common_reset(DeviceState *dev)
>      }
>  }
>  
> -static bool cpu_common_has_work(CPUState *cs)
> -{
> -    return false;
> -}
> -
>  ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
>  {
>      CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
> @@ -397,7 +392,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
>  
>      k->parse_features = cpu_common_parse_features;
>      k->get_arch_id = cpu_common_get_arch_id;
> -    k->has_work = cpu_common_has_work;
>      k->get_paging_enabled = cpu_common_get_paging_enabled;
>      k->get_memory_mapping = cpu_common_get_memory_mapping;
>      k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
> diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
> index e50ae7bef06..57e88bbe7fd 100644
> --- a/target/alpha/cpu.c
> +++ b/target/alpha/cpu.c
> @@ -210,6 +210,7 @@ static void alpha_cpu_initfn(Object *obj)
>  
>  static const struct TCGCPUOps alpha_tcg_ops = {
>      .initialize = alpha_translate_init,
> +    .has_work = alpha_cpu_has_work,
>      .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
>      .tlb_fill = alpha_cpu_tlb_fill,
>  
> @@ -230,7 +231,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
>                                      &acc->parent_realize);
>  
>      cc->class_by_name = alpha_cpu_class_by_name;
> -    cc->has_work = alpha_cpu_has_work;
>      cc->dump_state = alpha_cpu_dump_state;
>      cc->set_pc = alpha_cpu_set_pc;
>      cc->gdb_read_register = alpha_cpu_gdb_read_register;
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 6d2d9f2100f..7181deee84a 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2263,6 +2263,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
>  #ifdef CONFIG_TCG
>  static const struct TCGCPUOps arm_tcg_ops = {
>      .initialize = arm_translate_init,
> +    .has_work = arm_cpu_has_work,
>      .synchronize_from_tb = arm_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = arm_cpu_exec_interrupt,
>      .tlb_fill = arm_cpu_tlb_fill,
> @@ -2291,7 +2292,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
>  
>      cc->class_by_name = arm_cpu_class_by_name;
> -    cc->has_work = arm_cpu_has_work;
>      cc->dump_state = arm_cpu_dump_state;
>      cc->set_pc = arm_cpu_set_pc;
>      cc->gdb_read_register = arm_cpu_gdb_read_register;
> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
> index 7d0ab606ae1..7416aa805d0 100644
> --- a/target/avr/cpu.c
> +++ b/target/avr/cpu.c
> @@ -188,6 +188,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>  
>  static const struct TCGCPUOps avr_tcg_ops = {
>      .initialize = avr_cpu_tcg_init,
> +    .has_work = avr_cpu_has_work,
>      .synchronize_from_tb = avr_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = avr_cpu_exec_interrupt,
>      .tlb_fill = avr_cpu_tlb_fill,
> @@ -208,7 +209,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
>  
>      cc->class_by_name = avr_cpu_class_by_name;
>  
> -    cc->has_work = avr_cpu_has_work;
>      cc->dump_state = avr_cpu_dump_state;
>      cc->set_pc = avr_cpu_set_pc;
>      cc->memory_rw_debug = avr_cpu_memory_rw_debug;
> diff --git a/target/cris/cpu.c b/target/cris/cpu.c
> index 4586302ba39..eef76a211f1 100644
> --- a/target/cris/cpu.c
> +++ b/target/cris/cpu.c
> @@ -197,6 +197,7 @@ static void cris_cpu_initfn(Object *obj)
>  
>  static const struct TCGCPUOps crisv10_tcg_ops = {
>      .initialize = cris_initialize_crisv10_tcg,
> +    .has_work = cris_cpu_has_work,
>      .cpu_exec_interrupt = cris_cpu_exec_interrupt,
>      .tlb_fill = cris_cpu_tlb_fill,
>  
> @@ -207,6 +208,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = {
>  
>  static const struct TCGCPUOps crisv32_tcg_ops = {
>      .initialize = cris_initialize_tcg,
> +    .has_work = cris_cpu_has_work,
>      .cpu_exec_interrupt = cris_cpu_exec_interrupt,
>      .tlb_fill = cris_cpu_tlb_fill,
>  
> @@ -286,7 +288,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset);
>  
>      cc->class_by_name = cris_cpu_class_by_name;
> -    cc->has_work = cris_cpu_has_work;
>      cc->dump_state = cris_cpu_dump_state;
>      cc->set_pc = cris_cpu_set_pc;
>      cc->gdb_read_register = cris_cpu_gdb_read_register;
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
> index a13a941ed5b..cda63537d32 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -268,6 +268,7 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
>  
>  static const struct TCGCPUOps hexagon_tcg_ops = {
>      .initialize = hexagon_translate_init,
> +    .has_work = hexagon_cpu_has_work,
>      .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
>      .tlb_fill = hexagon_tlb_fill,
>  };
> @@ -284,7 +285,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
>      device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset);
>  
>      cc->class_by_name = hexagon_cpu_class_by_name;
> -    cc->has_work = hexagon_cpu_has_work;
>      cc->dump_state = hexagon_dump_state;
>      cc->set_pc = hexagon_cpu_set_pc;
>      cc->gdb_read_register = hexagon_gdb_read_register;
> diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
> index 5f1822b5fe6..b9437f4c534 100644
> --- a/target/hppa/cpu.c
> +++ b/target/hppa/cpu.c
> @@ -135,6 +135,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
>  
>  static const struct TCGCPUOps hppa_tcg_ops = {
>      .initialize = hppa_translate_init,
> +    .has_work = hppa_cpu_has_work,
>      .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
>      .tlb_fill = hppa_cpu_tlb_fill,
> @@ -155,7 +156,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
>                                      &acc->parent_realize);
>  
>      cc->class_by_name = hppa_cpu_class_by_name;
> -    cc->has_work = hppa_cpu_has_work;
>      cc->dump_state = hppa_cpu_dump_state;
>      cc->set_pc = hppa_cpu_set_pc;
>      cc->gdb_read_register = hppa_cpu_gdb_read_register;
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 50008431c35..464e136a072 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -7171,6 +7171,7 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
>      cpu->env.eip = value;
>  }
>  
> +/* FIXME TCG only? */
>  int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
>  {
>      X86CPU *cpu = X86_CPU(cs);
> @@ -7213,11 +7214,6 @@ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
>      return 0;
>  }
>  
> -static bool x86_cpu_has_work(CPUState *cs)
> -{
> -    return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
> -}
> -
>  static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
>  {
>      X86CPU *cpu = X86_CPU(cs);
> @@ -7404,7 +7400,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
>  
>      cc->class_by_name = x86_cpu_class_by_name;
>      cc->parse_features = x86_cpu_parse_featurestr;
> -    cc->has_work = x86_cpu_has_work;
>  
>  #ifdef CONFIG_TCG
>      tcg_cpu_common_class_init(cc);
> diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
> index 6a35aa664dc..fee8487135d 100644
> --- a/target/i386/tcg/tcg-cpu.c
> +++ b/target/i386/tcg/tcg-cpu.c
> @@ -57,10 +57,16 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
>      cpu->env.eip = tb->pc - tb->cs_base;
>  }
>  
> +static bool x86_cpu_has_work(CPUState *cs)
> +{
> +    return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
> +}
> +
>  #include "hw/core/tcg-cpu-ops.h"
>  
>  static const struct TCGCPUOps x86_tcg_ops = {
>      .initialize = tcg_x86_init,
> +    .has_work = x86_cpu_has_work,
>      .synchronize_from_tb = x86_cpu_synchronize_from_tb,
>      .cpu_exec_enter = x86_cpu_exec_enter,
>      .cpu_exec_exit = x86_cpu_exec_exit,
> diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
> index 4ad253a50ec..5d18255ac83 100644
> --- a/target/lm32/cpu.c
> +++ b/target/lm32/cpu.c
> @@ -214,6 +214,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
>  
>  static const struct TCGCPUOps lm32_tcg_ops = {
>      .initialize = lm32_translate_init,
> +    .has_work = lm32_cpu_has_work,
>      .cpu_exec_interrupt = lm32_cpu_exec_interrupt,
>      .tlb_fill = lm32_cpu_tlb_fill,
>      .debug_excp_handler = lm32_debug_excp_handler,
> @@ -234,7 +235,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset);
>  
>      cc->class_by_name = lm32_cpu_class_by_name;
> -    cc->has_work = lm32_cpu_has_work;
>      cc->dump_state = lm32_cpu_dump_state;
>      cc->set_pc = lm32_cpu_set_pc;
>      cc->gdb_read_register = lm32_cpu_gdb_read_register;
> diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
> index 9b2f651213b..9c38138215f 100644
> --- a/target/m68k/cpu.c
> +++ b/target/m68k/cpu.c
> @@ -506,6 +506,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
>  
>  static const struct TCGCPUOps m68k_tcg_ops = {
>      .initialize = m68k_tcg_init,
> +    .has_work = m68k_cpu_has_work,
>      .cpu_exec_interrupt = m68k_cpu_exec_interrupt,
>      .tlb_fill = m68k_cpu_tlb_fill,
>  
> @@ -526,7 +527,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
>      device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset);
>  
>      cc->class_by_name = m68k_cpu_class_by_name;
> -    cc->has_work = m68k_cpu_has_work;
>      cc->dump_state = m68k_cpu_dump_state;
>      cc->set_pc = m68k_cpu_set_pc;
>      cc->gdb_read_register = m68k_cpu_gdb_read_register;
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 4e086ab5465..809f42b5e0d 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -356,6 +356,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
>  
>  static const struct TCGCPUOps mb_tcg_ops = {
>      .initialize = mb_tcg_init,
> +    .has_work = mb_cpu_has_work,
>      .synchronize_from_tb = mb_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = mb_cpu_exec_interrupt,
>      .tlb_fill = mb_cpu_tlb_fill,
> @@ -378,7 +379,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
>  
>      cc->class_by_name = mb_cpu_class_by_name;
> -    cc->has_work = mb_cpu_has_work;
>  
>      cc->dump_state = mb_cpu_dump_state;
>      cc->set_pc = mb_cpu_set_pc;
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index 81030c5c407..a189710904a 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -688,6 +688,7 @@ static Property mips_cpu_properties[] = {
>   */
>  static const struct TCGCPUOps mips_tcg_ops = {
>      .initialize = mips_tcg_init,
> +    .has_work = mips_cpu_has_work,
>      .synchronize_from_tb = mips_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = mips_cpu_exec_interrupt,
>      .tlb_fill = mips_cpu_tlb_fill,
> @@ -713,7 +714,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>      device_class_set_props(dc, mips_cpu_properties);
>  
>      cc->class_by_name = mips_cpu_class_by_name;
> -    cc->has_work = mips_cpu_has_work;
>      cc->dump_state = mips_cpu_dump_state;
>      cc->set_pc = mips_cpu_set_pc;
>      cc->gdb_read_register = mips_cpu_gdb_read_register;
> diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
> index c3de71b82fe..942804de21b 100644
> --- a/target/moxie/cpu.c
> +++ b/target/moxie/cpu.c
> @@ -98,6 +98,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
>  
>  static const struct TCGCPUOps moxie_tcg_ops = {
>      .initialize = moxie_translate_init,
> +    .has_work = moxie_cpu_has_work,
>      .tlb_fill = moxie_cpu_tlb_fill,
>  
>  #ifndef CONFIG_USER_ONLY
> @@ -117,7 +118,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
>  
>      cc->class_by_name = moxie_cpu_class_by_name;
>  
> -    cc->has_work = moxie_cpu_has_work;
>      cc->dump_state = moxie_cpu_dump_state;
>      cc->set_pc = moxie_cpu_set_pc;
>  #ifndef CONFIG_USER_ONLY
> diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
> index 0de93cdd98f..cfd9f002436 100644
> --- a/target/nios2/cpu.c
> +++ b/target/nios2/cpu.c
> @@ -211,6 +211,7 @@ static Property nios2_properties[] = {
>  
>  static const struct TCGCPUOps nios2_tcg_ops = {
>      .initialize = nios2_tcg_init,
> +    .has_work = nios2_cpu_has_work,
>      .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
>      .tlb_fill = nios2_cpu_tlb_fill,
>  
> @@ -232,7 +233,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset);
>  
>      cc->class_by_name = nios2_cpu_class_by_name;
> -    cc->has_work = nios2_cpu_has_work;
>      cc->dump_state = nios2_cpu_dump_state;
>      cc->set_pc = nios2_cpu_set_pc;
>      cc->disas_set_info = nios2_cpu_disas_set_info;
> diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
> index 52aef277232..674e1ac0d23 100644
> --- a/target/openrisc/cpu.c
> +++ b/target/openrisc/cpu.c
> @@ -178,6 +178,7 @@ static void openrisc_any_initfn(Object *obj)
>  
>  static const struct TCGCPUOps openrisc_tcg_ops = {
>      .initialize = openrisc_translate_init,
> +    .has_work = openrisc_cpu_has_work,
>      .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
>      .tlb_fill = openrisc_cpu_tlb_fill,
>  
> @@ -197,7 +198,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset);
>  
>      cc->class_by_name = openrisc_cpu_class_by_name;
> -    cc->has_work = openrisc_cpu_has_work;
>      cc->dump_state = openrisc_cpu_dump_state;
>      cc->set_pc = openrisc_cpu_set_pc;
>      cc->gdb_read_register = openrisc_cpu_gdb_read_register;
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6f9822bc0a1..a5de166bb3f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -584,6 +584,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
>  
>  static const struct TCGCPUOps riscv_tcg_ops = {
>      .initialize = riscv_translate_init,
> +    .has_work = riscv_cpu_has_work,
>      .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
>      .tlb_fill = riscv_cpu_tlb_fill,
> @@ -607,7 +608,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
>      device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
>  
>      cc->class_by_name = riscv_cpu_class_by_name;
> -    cc->has_work = riscv_cpu_has_work;
>      cc->dump_state = riscv_cpu_dump_state;
>      cc->set_pc = riscv_cpu_set_pc;
>      cc->gdb_read_register = riscv_cpu_gdb_read_register;
> diff --git a/target/rx/cpu.c b/target/rx/cpu.c
> index 28d2becc32c..f5f967ff509 100644
> --- a/target/rx/cpu.c
> +++ b/target/rx/cpu.c
> @@ -177,6 +177,7 @@ static void rx_cpu_init(Object *obj)
>  
>  static const struct TCGCPUOps rx_tcg_ops = {
>      .initialize = rx_translate_init,
> +    .has_work = rx_cpu_has_work,
>      .synchronize_from_tb = rx_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = rx_cpu_exec_interrupt,
>      .tlb_fill = rx_cpu_tlb_fill,
> @@ -198,7 +199,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
>                                    &rcc->parent_reset);
>  
>      cc->class_by_name = rx_cpu_class_by_name;
> -    cc->has_work = rx_cpu_has_work;
>      cc->dump_state = rx_cpu_dump_state;
>      cc->set_pc = rx_cpu_set_pc;
>  
> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
> index d57f69e7f7d..d2f897bf41a 100644
> --- a/target/s390x/cpu.c
> +++ b/target/s390x/cpu.c
> @@ -465,6 +465,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
>  
>  static const struct TCGCPUOps s390_tcg_ops = {
>      .initialize = s390x_translate_init,
> +    .has_work = s390_cpu_has_work,
>      .tlb_fill = s390_cpu_tlb_fill,
>  
>  #if !defined(CONFIG_USER_ONLY)
> @@ -493,7 +494,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
>  #endif
>      scc->reset = s390_cpu_reset;
>      cc->class_by_name = s390_cpu_class_by_name,
> -    cc->has_work = s390_cpu_has_work;
>      cc->dump_state = s390_cpu_dump_state;
>      cc->set_pc = s390_cpu_set_pc;
>      cc->gdb_read_register = s390_cpu_gdb_read_register;
> diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
> index 9d77f9cfdae..8bac001bfa4 100644
> --- a/target/sh4/cpu.c
> +++ b/target/sh4/cpu.c
> @@ -227,6 +227,7 @@ static const VMStateDescription vmstate_sh_cpu = {
>  
>  static const struct TCGCPUOps superh_tcg_ops = {
>      .initialize = sh4_translate_init,
> +    .has_work = superh_cpu_has_work,
>      .synchronize_from_tb = superh_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = superh_cpu_exec_interrupt,
>      .tlb_fill = superh_cpu_tlb_fill,
> @@ -250,7 +251,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset);
>  
>      cc->class_by_name = superh_cpu_class_by_name;
> -    cc->has_work = superh_cpu_has_work;
>      cc->dump_state = superh_cpu_dump_state;
>      cc->set_pc = superh_cpu_set_pc;
>      cc->gdb_read_register = superh_cpu_gdb_read_register;
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index ccabe189c4a..761813ce96b 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -853,6 +853,7 @@ static Property sparc_cpu_properties[] = {
>  
>  static const struct TCGCPUOps sparc_tcg_ops = {
>      .initialize = sparc_tcg_init,
> +    .has_work = sparc_cpu_has_work,
>      .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
>      .tlb_fill = sparc_cpu_tlb_fill,
> @@ -879,7 +880,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
>  
>      cc->class_by_name = sparc_cpu_class_by_name;
>      cc->parse_features = sparc_cpu_parse_features;
> -    cc->has_work = sparc_cpu_has_work;
>      cc->dump_state = sparc_cpu_dump_state;
>  #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
>      cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
> diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
> index c7f8a898caf..3bc89e736b3 100644
> --- a/target/tilegx/cpu.c
> +++ b/target/tilegx/cpu.c
> @@ -138,6 +138,7 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>  
>  static const struct TCGCPUOps tilegx_tcg_ops = {
>      .initialize = tilegx_tcg_init,
> +    .has_work = tilegx_cpu_has_work,
>      .cpu_exec_interrupt = tilegx_cpu_exec_interrupt,
>      .tlb_fill = tilegx_cpu_tlb_fill,
>  
> @@ -158,7 +159,6 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, tilegx_cpu_reset, &tcc->parent_reset);
>  
>      cc->class_by_name = tilegx_cpu_class_by_name;
> -    cc->has_work = tilegx_cpu_has_work;
>      cc->dump_state = tilegx_cpu_dump_state;
>      cc->set_pc = tilegx_cpu_set_pc;
>      cc->gdb_num_core_regs = 0;
> diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
> index 5b500b575bd..b493e3ede85 100644
> --- a/target/tricore/cpu.c
> +++ b/target/tricore/cpu.c
> @@ -146,6 +146,7 @@ static void tc27x_initfn(Object *obj)
>  
>  static const struct TCGCPUOps tricore_tcg_ops = {
>      .initialize = tricore_tcg_init,
> +    .has_work = tricore_cpu_has_work,
>      .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
>      .tlb_fill = tricore_cpu_tlb_fill,
>  };
> @@ -161,7 +162,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
>  
>      device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset);
>      cc->class_by_name = tricore_cpu_class_by_name;
> -    cc->has_work = tricore_cpu_has_work;
>  
>      cc->gdb_read_register = tricore_cpu_gdb_read_register;
>      cc->gdb_write_register = tricore_cpu_gdb_write_register;
> diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
> index a732b08748d..55569018296 100644
> --- a/target/unicore32/cpu.c
> +++ b/target/unicore32/cpu.c
> @@ -124,6 +124,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
>  
>  static const struct TCGCPUOps uc32_tcg_ops = {
>      .initialize = uc32_translate_init,
> +    .has_work = uc32_cpu_has_work,
>      .cpu_exec_interrupt = uc32_cpu_exec_interrupt,
>      .tlb_fill = uc32_cpu_tlb_fill,
>  
> @@ -142,7 +143,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
>                                      &ucc->parent_realize);
>  
>      cc->class_by_name = uc32_cpu_class_by_name;
> -    cc->has_work = uc32_cpu_has_work;
>      cc->dump_state = uc32_cpu_dump_state;
>      cc->set_pc = uc32_cpu_set_pc;
>      cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
> diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
> index badc3a26aa2..849a664a679 100644
> --- a/target/xtensa/cpu.c
> +++ b/target/xtensa/cpu.c
> @@ -185,6 +185,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
>  
>  static const struct TCGCPUOps xtensa_tcg_ops = {
>      .initialize = xtensa_translate_init,
> +    .has_work = xtensa_cpu_has_work,
>      .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
>      .tlb_fill = xtensa_cpu_tlb_fill,
>      .debug_excp_handler = xtensa_breakpoint_handler,
> @@ -208,7 +209,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
>  
>      cc->class_by_name = xtensa_cpu_class_by_name;
> -    cc->has_work = xtensa_cpu_has_work;
>      cc->dump_state = xtensa_cpu_dump_state;
>      cc->set_pc = xtensa_cpu_set_pc;
>      cc->gdb_read_register = xtensa_cpu_gdb_read_register;
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index fe76d0b3773..1558de804c9 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -8633,7 +8633,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
>      pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
>      pcc->init_proc = init_proc_POWER7;
>      pcc->check_pow = check_pow_nocheck;
> -    cc->has_work = cpu_has_work_POWER7;
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
>                         PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
>                         PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -8806,7 +8805,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>      pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
>      pcc->init_proc = init_proc_POWER8;
>      pcc->check_pow = check_pow_nocheck;
> -    cc->has_work = cpu_has_work_POWER8;
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
>                         PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
>                         PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -9026,7 +9024,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
>                           PCR_COMPAT_2_05;
>      pcc->init_proc = init_proc_POWER9;
>      pcc->check_pow = check_pow_nocheck;
> -    cc->has_work = cpu_has_work_POWER9;
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
>                         PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
>                         PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -9241,7 +9238,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
>                           PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
>      pcc->init_proc = init_proc_POWER10;
>      pcc->check_pow = check_pow_nocheck;
> -    cc->has_work = cpu_has_work_POWER10;
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
>                         PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
>                         PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -10865,6 +10861,7 @@ static Property ppc_cpu_properties[] = {
>  
>  static const struct TCGCPUOps ppc_tcg_ops = {
>    .initialize = ppc_translate_init,
> +  .has_work = ppc_cpu_has_work,
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> @@ -10878,6 +10875,7 @@ static const struct TCGCPUOps ppc_tcg_ops = {
>  
>  static const struct TCGCPUOps power7_tcg_ops = {
>    .initialize = ppc_translate_init,
> +  .has_work = cpu_has_work_POWER7,
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> @@ -10891,6 +10889,7 @@ static const struct TCGCPUOps power7_tcg_ops = {
>  
>  static const struct TCGCPUOps power8_tcg_ops = {
>    .initialize = ppc_translate_init,
> +  .has_work = cpu_has_work_POWER8,
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> @@ -10904,6 +10903,7 @@ static const struct TCGCPUOps power8_tcg_ops = {
>  
>  static const struct TCGCPUOps power9_tcg_ops = {
>    .initialize = ppc_translate_init,
> +  .has_work = cpu_has_work_POWER9,
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> @@ -10917,6 +10917,7 @@ static const struct TCGCPUOps power9_tcg_ops = {
>  
>  static const struct TCGCPUOps power10_tcg_ops = {
>    .initialize = ppc_translate_init,
> +  .has_work = cpu_has_work_POWER10,
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> @@ -10946,7 +10947,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
>  
>      cc->class_by_name = ppc_cpu_class_by_name;
> -    cc->has_work = ppc_cpu_has_work;
>      cc->dump_state = ppc_cpu_dump_state;
>      cc->dump_statistics = ppc_cpu_dump_statistics;
>      cc->set_pc = ppc_cpu_set_pc;

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 7/8] cpu: Move CPUClass::has_work() to TCGCPUOps
@ 2021-03-05  1:05     ` David Gibson
  0 siblings, 0 replies; 35+ messages in thread
From: David Gibson @ 2021-03-05  1:05 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé
  Cc: qemu-devel, David Hildenbrand, qemu-ppc, qemu-s390x, Thomas Huth,
	Laurent Vivier, Cornelia Huck, Greg Kurz, Paolo Bonzini,
	qemu-arm, Eduardo Habkost, Peter Maydell, Richard Henderson,
	qemu-riscv, Claudio Fontana, Taylor Simpson, Marcel Apfelbaum,
	Michael Rolnik, Sarah Harris, Edgar E. Iglesias, Michael Walle,
	Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, Anthony Green,
	Chris Wulff, Marek Vasut, Stafford Horne, Palmer Dabbelt,
	Alistair Francis, Sagar Karandikar, Bastian Koppelmann,
	Yoshinori Sato, Mark Cave-Ayland, Artyom Tarasenko, Guan Xuetao,
	Max Filippov

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On Thu, Mar 04, 2021 at 11:23:22PM +0100, Philippe Mathieu-Daudé wrote:
> We can only check if a vCPU has work with TCG.
> Restrict the has_work() handler to TCG by moving it to
> the TCGCPUOps structure, and adapt all the targets.
> 
> cpu_common_has_work() is removed as being inlined in
> cpu_has_work().
> 
> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

ppc parts
Acked-by: David Gibson <david@gibson.dropbear.id.au>

> ---
> v2:
> - finished PPC
> - check cc->tcg_ops->has_work non-null (thuth)
> ---
>  include/hw/core/cpu.h           |  2 --
>  include/hw/core/tcg-cpu-ops.h   |  4 ++++
>  accel/tcg/cpu-exec.c            |  6 +++++-
>  hw/core/cpu.c                   |  6 ------
>  target/alpha/cpu.c              |  2 +-
>  target/arm/cpu.c                |  2 +-
>  target/avr/cpu.c                |  2 +-
>  target/cris/cpu.c               |  3 ++-
>  target/hexagon/cpu.c            |  2 +-
>  target/hppa/cpu.c               |  2 +-
>  target/i386/cpu.c               |  7 +------
>  target/i386/tcg/tcg-cpu.c       |  6 ++++++
>  target/lm32/cpu.c               |  2 +-
>  target/m68k/cpu.c               |  2 +-
>  target/microblaze/cpu.c         |  2 +-
>  target/mips/cpu.c               |  2 +-
>  target/moxie/cpu.c              |  2 +-
>  target/nios2/cpu.c              |  2 +-
>  target/openrisc/cpu.c           |  2 +-
>  target/riscv/cpu.c              |  2 +-
>  target/rx/cpu.c                 |  2 +-
>  target/s390x/cpu.c              |  2 +-
>  target/sh4/cpu.c                |  2 +-
>  target/sparc/cpu.c              |  2 +-
>  target/tilegx/cpu.c             |  2 +-
>  target/tricore/cpu.c            |  2 +-
>  target/unicore32/cpu.c          |  2 +-
>  target/xtensa/cpu.c             |  2 +-
>  target/ppc/translate_init.c.inc | 10 +++++-----
>  29 files changed, 44 insertions(+), 42 deletions(-)
> 
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 66109bcca35..8efea289e7e 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -86,7 +86,6 @@ struct AccelCPUClass;
>   * instantiatable CPU type.
>   * @parse_features: Callback to parse command line arguments.
>   * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
> - * @has_work: Callback for checking if there is work to do.
>   * @virtio_is_big_endian: Callback to return %true if a CPU which supports
>   * runtime configurable endianness is currently big-endian. Non-configurable
>   * CPUs can use the default implementation of this method. This method should
> @@ -149,7 +148,6 @@ struct CPUClass {
>      void (*parse_features)(const char *typename, char *str, Error **errp);
>  
>      int reset_dump_flags;
> -    bool (*has_work)(CPUState *cpu);
>      bool (*virtio_is_big_endian)(CPUState *cpu);
>      int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
>                             uint8_t *buf, int len, bool is_write);
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 72d791438c2..f5d44ba59f3 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -19,6 +19,10 @@ struct TCGCPUOps {
>       * Called when the first CPU is realized.
>       */
>      void (*initialize)(void);
> +    /**
> +     * @has_work: Callback for checking if there is work to do
> +     */
> +    bool (*has_work)(CPUState *cpu);
>      /**
>       * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
>       *
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index b9ce36e59e2..4e73550f981 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -451,7 +451,11 @@ bool cpu_has_work(CPUState *cpu)
>  {
>      CPUClass *cc = CPU_GET_CLASS(cpu);
>  
> -    return cc->has_work(cpu);
> +    if (cc->tcg_ops->has_work) {
> +        return cc->tcg_ops->has_work(cpu);
> +    }
> +
> +    return false;
>  }
>  
>  static inline bool cpu_handle_halt(CPUState *cpu)
> diff --git a/hw/core/cpu.c b/hw/core/cpu.c
> index 00330ba07de..3110867c3a3 100644
> --- a/hw/core/cpu.c
> +++ b/hw/core/cpu.c
> @@ -261,11 +261,6 @@ static void cpu_common_reset(DeviceState *dev)
>      }
>  }
>  
> -static bool cpu_common_has_work(CPUState *cs)
> -{
> -    return false;
> -}
> -
>  ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
>  {
>      CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
> @@ -397,7 +392,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
>  
>      k->parse_features = cpu_common_parse_features;
>      k->get_arch_id = cpu_common_get_arch_id;
> -    k->has_work = cpu_common_has_work;
>      k->get_paging_enabled = cpu_common_get_paging_enabled;
>      k->get_memory_mapping = cpu_common_get_memory_mapping;
>      k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
> diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
> index e50ae7bef06..57e88bbe7fd 100644
> --- a/target/alpha/cpu.c
> +++ b/target/alpha/cpu.c
> @@ -210,6 +210,7 @@ static void alpha_cpu_initfn(Object *obj)
>  
>  static const struct TCGCPUOps alpha_tcg_ops = {
>      .initialize = alpha_translate_init,
> +    .has_work = alpha_cpu_has_work,
>      .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
>      .tlb_fill = alpha_cpu_tlb_fill,
>  
> @@ -230,7 +231,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
>                                      &acc->parent_realize);
>  
>      cc->class_by_name = alpha_cpu_class_by_name;
> -    cc->has_work = alpha_cpu_has_work;
>      cc->dump_state = alpha_cpu_dump_state;
>      cc->set_pc = alpha_cpu_set_pc;
>      cc->gdb_read_register = alpha_cpu_gdb_read_register;
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 6d2d9f2100f..7181deee84a 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2263,6 +2263,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
>  #ifdef CONFIG_TCG
>  static const struct TCGCPUOps arm_tcg_ops = {
>      .initialize = arm_translate_init,
> +    .has_work = arm_cpu_has_work,
>      .synchronize_from_tb = arm_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = arm_cpu_exec_interrupt,
>      .tlb_fill = arm_cpu_tlb_fill,
> @@ -2291,7 +2292,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
>  
>      cc->class_by_name = arm_cpu_class_by_name;
> -    cc->has_work = arm_cpu_has_work;
>      cc->dump_state = arm_cpu_dump_state;
>      cc->set_pc = arm_cpu_set_pc;
>      cc->gdb_read_register = arm_cpu_gdb_read_register;
> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
> index 7d0ab606ae1..7416aa805d0 100644
> --- a/target/avr/cpu.c
> +++ b/target/avr/cpu.c
> @@ -188,6 +188,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>  
>  static const struct TCGCPUOps avr_tcg_ops = {
>      .initialize = avr_cpu_tcg_init,
> +    .has_work = avr_cpu_has_work,
>      .synchronize_from_tb = avr_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = avr_cpu_exec_interrupt,
>      .tlb_fill = avr_cpu_tlb_fill,
> @@ -208,7 +209,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
>  
>      cc->class_by_name = avr_cpu_class_by_name;
>  
> -    cc->has_work = avr_cpu_has_work;
>      cc->dump_state = avr_cpu_dump_state;
>      cc->set_pc = avr_cpu_set_pc;
>      cc->memory_rw_debug = avr_cpu_memory_rw_debug;
> diff --git a/target/cris/cpu.c b/target/cris/cpu.c
> index 4586302ba39..eef76a211f1 100644
> --- a/target/cris/cpu.c
> +++ b/target/cris/cpu.c
> @@ -197,6 +197,7 @@ static void cris_cpu_initfn(Object *obj)
>  
>  static const struct TCGCPUOps crisv10_tcg_ops = {
>      .initialize = cris_initialize_crisv10_tcg,
> +    .has_work = cris_cpu_has_work,
>      .cpu_exec_interrupt = cris_cpu_exec_interrupt,
>      .tlb_fill = cris_cpu_tlb_fill,
>  
> @@ -207,6 +208,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = {
>  
>  static const struct TCGCPUOps crisv32_tcg_ops = {
>      .initialize = cris_initialize_tcg,
> +    .has_work = cris_cpu_has_work,
>      .cpu_exec_interrupt = cris_cpu_exec_interrupt,
>      .tlb_fill = cris_cpu_tlb_fill,
>  
> @@ -286,7 +288,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset);
>  
>      cc->class_by_name = cris_cpu_class_by_name;
> -    cc->has_work = cris_cpu_has_work;
>      cc->dump_state = cris_cpu_dump_state;
>      cc->set_pc = cris_cpu_set_pc;
>      cc->gdb_read_register = cris_cpu_gdb_read_register;
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
> index a13a941ed5b..cda63537d32 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -268,6 +268,7 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
>  
>  static const struct TCGCPUOps hexagon_tcg_ops = {
>      .initialize = hexagon_translate_init,
> +    .has_work = hexagon_cpu_has_work,
>      .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
>      .tlb_fill = hexagon_tlb_fill,
>  };
> @@ -284,7 +285,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
>      device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset);
>  
>      cc->class_by_name = hexagon_cpu_class_by_name;
> -    cc->has_work = hexagon_cpu_has_work;
>      cc->dump_state = hexagon_dump_state;
>      cc->set_pc = hexagon_cpu_set_pc;
>      cc->gdb_read_register = hexagon_gdb_read_register;
> diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
> index 5f1822b5fe6..b9437f4c534 100644
> --- a/target/hppa/cpu.c
> +++ b/target/hppa/cpu.c
> @@ -135,6 +135,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
>  
>  static const struct TCGCPUOps hppa_tcg_ops = {
>      .initialize = hppa_translate_init,
> +    .has_work = hppa_cpu_has_work,
>      .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
>      .tlb_fill = hppa_cpu_tlb_fill,
> @@ -155,7 +156,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
>                                      &acc->parent_realize);
>  
>      cc->class_by_name = hppa_cpu_class_by_name;
> -    cc->has_work = hppa_cpu_has_work;
>      cc->dump_state = hppa_cpu_dump_state;
>      cc->set_pc = hppa_cpu_set_pc;
>      cc->gdb_read_register = hppa_cpu_gdb_read_register;
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 50008431c35..464e136a072 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -7171,6 +7171,7 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
>      cpu->env.eip = value;
>  }
>  
> +/* FIXME TCG only? */
>  int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
>  {
>      X86CPU *cpu = X86_CPU(cs);
> @@ -7213,11 +7214,6 @@ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
>      return 0;
>  }
>  
> -static bool x86_cpu_has_work(CPUState *cs)
> -{
> -    return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
> -}
> -
>  static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
>  {
>      X86CPU *cpu = X86_CPU(cs);
> @@ -7404,7 +7400,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
>  
>      cc->class_by_name = x86_cpu_class_by_name;
>      cc->parse_features = x86_cpu_parse_featurestr;
> -    cc->has_work = x86_cpu_has_work;
>  
>  #ifdef CONFIG_TCG
>      tcg_cpu_common_class_init(cc);
> diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
> index 6a35aa664dc..fee8487135d 100644
> --- a/target/i386/tcg/tcg-cpu.c
> +++ b/target/i386/tcg/tcg-cpu.c
> @@ -57,10 +57,16 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
>      cpu->env.eip = tb->pc - tb->cs_base;
>  }
>  
> +static bool x86_cpu_has_work(CPUState *cs)
> +{
> +    return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
> +}
> +
>  #include "hw/core/tcg-cpu-ops.h"
>  
>  static const struct TCGCPUOps x86_tcg_ops = {
>      .initialize = tcg_x86_init,
> +    .has_work = x86_cpu_has_work,
>      .synchronize_from_tb = x86_cpu_synchronize_from_tb,
>      .cpu_exec_enter = x86_cpu_exec_enter,
>      .cpu_exec_exit = x86_cpu_exec_exit,
> diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
> index 4ad253a50ec..5d18255ac83 100644
> --- a/target/lm32/cpu.c
> +++ b/target/lm32/cpu.c
> @@ -214,6 +214,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
>  
>  static const struct TCGCPUOps lm32_tcg_ops = {
>      .initialize = lm32_translate_init,
> +    .has_work = lm32_cpu_has_work,
>      .cpu_exec_interrupt = lm32_cpu_exec_interrupt,
>      .tlb_fill = lm32_cpu_tlb_fill,
>      .debug_excp_handler = lm32_debug_excp_handler,
> @@ -234,7 +235,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset);
>  
>      cc->class_by_name = lm32_cpu_class_by_name;
> -    cc->has_work = lm32_cpu_has_work;
>      cc->dump_state = lm32_cpu_dump_state;
>      cc->set_pc = lm32_cpu_set_pc;
>      cc->gdb_read_register = lm32_cpu_gdb_read_register;
> diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
> index 9b2f651213b..9c38138215f 100644
> --- a/target/m68k/cpu.c
> +++ b/target/m68k/cpu.c
> @@ -506,6 +506,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
>  
>  static const struct TCGCPUOps m68k_tcg_ops = {
>      .initialize = m68k_tcg_init,
> +    .has_work = m68k_cpu_has_work,
>      .cpu_exec_interrupt = m68k_cpu_exec_interrupt,
>      .tlb_fill = m68k_cpu_tlb_fill,
>  
> @@ -526,7 +527,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
>      device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset);
>  
>      cc->class_by_name = m68k_cpu_class_by_name;
> -    cc->has_work = m68k_cpu_has_work;
>      cc->dump_state = m68k_cpu_dump_state;
>      cc->set_pc = m68k_cpu_set_pc;
>      cc->gdb_read_register = m68k_cpu_gdb_read_register;
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 4e086ab5465..809f42b5e0d 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -356,6 +356,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
>  
>  static const struct TCGCPUOps mb_tcg_ops = {
>      .initialize = mb_tcg_init,
> +    .has_work = mb_cpu_has_work,
>      .synchronize_from_tb = mb_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = mb_cpu_exec_interrupt,
>      .tlb_fill = mb_cpu_tlb_fill,
> @@ -378,7 +379,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
>  
>      cc->class_by_name = mb_cpu_class_by_name;
> -    cc->has_work = mb_cpu_has_work;
>  
>      cc->dump_state = mb_cpu_dump_state;
>      cc->set_pc = mb_cpu_set_pc;
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index 81030c5c407..a189710904a 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -688,6 +688,7 @@ static Property mips_cpu_properties[] = {
>   */
>  static const struct TCGCPUOps mips_tcg_ops = {
>      .initialize = mips_tcg_init,
> +    .has_work = mips_cpu_has_work,
>      .synchronize_from_tb = mips_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = mips_cpu_exec_interrupt,
>      .tlb_fill = mips_cpu_tlb_fill,
> @@ -713,7 +714,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>      device_class_set_props(dc, mips_cpu_properties);
>  
>      cc->class_by_name = mips_cpu_class_by_name;
> -    cc->has_work = mips_cpu_has_work;
>      cc->dump_state = mips_cpu_dump_state;
>      cc->set_pc = mips_cpu_set_pc;
>      cc->gdb_read_register = mips_cpu_gdb_read_register;
> diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
> index c3de71b82fe..942804de21b 100644
> --- a/target/moxie/cpu.c
> +++ b/target/moxie/cpu.c
> @@ -98,6 +98,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
>  
>  static const struct TCGCPUOps moxie_tcg_ops = {
>      .initialize = moxie_translate_init,
> +    .has_work = moxie_cpu_has_work,
>      .tlb_fill = moxie_cpu_tlb_fill,
>  
>  #ifndef CONFIG_USER_ONLY
> @@ -117,7 +118,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
>  
>      cc->class_by_name = moxie_cpu_class_by_name;
>  
> -    cc->has_work = moxie_cpu_has_work;
>      cc->dump_state = moxie_cpu_dump_state;
>      cc->set_pc = moxie_cpu_set_pc;
>  #ifndef CONFIG_USER_ONLY
> diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
> index 0de93cdd98f..cfd9f002436 100644
> --- a/target/nios2/cpu.c
> +++ b/target/nios2/cpu.c
> @@ -211,6 +211,7 @@ static Property nios2_properties[] = {
>  
>  static const struct TCGCPUOps nios2_tcg_ops = {
>      .initialize = nios2_tcg_init,
> +    .has_work = nios2_cpu_has_work,
>      .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
>      .tlb_fill = nios2_cpu_tlb_fill,
>  
> @@ -232,7 +233,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset);
>  
>      cc->class_by_name = nios2_cpu_class_by_name;
> -    cc->has_work = nios2_cpu_has_work;
>      cc->dump_state = nios2_cpu_dump_state;
>      cc->set_pc = nios2_cpu_set_pc;
>      cc->disas_set_info = nios2_cpu_disas_set_info;
> diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
> index 52aef277232..674e1ac0d23 100644
> --- a/target/openrisc/cpu.c
> +++ b/target/openrisc/cpu.c
> @@ -178,6 +178,7 @@ static void openrisc_any_initfn(Object *obj)
>  
>  static const struct TCGCPUOps openrisc_tcg_ops = {
>      .initialize = openrisc_translate_init,
> +    .has_work = openrisc_cpu_has_work,
>      .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
>      .tlb_fill = openrisc_cpu_tlb_fill,
>  
> @@ -197,7 +198,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset);
>  
>      cc->class_by_name = openrisc_cpu_class_by_name;
> -    cc->has_work = openrisc_cpu_has_work;
>      cc->dump_state = openrisc_cpu_dump_state;
>      cc->set_pc = openrisc_cpu_set_pc;
>      cc->gdb_read_register = openrisc_cpu_gdb_read_register;
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6f9822bc0a1..a5de166bb3f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -584,6 +584,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
>  
>  static const struct TCGCPUOps riscv_tcg_ops = {
>      .initialize = riscv_translate_init,
> +    .has_work = riscv_cpu_has_work,
>      .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
>      .tlb_fill = riscv_cpu_tlb_fill,
> @@ -607,7 +608,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
>      device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
>  
>      cc->class_by_name = riscv_cpu_class_by_name;
> -    cc->has_work = riscv_cpu_has_work;
>      cc->dump_state = riscv_cpu_dump_state;
>      cc->set_pc = riscv_cpu_set_pc;
>      cc->gdb_read_register = riscv_cpu_gdb_read_register;
> diff --git a/target/rx/cpu.c b/target/rx/cpu.c
> index 28d2becc32c..f5f967ff509 100644
> --- a/target/rx/cpu.c
> +++ b/target/rx/cpu.c
> @@ -177,6 +177,7 @@ static void rx_cpu_init(Object *obj)
>  
>  static const struct TCGCPUOps rx_tcg_ops = {
>      .initialize = rx_translate_init,
> +    .has_work = rx_cpu_has_work,
>      .synchronize_from_tb = rx_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = rx_cpu_exec_interrupt,
>      .tlb_fill = rx_cpu_tlb_fill,
> @@ -198,7 +199,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
>                                    &rcc->parent_reset);
>  
>      cc->class_by_name = rx_cpu_class_by_name;
> -    cc->has_work = rx_cpu_has_work;
>      cc->dump_state = rx_cpu_dump_state;
>      cc->set_pc = rx_cpu_set_pc;
>  
> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
> index d57f69e7f7d..d2f897bf41a 100644
> --- a/target/s390x/cpu.c
> +++ b/target/s390x/cpu.c
> @@ -465,6 +465,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
>  
>  static const struct TCGCPUOps s390_tcg_ops = {
>      .initialize = s390x_translate_init,
> +    .has_work = s390_cpu_has_work,
>      .tlb_fill = s390_cpu_tlb_fill,
>  
>  #if !defined(CONFIG_USER_ONLY)
> @@ -493,7 +494,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
>  #endif
>      scc->reset = s390_cpu_reset;
>      cc->class_by_name = s390_cpu_class_by_name,
> -    cc->has_work = s390_cpu_has_work;
>      cc->dump_state = s390_cpu_dump_state;
>      cc->set_pc = s390_cpu_set_pc;
>      cc->gdb_read_register = s390_cpu_gdb_read_register;
> diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
> index 9d77f9cfdae..8bac001bfa4 100644
> --- a/target/sh4/cpu.c
> +++ b/target/sh4/cpu.c
> @@ -227,6 +227,7 @@ static const VMStateDescription vmstate_sh_cpu = {
>  
>  static const struct TCGCPUOps superh_tcg_ops = {
>      .initialize = sh4_translate_init,
> +    .has_work = superh_cpu_has_work,
>      .synchronize_from_tb = superh_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = superh_cpu_exec_interrupt,
>      .tlb_fill = superh_cpu_tlb_fill,
> @@ -250,7 +251,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset);
>  
>      cc->class_by_name = superh_cpu_class_by_name;
> -    cc->has_work = superh_cpu_has_work;
>      cc->dump_state = superh_cpu_dump_state;
>      cc->set_pc = superh_cpu_set_pc;
>      cc->gdb_read_register = superh_cpu_gdb_read_register;
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index ccabe189c4a..761813ce96b 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -853,6 +853,7 @@ static Property sparc_cpu_properties[] = {
>  
>  static const struct TCGCPUOps sparc_tcg_ops = {
>      .initialize = sparc_tcg_init,
> +    .has_work = sparc_cpu_has_work,
>      .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
>      .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
>      .tlb_fill = sparc_cpu_tlb_fill,
> @@ -879,7 +880,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
>  
>      cc->class_by_name = sparc_cpu_class_by_name;
>      cc->parse_features = sparc_cpu_parse_features;
> -    cc->has_work = sparc_cpu_has_work;
>      cc->dump_state = sparc_cpu_dump_state;
>  #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
>      cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
> diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
> index c7f8a898caf..3bc89e736b3 100644
> --- a/target/tilegx/cpu.c
> +++ b/target/tilegx/cpu.c
> @@ -138,6 +138,7 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>  
>  static const struct TCGCPUOps tilegx_tcg_ops = {
>      .initialize = tilegx_tcg_init,
> +    .has_work = tilegx_cpu_has_work,
>      .cpu_exec_interrupt = tilegx_cpu_exec_interrupt,
>      .tlb_fill = tilegx_cpu_tlb_fill,
>  
> @@ -158,7 +159,6 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, tilegx_cpu_reset, &tcc->parent_reset);
>  
>      cc->class_by_name = tilegx_cpu_class_by_name;
> -    cc->has_work = tilegx_cpu_has_work;
>      cc->dump_state = tilegx_cpu_dump_state;
>      cc->set_pc = tilegx_cpu_set_pc;
>      cc->gdb_num_core_regs = 0;
> diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
> index 5b500b575bd..b493e3ede85 100644
> --- a/target/tricore/cpu.c
> +++ b/target/tricore/cpu.c
> @@ -146,6 +146,7 @@ static void tc27x_initfn(Object *obj)
>  
>  static const struct TCGCPUOps tricore_tcg_ops = {
>      .initialize = tricore_tcg_init,
> +    .has_work = tricore_cpu_has_work,
>      .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
>      .tlb_fill = tricore_cpu_tlb_fill,
>  };
> @@ -161,7 +162,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
>  
>      device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset);
>      cc->class_by_name = tricore_cpu_class_by_name;
> -    cc->has_work = tricore_cpu_has_work;
>  
>      cc->gdb_read_register = tricore_cpu_gdb_read_register;
>      cc->gdb_write_register = tricore_cpu_gdb_write_register;
> diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
> index a732b08748d..55569018296 100644
> --- a/target/unicore32/cpu.c
> +++ b/target/unicore32/cpu.c
> @@ -124,6 +124,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
>  
>  static const struct TCGCPUOps uc32_tcg_ops = {
>      .initialize = uc32_translate_init,
> +    .has_work = uc32_cpu_has_work,
>      .cpu_exec_interrupt = uc32_cpu_exec_interrupt,
>      .tlb_fill = uc32_cpu_tlb_fill,
>  
> @@ -142,7 +143,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
>                                      &ucc->parent_realize);
>  
>      cc->class_by_name = uc32_cpu_class_by_name;
> -    cc->has_work = uc32_cpu_has_work;
>      cc->dump_state = uc32_cpu_dump_state;
>      cc->set_pc = uc32_cpu_set_pc;
>      cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
> diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
> index badc3a26aa2..849a664a679 100644
> --- a/target/xtensa/cpu.c
> +++ b/target/xtensa/cpu.c
> @@ -185,6 +185,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
>  
>  static const struct TCGCPUOps xtensa_tcg_ops = {
>      .initialize = xtensa_translate_init,
> +    .has_work = xtensa_cpu_has_work,
>      .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
>      .tlb_fill = xtensa_cpu_tlb_fill,
>      .debug_excp_handler = xtensa_breakpoint_handler,
> @@ -208,7 +209,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
>  
>      cc->class_by_name = xtensa_cpu_class_by_name;
> -    cc->has_work = xtensa_cpu_has_work;
>      cc->dump_state = xtensa_cpu_dump_state;
>      cc->set_pc = xtensa_cpu_set_pc;
>      cc->gdb_read_register = xtensa_cpu_gdb_read_register;
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index fe76d0b3773..1558de804c9 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -8633,7 +8633,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
>      pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
>      pcc->init_proc = init_proc_POWER7;
>      pcc->check_pow = check_pow_nocheck;
> -    cc->has_work = cpu_has_work_POWER7;
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
>                         PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
>                         PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -8806,7 +8805,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>      pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
>      pcc->init_proc = init_proc_POWER8;
>      pcc->check_pow = check_pow_nocheck;
> -    cc->has_work = cpu_has_work_POWER8;
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
>                         PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
>                         PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -9026,7 +9024,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
>                           PCR_COMPAT_2_05;
>      pcc->init_proc = init_proc_POWER9;
>      pcc->check_pow = check_pow_nocheck;
> -    cc->has_work = cpu_has_work_POWER9;
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
>                         PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
>                         PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -9241,7 +9238,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
>                           PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
>      pcc->init_proc = init_proc_POWER10;
>      pcc->check_pow = check_pow_nocheck;
> -    cc->has_work = cpu_has_work_POWER10;
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
>                         PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
>                         PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -10865,6 +10861,7 @@ static Property ppc_cpu_properties[] = {
>  
>  static const struct TCGCPUOps ppc_tcg_ops = {
>    .initialize = ppc_translate_init,
> +  .has_work = ppc_cpu_has_work,
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> @@ -10878,6 +10875,7 @@ static const struct TCGCPUOps ppc_tcg_ops = {
>  
>  static const struct TCGCPUOps power7_tcg_ops = {
>    .initialize = ppc_translate_init,
> +  .has_work = cpu_has_work_POWER7,
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> @@ -10891,6 +10889,7 @@ static const struct TCGCPUOps power7_tcg_ops = {
>  
>  static const struct TCGCPUOps power8_tcg_ops = {
>    .initialize = ppc_translate_init,
> +  .has_work = cpu_has_work_POWER8,
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> @@ -10904,6 +10903,7 @@ static const struct TCGCPUOps power8_tcg_ops = {
>  
>  static const struct TCGCPUOps power9_tcg_ops = {
>    .initialize = ppc_translate_init,
> +  .has_work = cpu_has_work_POWER9,
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> @@ -10917,6 +10917,7 @@ static const struct TCGCPUOps power9_tcg_ops = {
>  
>  static const struct TCGCPUOps power10_tcg_ops = {
>    .initialize = ppc_translate_init,
> +  .has_work = cpu_has_work_POWER10,
>    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>    .tlb_fill = ppc_cpu_tlb_fill,
>  
> @@ -10946,7 +10947,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
>      device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
>  
>      cc->class_by_name = ppc_cpu_class_by_name;
> -    cc->has_work = ppc_cpu_has_work;
>      cc->dump_state = ppc_cpu_dump_state;
>      cc->dump_statistics = ppc_cpu_dump_statistics;
>      cc->set_pc = ppc_cpu_set_pc;

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
  2021-03-04 22:23   ` Philippe Mathieu-Daudé
@ 2021-03-08 12:13     ` Claudio Fontana
  -1 siblings, 0 replies; 35+ messages in thread
From: Claudio Fontana @ 2021-03-08 12:13 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Cornelia Huck, Richard Henderson,
	Laurent Vivier, Greg Kurz, qemu-s390x, qemu-arm, qemu-ppc,
	Paolo Bonzini, David Gibson

On 3/4/21 11:23 PM, Philippe Mathieu-Daudé wrote:
> We can only check if a vCPU has work with TCG.
> Move the cpu_has_work() prototype to "sysemu/tcg.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> RFC: could another accelerator do that?
>      can we rename this tcg_vcpu_has_work()?
> ---
>  include/hw/core/cpu.h | 16 ----------------
>  include/sysemu/tcg.h  | 11 +++++++++++
>  accel/tcg/cpu-exec.c  |  7 +++++++
>  softmmu/cpus.c        |  1 +
>  4 files changed, 19 insertions(+), 16 deletions(-)
> 
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 1376e496a3f..66109bcca35 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename);
>   */
>  const char *parse_cpu_option(const char *cpu_option);
>  
> -/**
> - * cpu_has_work:
> - * @cpu: The vCPU to check.
> - *
> - * Checks whether the CPU has work to do.
> - *
> - * Returns: %true if the CPU has work, %false otherwise.
> - */
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> -    CPUClass *cc = CPU_GET_CLASS(cpu);
> -
> -    g_assert(cc->has_work);
> -    return cc->has_work(cpu);
> -}
> -
>  /**
>   * qemu_cpu_is_self:
>   * @cpu: The vCPU to check against.
> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
> index c16c13c3c69..3d46b0a7a93 100644
> --- a/include/sysemu/tcg.h
> +++ b/include/sysemu/tcg.h
> @@ -10,6 +10,7 @@
>  
>  #ifndef CONFIG_TCG
>  #define tcg_enabled() 0
> +#define cpu_has_work(cpu) false


I am not sure I like this approach,

it is misleading for the reader: cpu_has_work should not be called for TCG at all,
or at least a clue should be given that it is indeed a TCG-only function.

Otherwise, from the common code, the reader does not have any clue from the context that this is actually meaningful for TCG only.

Where is this actually used..?


>  #else
>  
>  void tcg_exec_init(unsigned long tb_size, int splitwx);
> @@ -26,6 +27,16 @@ extern bool tcg_allowed;
>  extern bool mttcg_enabled;
>  #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
>  
> +/**
> + * cpu_has_work:
> + * @cpu: The vCPU to check.
> + *
> + * Checks whether the CPU has work to do.
> + *
> + * Returns: %true if the CPU has work, %false otherwise.
> + */
> +bool cpu_has_work(CPUState *cpu);
> +
>  #endif /* CONFIG_TCG */
>  
>  #endif
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 7e67ade35b9..b9ce36e59e2 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
>      return tb;
>  }
>  
> +bool cpu_has_work(CPUState *cpu)
> +{
> +    CPUClass *cc = CPU_GET_CLASS(cpu);
> +
> +    return cc->has_work(cpu);
> +}
> +
>  static inline bool cpu_handle_halt(CPUState *cpu)
>  {
>      if (cpu->halted) {
> diff --git a/softmmu/cpus.c b/softmmu/cpus.c
> index a7ee431187a..548ab9236f1 100644
> --- a/softmmu/cpus.c
> +++ b/softmmu/cpus.c
> @@ -42,6 +42,7 @@
>  #include "sysemu/runstate.h"
>  #include "sysemu/cpu-timers.h"
>  #include "sysemu/whpx.h"
> +#include "sysemu/tcg.h"
>  #include "hw/boards.h"
>  #include "hw/hw.h"
>  
> 



^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
@ 2021-03-08 12:13     ` Claudio Fontana
  0 siblings, 0 replies; 35+ messages in thread
From: Claudio Fontana @ 2021-03-08 12:13 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Marcel Apfelbaum

On 3/4/21 11:23 PM, Philippe Mathieu-Daudé wrote:
> We can only check if a vCPU has work with TCG.
> Move the cpu_has_work() prototype to "sysemu/tcg.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> RFC: could another accelerator do that?
>      can we rename this tcg_vcpu_has_work()?
> ---
>  include/hw/core/cpu.h | 16 ----------------
>  include/sysemu/tcg.h  | 11 +++++++++++
>  accel/tcg/cpu-exec.c  |  7 +++++++
>  softmmu/cpus.c        |  1 +
>  4 files changed, 19 insertions(+), 16 deletions(-)
> 
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 1376e496a3f..66109bcca35 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename);
>   */
>  const char *parse_cpu_option(const char *cpu_option);
>  
> -/**
> - * cpu_has_work:
> - * @cpu: The vCPU to check.
> - *
> - * Checks whether the CPU has work to do.
> - *
> - * Returns: %true if the CPU has work, %false otherwise.
> - */
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> -    CPUClass *cc = CPU_GET_CLASS(cpu);
> -
> -    g_assert(cc->has_work);
> -    return cc->has_work(cpu);
> -}
> -
>  /**
>   * qemu_cpu_is_self:
>   * @cpu: The vCPU to check against.
> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
> index c16c13c3c69..3d46b0a7a93 100644
> --- a/include/sysemu/tcg.h
> +++ b/include/sysemu/tcg.h
> @@ -10,6 +10,7 @@
>  
>  #ifndef CONFIG_TCG
>  #define tcg_enabled() 0
> +#define cpu_has_work(cpu) false


I am not sure I like this approach,

it is misleading for the reader: cpu_has_work should not be called for TCG at all,
or at least a clue should be given that it is indeed a TCG-only function.

Otherwise, from the common code, the reader does not have any clue from the context that this is actually meaningful for TCG only.

Where is this actually used..?


>  #else
>  
>  void tcg_exec_init(unsigned long tb_size, int splitwx);
> @@ -26,6 +27,16 @@ extern bool tcg_allowed;
>  extern bool mttcg_enabled;
>  #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
>  
> +/**
> + * cpu_has_work:
> + * @cpu: The vCPU to check.
> + *
> + * Checks whether the CPU has work to do.
> + *
> + * Returns: %true if the CPU has work, %false otherwise.
> + */
> +bool cpu_has_work(CPUState *cpu);
> +
>  #endif /* CONFIG_TCG */
>  
>  #endif
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 7e67ade35b9..b9ce36e59e2 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
>      return tb;
>  }
>  
> +bool cpu_has_work(CPUState *cpu)
> +{
> +    CPUClass *cc = CPU_GET_CLASS(cpu);
> +
> +    return cc->has_work(cpu);
> +}
> +
>  static inline bool cpu_handle_halt(CPUState *cpu)
>  {
>      if (cpu->halted) {
> diff --git a/softmmu/cpus.c b/softmmu/cpus.c
> index a7ee431187a..548ab9236f1 100644
> --- a/softmmu/cpus.c
> +++ b/softmmu/cpus.c
> @@ -42,6 +42,7 @@
>  #include "sysemu/runstate.h"
>  #include "sysemu/cpu-timers.h"
>  #include "sysemu/whpx.h"
> +#include "sysemu/tcg.h"
>  #include "hw/boards.h"
>  #include "hw/hw.h"
>  
> 



^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
  2021-03-04 22:23   ` Philippe Mathieu-Daudé
@ 2021-03-08 12:17     ` Claudio Fontana
  -1 siblings, 0 replies; 35+ messages in thread
From: Claudio Fontana @ 2021-03-08 12:17 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Cornelia Huck, Richard Henderson,
	Laurent Vivier, Greg Kurz, qemu-s390x, qemu-arm, qemu-ppc,
	Paolo Bonzini, David Gibson

On 3/4/21 11:23 PM, Philippe Mathieu-Daudé wrote:
> We can only check if a vCPU has work with TCG.
> Move the cpu_has_work() prototype to "sysemu/tcg.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> RFC: could another accelerator do that?
>      can we rename this tcg_vcpu_has_work()?
> ---
>  include/hw/core/cpu.h | 16 ----------------
>  include/sysemu/tcg.h  | 11 +++++++++++
>  accel/tcg/cpu-exec.c  |  7 +++++++
>  softmmu/cpus.c        |  1 +
>  4 files changed, 19 insertions(+), 16 deletions(-)
> 
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 1376e496a3f..66109bcca35 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename);
>   */
>  const char *parse_cpu_option(const char *cpu_option);
>  
> -/**
> - * cpu_has_work:
> - * @cpu: The vCPU to check.
> - *
> - * Checks whether the CPU has work to do.
> - *
> - * Returns: %true if the CPU has work, %false otherwise.
> - */
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> -    CPUClass *cc = CPU_GET_CLASS(cpu);
> -
> -    g_assert(cc->has_work);
> -    return cc->has_work(cpu);
> -}
> -
>  /**
>   * qemu_cpu_is_self:
>   * @cpu: The vCPU to check against.
> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
> index c16c13c3c69..3d46b0a7a93 100644
> --- a/include/sysemu/tcg.h
> +++ b/include/sysemu/tcg.h
> @@ -10,6 +10,7 @@
>  
>  #ifndef CONFIG_TCG
>  #define tcg_enabled() 0
> +#define cpu_has_work(cpu) false

email errors, so not sure if my previous message went off.

I am not convinced by this approach of _hiding_ the fact that cpu_has_work is TCG-only from the context where it is used.

When reading the actual code using this, how to get an immediate clue that this is TCG-only?

I think cpu_has_work should either be renamed to tcg_cpu_has_work(), thus providing the context in the name,
or it should not be visible/called for non-TCG at all, its call protected in some way (if (tcg_enabled() or ifdef or such..)

Ciao,

Claudio


>  #else
>  
>  void tcg_exec_init(unsigned long tb_size, int splitwx);
> @@ -26,6 +27,16 @@ extern bool tcg_allowed;
>  extern bool mttcg_enabled;
>  #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
>  
> +/**
> + * cpu_has_work:
> + * @cpu: The vCPU to check.
> + *
> + * Checks whether the CPU has work to do.
> + *
> + * Returns: %true if the CPU has work, %false otherwise.
> + */
> +bool cpu_has_work(CPUState *cpu);
> +
>  #endif /* CONFIG_TCG */
>  
>  #endif
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 7e67ade35b9..b9ce36e59e2 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
>      return tb;
>  }
>  
> +bool cpu_has_work(CPUState *cpu)
> +{
> +    CPUClass *cc = CPU_GET_CLASS(cpu);
> +
> +    return cc->has_work(cpu);
> +}
> +
>  static inline bool cpu_handle_halt(CPUState *cpu)
>  {
>      if (cpu->halted) {
> diff --git a/softmmu/cpus.c b/softmmu/cpus.c
> index a7ee431187a..548ab9236f1 100644
> --- a/softmmu/cpus.c
> +++ b/softmmu/cpus.c
> @@ -42,6 +42,7 @@
>  #include "sysemu/runstate.h"
>  #include "sysemu/cpu-timers.h"
>  #include "sysemu/whpx.h"
> +#include "sysemu/tcg.h"
>  #include "hw/boards.h"
>  #include "hw/hw.h"
>  
> 



^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
@ 2021-03-08 12:17     ` Claudio Fontana
  0 siblings, 0 replies; 35+ messages in thread
From: Claudio Fontana @ 2021-03-08 12:17 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: David Hildenbrand, David Gibson, qemu-ppc, qemu-s390x,
	Thomas Huth, Laurent Vivier, Cornelia Huck, Greg Kurz,
	Paolo Bonzini, qemu-arm, Eduardo Habkost, Peter Maydell,
	Richard Henderson, qemu-riscv, Marcel Apfelbaum

On 3/4/21 11:23 PM, Philippe Mathieu-Daudé wrote:
> We can only check if a vCPU has work with TCG.
> Move the cpu_has_work() prototype to "sysemu/tcg.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> RFC: could another accelerator do that?
>      can we rename this tcg_vcpu_has_work()?
> ---
>  include/hw/core/cpu.h | 16 ----------------
>  include/sysemu/tcg.h  | 11 +++++++++++
>  accel/tcg/cpu-exec.c  |  7 +++++++
>  softmmu/cpus.c        |  1 +
>  4 files changed, 19 insertions(+), 16 deletions(-)
> 
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 1376e496a3f..66109bcca35 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename);
>   */
>  const char *parse_cpu_option(const char *cpu_option);
>  
> -/**
> - * cpu_has_work:
> - * @cpu: The vCPU to check.
> - *
> - * Checks whether the CPU has work to do.
> - *
> - * Returns: %true if the CPU has work, %false otherwise.
> - */
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> -    CPUClass *cc = CPU_GET_CLASS(cpu);
> -
> -    g_assert(cc->has_work);
> -    return cc->has_work(cpu);
> -}
> -
>  /**
>   * qemu_cpu_is_self:
>   * @cpu: The vCPU to check against.
> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
> index c16c13c3c69..3d46b0a7a93 100644
> --- a/include/sysemu/tcg.h
> +++ b/include/sysemu/tcg.h
> @@ -10,6 +10,7 @@
>  
>  #ifndef CONFIG_TCG
>  #define tcg_enabled() 0
> +#define cpu_has_work(cpu) false

email errors, so not sure if my previous message went off.

I am not convinced by this approach of _hiding_ the fact that cpu_has_work is TCG-only from the context where it is used.

When reading the actual code using this, how to get an immediate clue that this is TCG-only?

I think cpu_has_work should either be renamed to tcg_cpu_has_work(), thus providing the context in the name,
or it should not be visible/called for non-TCG at all, its call protected in some way (if (tcg_enabled() or ifdef or such..)

Ciao,

Claudio


>  #else
>  
>  void tcg_exec_init(unsigned long tb_size, int splitwx);
> @@ -26,6 +27,16 @@ extern bool tcg_allowed;
>  extern bool mttcg_enabled;
>  #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
>  
> +/**
> + * cpu_has_work:
> + * @cpu: The vCPU to check.
> + *
> + * Checks whether the CPU has work to do.
> + *
> + * Returns: %true if the CPU has work, %false otherwise.
> + */
> +bool cpu_has_work(CPUState *cpu);
> +
>  #endif /* CONFIG_TCG */
>  
>  #endif
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 7e67ade35b9..b9ce36e59e2 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
>      return tb;
>  }
>  
> +bool cpu_has_work(CPUState *cpu)
> +{
> +    CPUClass *cc = CPU_GET_CLASS(cpu);
> +
> +    return cc->has_work(cpu);
> +}
> +
>  static inline bool cpu_handle_halt(CPUState *cpu)
>  {
>      if (cpu->halted) {
> diff --git a/softmmu/cpus.c b/softmmu/cpus.c
> index a7ee431187a..548ab9236f1 100644
> --- a/softmmu/cpus.c
> +++ b/softmmu/cpus.c
> @@ -42,6 +42,7 @@
>  #include "sysemu/runstate.h"
>  #include "sysemu/cpu-timers.h"
>  #include "sysemu/whpx.h"
> +#include "sysemu/tcg.h"
>  #include "hw/boards.h"
>  #include "hw/hw.h"
>  
> 



^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
  2021-03-08 12:17     ` Claudio Fontana
@ 2021-03-08 13:37       ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-08 13:37 UTC (permalink / raw)
  To: Claudio Fontana, qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Cornelia Huck, Richard Henderson,
	Laurent Vivier, Greg Kurz, qemu-s390x, qemu-arm, qemu-ppc,
	Paolo Bonzini, David Gibson

On 3/8/21 1:17 PM, Claudio Fontana wrote:
> On 3/4/21 11:23 PM, Philippe Mathieu-Daudé wrote:
>> We can only check if a vCPU has work with TCG.
>> Move the cpu_has_work() prototype to "sysemu/tcg.h".
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> RFC: could another accelerator do that?
>>      can we rename this tcg_vcpu_has_work()?
>> ---
>>  include/hw/core/cpu.h | 16 ----------------
>>  include/sysemu/tcg.h  | 11 +++++++++++
>>  accel/tcg/cpu-exec.c  |  7 +++++++
>>  softmmu/cpus.c        |  1 +
>>  4 files changed, 19 insertions(+), 16 deletions(-)
>>
>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>> index 1376e496a3f..66109bcca35 100644
>> --- a/include/hw/core/cpu.h
>> +++ b/include/hw/core/cpu.h
>> @@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename);
>>   */
>>  const char *parse_cpu_option(const char *cpu_option);
>>  
>> -/**
>> - * cpu_has_work:
>> - * @cpu: The vCPU to check.
>> - *
>> - * Checks whether the CPU has work to do.
>> - *
>> - * Returns: %true if the CPU has work, %false otherwise.
>> - */
>> -static inline bool cpu_has_work(CPUState *cpu)
>> -{
>> -    CPUClass *cc = CPU_GET_CLASS(cpu);
>> -
>> -    g_assert(cc->has_work);
>> -    return cc->has_work(cpu);
>> -}
>> -
>>  /**
>>   * qemu_cpu_is_self:
>>   * @cpu: The vCPU to check against.
>> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
>> index c16c13c3c69..3d46b0a7a93 100644
>> --- a/include/sysemu/tcg.h
>> +++ b/include/sysemu/tcg.h
>> @@ -10,6 +10,7 @@
>>  
>>  #ifndef CONFIG_TCG
>>  #define tcg_enabled() 0
>> +#define cpu_has_work(cpu) false
> 
> email errors, so not sure if my previous message went off.

Yes, got it.

> 
> I am not convinced by this approach of _hiding_ the fact that cpu_has_work is TCG-only from the context where it is used.
> 
> When reading the actual code using this, how to get an immediate clue that this is TCG-only?
> 
> I think cpu_has_work should either be renamed to tcg_cpu_has_work(), thus providing the context in the name,
> or it should not be visible/called for non-TCG at all, its call protected in some way (if (tcg_enabled() or ifdef or such..)

If no other accelerator can do that, then I agree. I don't know enough
all accelerators to be sure.

> 
> Ciao,
> 
> Claudio
> 
> 
>>  #else
>>  
>>  void tcg_exec_init(unsigned long tb_size, int splitwx);
>> @@ -26,6 +27,16 @@ extern bool tcg_allowed;
>>  extern bool mttcg_enabled;
>>  #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
>>  
>> +/**
>> + * cpu_has_work:
>> + * @cpu: The vCPU to check.
>> + *
>> + * Checks whether the CPU has work to do.
>> + *
>> + * Returns: %true if the CPU has work, %false otherwise.
>> + */
>> +bool cpu_has_work(CPUState *cpu);
>> +
>>  #endif /* CONFIG_TCG */
>>  
>>  #endif
>> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
>> index 7e67ade35b9..b9ce36e59e2 100644
>> --- a/accel/tcg/cpu-exec.c
>> +++ b/accel/tcg/cpu-exec.c
>> @@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
>>      return tb;
>>  }
>>  
>> +bool cpu_has_work(CPUState *cpu)
>> +{
>> +    CPUClass *cc = CPU_GET_CLASS(cpu);
>> +
>> +    return cc->has_work(cpu);
>> +}
>> +
>>  static inline bool cpu_handle_halt(CPUState *cpu)
>>  {
>>      if (cpu->halted) {
>> diff --git a/softmmu/cpus.c b/softmmu/cpus.c
>> index a7ee431187a..548ab9236f1 100644
>> --- a/softmmu/cpus.c
>> +++ b/softmmu/cpus.c
>> @@ -42,6 +42,7 @@
>>  #include "sysemu/runstate.h"
>>  #include "sysemu/cpu-timers.h"
>>  #include "sysemu/whpx.h"
>> +#include "sysemu/tcg.h"
>>  #include "hw/boards.h"
>>  #include "hw/hw.h"
>>  
>>
> 
> 


^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
@ 2021-03-08 13:37       ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-08 13:37 UTC (permalink / raw)
  To: Claudio Fontana, qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Cornelia Huck, Richard Henderson,
	Laurent Vivier, Greg Kurz, qemu-s390x, qemu-arm, qemu-ppc,
	Marcel Apfelbaum, Paolo Bonzini, David Gibson

On 3/8/21 1:17 PM, Claudio Fontana wrote:
> On 3/4/21 11:23 PM, Philippe Mathieu-Daudé wrote:
>> We can only check if a vCPU has work with TCG.
>> Move the cpu_has_work() prototype to "sysemu/tcg.h".
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> RFC: could another accelerator do that?
>>      can we rename this tcg_vcpu_has_work()?
>> ---
>>  include/hw/core/cpu.h | 16 ----------------
>>  include/sysemu/tcg.h  | 11 +++++++++++
>>  accel/tcg/cpu-exec.c  |  7 +++++++
>>  softmmu/cpus.c        |  1 +
>>  4 files changed, 19 insertions(+), 16 deletions(-)
>>
>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>> index 1376e496a3f..66109bcca35 100644
>> --- a/include/hw/core/cpu.h
>> +++ b/include/hw/core/cpu.h
>> @@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename);
>>   */
>>  const char *parse_cpu_option(const char *cpu_option);
>>  
>> -/**
>> - * cpu_has_work:
>> - * @cpu: The vCPU to check.
>> - *
>> - * Checks whether the CPU has work to do.
>> - *
>> - * Returns: %true if the CPU has work, %false otherwise.
>> - */
>> -static inline bool cpu_has_work(CPUState *cpu)
>> -{
>> -    CPUClass *cc = CPU_GET_CLASS(cpu);
>> -
>> -    g_assert(cc->has_work);
>> -    return cc->has_work(cpu);
>> -}
>> -
>>  /**
>>   * qemu_cpu_is_self:
>>   * @cpu: The vCPU to check against.
>> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
>> index c16c13c3c69..3d46b0a7a93 100644
>> --- a/include/sysemu/tcg.h
>> +++ b/include/sysemu/tcg.h
>> @@ -10,6 +10,7 @@
>>  
>>  #ifndef CONFIG_TCG
>>  #define tcg_enabled() 0
>> +#define cpu_has_work(cpu) false
> 
> email errors, so not sure if my previous message went off.

Yes, got it.

> 
> I am not convinced by this approach of _hiding_ the fact that cpu_has_work is TCG-only from the context where it is used.
> 
> When reading the actual code using this, how to get an immediate clue that this is TCG-only?
> 
> I think cpu_has_work should either be renamed to tcg_cpu_has_work(), thus providing the context in the name,
> or it should not be visible/called for non-TCG at all, its call protected in some way (if (tcg_enabled() or ifdef or such..)

If no other accelerator can do that, then I agree. I don't know enough
all accelerators to be sure.

> 
> Ciao,
> 
> Claudio
> 
> 
>>  #else
>>  
>>  void tcg_exec_init(unsigned long tb_size, int splitwx);
>> @@ -26,6 +27,16 @@ extern bool tcg_allowed;
>>  extern bool mttcg_enabled;
>>  #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
>>  
>> +/**
>> + * cpu_has_work:
>> + * @cpu: The vCPU to check.
>> + *
>> + * Checks whether the CPU has work to do.
>> + *
>> + * Returns: %true if the CPU has work, %false otherwise.
>> + */
>> +bool cpu_has_work(CPUState *cpu);
>> +
>>  #endif /* CONFIG_TCG */
>>  
>>  #endif
>> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
>> index 7e67ade35b9..b9ce36e59e2 100644
>> --- a/accel/tcg/cpu-exec.c
>> +++ b/accel/tcg/cpu-exec.c
>> @@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
>>      return tb;
>>  }
>>  
>> +bool cpu_has_work(CPUState *cpu)
>> +{
>> +    CPUClass *cc = CPU_GET_CLASS(cpu);
>> +
>> +    return cc->has_work(cpu);
>> +}
>> +
>>  static inline bool cpu_handle_halt(CPUState *cpu)
>>  {
>>      if (cpu->halted) {
>> diff --git a/softmmu/cpus.c b/softmmu/cpus.c
>> index a7ee431187a..548ab9236f1 100644
>> --- a/softmmu/cpus.c
>> +++ b/softmmu/cpus.c
>> @@ -42,6 +42,7 @@
>>  #include "sysemu/runstate.h"
>>  #include "sysemu/cpu-timers.h"
>>  #include "sysemu/whpx.h"
>> +#include "sysemu/tcg.h"
>>  #include "hw/boards.h"
>>  #include "hw/hw.h"
>>  
>>
> 
> 


^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
  2021-03-04 22:23   ` Philippe Mathieu-Daudé
@ 2021-03-08 13:40     ` David Hildenbrand
  -1 siblings, 0 replies; 35+ messages in thread
From: David Hildenbrand @ 2021-03-08 13:40 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	Cornelia Huck, Richard Henderson, Laurent Vivier, Greg Kurz,
	qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
	David Gibson

On 04.03.21 23:23, Philippe Mathieu-Daudé wrote:
> Invert the #ifdef'ry to easily restrict tcg_exec_init() declaration
> to CONFIG_TCG.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   include/sysemu/tcg.h | 10 ++++++----
>   1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
> index 00349fb18a7..fddde2b6b9a 100644
> --- a/include/sysemu/tcg.h
> +++ b/include/sysemu/tcg.h
> @@ -8,13 +8,15 @@
>   #ifndef SYSEMU_TCG_H
>   #define SYSEMU_TCG_H
>   
> +#ifndef CONFIG_TCG
> +#define tcg_enabled() 0
> +#else
> +
>   void tcg_exec_init(unsigned long tb_size, int splitwx);
>   
> -#ifdef CONFIG_TCG
>   extern bool tcg_allowed;
>   #define tcg_enabled() (tcg_allowed)
> -#else
> -#define tcg_enabled() 0
> -#endif
> +
> +#endif /* CONFIG_TCG */
>   
>   #endif
> 

Reviewed-by: David Hildenbrand <david@redhat.com>

-- 
Thanks,

David / dhildenb



^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
@ 2021-03-08 13:40     ` David Hildenbrand
  0 siblings, 0 replies; 35+ messages in thread
From: David Hildenbrand @ 2021-03-08 13:40 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: David Gibson, qemu-ppc, qemu-s390x, Thomas Huth, Laurent Vivier,
	Cornelia Huck, Greg Kurz, Paolo Bonzini, qemu-arm,
	Eduardo Habkost, Peter Maydell, Richard Henderson, qemu-riscv,
	Claudio Fontana

On 04.03.21 23:23, Philippe Mathieu-Daudé wrote:
> Invert the #ifdef'ry to easily restrict tcg_exec_init() declaration
> to CONFIG_TCG.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   include/sysemu/tcg.h | 10 ++++++----
>   1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
> index 00349fb18a7..fddde2b6b9a 100644
> --- a/include/sysemu/tcg.h
> +++ b/include/sysemu/tcg.h
> @@ -8,13 +8,15 @@
>   #ifndef SYSEMU_TCG_H
>   #define SYSEMU_TCG_H
>   
> +#ifndef CONFIG_TCG
> +#define tcg_enabled() 0
> +#else
> +
>   void tcg_exec_init(unsigned long tb_size, int splitwx);
>   
> -#ifdef CONFIG_TCG
>   extern bool tcg_allowed;
>   #define tcg_enabled() (tcg_allowed)
> -#else
> -#define tcg_enabled() 0
> -#endif
> +
> +#endif /* CONFIG_TCG */
>   
>   #endif
> 

Reviewed-by: David Hildenbrand <david@redhat.com>

-- 
Thanks,

David / dhildenb



^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
  2021-03-08 13:40     ` David Hildenbrand
@ 2021-03-08 14:50       ` Claudio Fontana
  -1 siblings, 0 replies; 35+ messages in thread
From: Claudio Fontana @ 2021-03-08 14:50 UTC (permalink / raw)
  To: David Hildenbrand, Philippe Mathieu-Daudé, qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	Cornelia Huck, Richard Henderson, Laurent Vivier, Greg Kurz,
	qemu-s390x, qemu-arm, qemu-ppc, Paolo Bonzini, David Gibson

On 3/8/21 2:40 PM, David Hildenbrand wrote:
> On 04.03.21 23:23, Philippe Mathieu-Daudé wrote:
>> Invert the #ifdef'ry to easily restrict tcg_exec_init() declaration
>> to CONFIG_TCG.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>>   include/sysemu/tcg.h | 10 ++++++----
>>   1 file changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
>> index 00349fb18a7..fddde2b6b9a 100644
>> --- a/include/sysemu/tcg.h
>> +++ b/include/sysemu/tcg.h
>> @@ -8,13 +8,15 @@
>>   #ifndef SYSEMU_TCG_H
>>   #define SYSEMU_TCG_H
>>   
>> +#ifndef CONFIG_TCG
>> +#define tcg_enabled() 0
>> +#else
>> +
>>   void tcg_exec_init(unsigned long tb_size, int splitwx);
>>   
>> -#ifdef CONFIG_TCG
>>   extern bool tcg_allowed;
>>   #define tcg_enabled() (tcg_allowed)
>> -#else
>> -#define tcg_enabled() 0
>> -#endif
>> +
>> +#endif /* CONFIG_TCG */
>>   
>>   #endif
>>
> 
> Reviewed-by: David Hildenbrand <david@redhat.com>
> 
Reviewed-by: Claudio Fontana <cfontana@suse.de>


^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
@ 2021-03-08 14:50       ` Claudio Fontana
  0 siblings, 0 replies; 35+ messages in thread
From: Claudio Fontana @ 2021-03-08 14:50 UTC (permalink / raw)
  To: David Hildenbrand, Philippe Mathieu-Daudé, qemu-devel
  Cc: David Gibson, qemu-ppc, qemu-s390x, Thomas Huth, Laurent Vivier,
	Cornelia Huck, Greg Kurz, Paolo Bonzini, qemu-arm,
	Eduardo Habkost, Peter Maydell, Richard Henderson, qemu-riscv

On 3/8/21 2:40 PM, David Hildenbrand wrote:
> On 04.03.21 23:23, Philippe Mathieu-Daudé wrote:
>> Invert the #ifdef'ry to easily restrict tcg_exec_init() declaration
>> to CONFIG_TCG.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>>   include/sysemu/tcg.h | 10 ++++++----
>>   1 file changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
>> index 00349fb18a7..fddde2b6b9a 100644
>> --- a/include/sysemu/tcg.h
>> +++ b/include/sysemu/tcg.h
>> @@ -8,13 +8,15 @@
>>   #ifndef SYSEMU_TCG_H
>>   #define SYSEMU_TCG_H
>>   
>> +#ifndef CONFIG_TCG
>> +#define tcg_enabled() 0
>> +#else
>> +
>>   void tcg_exec_init(unsigned long tb_size, int splitwx);
>>   
>> -#ifdef CONFIG_TCG
>>   extern bool tcg_allowed;
>>   #define tcg_enabled() (tcg_allowed)
>> -#else
>> -#define tcg_enabled() 0
>> -#endif
>> +
>> +#endif /* CONFIG_TCG */
>>   
>>   #endif
>>
> 
> Reviewed-by: David Hildenbrand <david@redhat.com>
> 
Reviewed-by: Claudio Fontana <cfontana@suse.de>


^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 2/8] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG
  2021-03-04 22:23   ` Philippe Mathieu-Daudé
  (?)
@ 2021-03-08 14:52   ` Claudio Fontana
  -1 siblings, 0 replies; 35+ messages in thread
From: Claudio Fontana @ 2021-03-08 14:52 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Cornelia Huck, Richard Henderson,
	Laurent Vivier, Greg Kurz, qemu-s390x, qemu-arm, qemu-ppc,
	Paolo Bonzini, David Gibson

On 3/4/21 11:23 PM, Philippe Mathieu-Daudé wrote:
> qemu_tcg_mttcg_enabled() shouldn't not be used outside of TCG,
> restrict its declaration.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Claudio Fontana <cfontana@suse.de>

> ---
>  include/hw/core/cpu.h | 9 ---------
>  include/sysemu/tcg.h  | 9 +++++++++
>  accel/tcg/cpu-exec.c  | 1 +
>  tcg/tcg.c             | 1 +
>  4 files changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index e3648338dfe..1376e496a3f 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -454,15 +454,6 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
>      }
>  }
>  
> -/**
> - * qemu_tcg_mttcg_enabled:
> - * Check whether we are running MultiThread TCG or not.
> - *
> - * Returns: %true if we are in MTTCG mode %false otherwise.
> - */
> -extern bool mttcg_enabled;
> -#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
> -
>  /**
>   * cpu_paging_enabled:
>   * @cpu: The CPU whose state is to be inspected.
> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
> index fddde2b6b9a..c16c13c3c69 100644
> --- a/include/sysemu/tcg.h
> +++ b/include/sysemu/tcg.h
> @@ -17,6 +17,15 @@ void tcg_exec_init(unsigned long tb_size, int splitwx);
>  extern bool tcg_allowed;
>  #define tcg_enabled() (tcg_allowed)
>  
> +/**
> + * qemu_tcg_mttcg_enabled:
> + * Check whether we are running MultiThread TCG or not.
> + *
> + * Returns: %true if we are in MTTCG mode %false otherwise.
> + */
> +extern bool mttcg_enabled;
> +#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
> +
>  #endif /* CONFIG_TCG */
>  
>  #endif
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 16e4fe3ccd8..7e67ade35b9 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -39,6 +39,7 @@
>  #include "hw/i386/apic.h"
>  #endif
>  #include "sysemu/cpus.h"
> +#include "sysemu/tcg.h"
>  #include "exec/cpu-all.h"
>  #include "sysemu/cpu-timers.h"
>  #include "sysemu/replay.h"
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 63a12b197bf..4a4dac0bb3e 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -65,6 +65,7 @@
>  #include "elf.h"
>  #include "exec/log.h"
>  #include "sysemu/sysemu.h"
> +#include "sysemu/tcg.h"
>  
>  /* Forward declarations for functions declared in tcg-target.c.inc and
>     used here. */
> 



^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 3/8] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work
  2021-03-04 22:23   ` Philippe Mathieu-Daudé
  (?)
@ 2021-03-08 14:53   ` Claudio Fontana
  -1 siblings, 0 replies; 35+ messages in thread
From: Claudio Fontana @ 2021-03-08 14:53 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
	David Hildenbrand, Cornelia Huck, Richard Henderson,
	Laurent Vivier, Greg Kurz, qemu-s390x, qemu-arm, qemu-ppc,
	Paolo Bonzini, David Gibson

On 3/4/21 11:23 PM, Philippe Mathieu-Daudé wrote:
> There is only one CPUClass::has_work() ARM handler: arm_cpu_has_work().
> 
> Avoid a dereference by declaring it in "internals.h" and call it
> directly  in the WFI helper.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Claudio Fontana <cfontana@suse.de>
> ---
>  target/arm/internals.h | 1 +
>  target/arm/cpu.c       | 2 +-
>  target/arm/op_helper.c | 2 +-
>  3 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 05cebc8597c..1930be08828 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -172,6 +172,7 @@ static inline int r14_bank_number(int mode)
>  void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
>  void arm_translate_init(void);
>  
> +bool arm_cpu_has_work(CPUState *cs);
>  #ifdef CONFIG_TCG
>  void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
>  #endif /* CONFIG_TCG */
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 5e018b2a732..6d2d9f2100f 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -76,7 +76,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
>  }
>  #endif /* CONFIG_TCG */
>  
> -static bool arm_cpu_has_work(CPUState *cs)
> +bool arm_cpu_has_work(CPUState *cs)
>  {
>      ARMCPU *cpu = ARM_CPU(cs);
>  
> diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
> index 65cb37d088f..a4da6f4fde8 100644
> --- a/target/arm/op_helper.c
> +++ b/target/arm/op_helper.c
> @@ -289,7 +289,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
>      CPUState *cs = env_cpu(env);
>      int target_el = check_wfx_trap(env, false);
>  
> -    if (cpu_has_work(cs)) {
> +    if (arm_cpu_has_work(cs)) {
>          /* Don't bother to go into our "low power state" if
>           * we would just wake up immediately.
>           */
> 



^ permalink raw reply	[flat|nested] 35+ messages in thread
* Re: [RFC PATCH v2 0/8] cpu: Move CPUClass::has_work() to TCGCPUOps
  2021-03-04 22:23 ` Philippe Mathieu-Daudé
                   ` (8 preceding siblings ...)
  (?)
@ 2021-03-13 23:55 ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-13 23:55 UTC (permalink / raw)
  To: qemu-devel, Richard Henderson

Hi Richard,

On 3/4/21 11:23 PM, Philippe Mathieu-Daudé wrote:
> Hi,
> 
> cpu_has_work() isn't used out of TCG, so restrict it to it.
> RFC because maybe it could?
> 
> Since v1:
> - finished PPC
> - check cc->tcg_ops->has_work non-null (thuth)
> 
> Based-on: <20210227232519.222663-1-richard.henderson@linaro.org>
> 
> Philippe Mathieu-Daudé (8):
>   sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
>   sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG

Patches 1 & 2 are reviewed, could you take them via your
TCG tree?

Regards,

Phil.


^ permalink raw reply	[flat|nested] 35+ messages in thread
end of thread, other threads:[~2021-03-13 23:56 UTC | newest]

Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-04 22:23 [RFC PATCH v2 0/8] cpu: Move CPUClass::has_work() to TCGCPUOps Philippe Mathieu-Daudé
2021-03-04 22:23 ` Philippe Mathieu-Daudé
2021-03-04 22:23 ` [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG Philippe Mathieu-Daudé
2021-03-04 22:23   ` Philippe Mathieu-Daudé
2021-03-08 13:40   ` David Hildenbrand
2021-03-08 13:40     ` David Hildenbrand
2021-03-08 14:50     ` Claudio Fontana
2021-03-08 14:50       ` Claudio Fontana
2021-03-04 22:23 ` [RFC PATCH v2 2/8] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG Philippe Mathieu-Daudé
2021-03-04 22:23   ` Philippe Mathieu-Daudé
2021-03-08 14:52   ` Claudio Fontana
2021-03-04 22:23 ` [RFC PATCH v2 3/8] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work Philippe Mathieu-Daudé
2021-03-04 22:23   ` Philippe Mathieu-Daudé
2021-03-08 14:53   ` Claudio Fontana
2021-03-04 22:23 ` [RFC PATCH v2 4/8] target/s390x: Move s390_cpu_has_work to excp_helper.c Philippe Mathieu-Daudé
2021-03-04 22:23   ` Philippe Mathieu-Daudé
2021-03-04 22:23 ` [RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs Philippe Mathieu-Daudé
2021-03-04 22:23   ` Philippe Mathieu-Daudé
2021-03-05  1:05   ` David Gibson
2021-03-05  1:05     ` David Gibson
2021-03-04 22:23 ` [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h' Philippe Mathieu-Daudé
2021-03-04 22:23   ` Philippe Mathieu-Daudé
2021-03-08 12:13   ` Claudio Fontana
2021-03-08 12:13     ` Claudio Fontana
2021-03-08 12:17   ` Claudio Fontana
2021-03-08 12:17     ` Claudio Fontana
2021-03-08 13:37     ` Philippe Mathieu-Daudé
2021-03-08 13:37       ` Philippe Mathieu-Daudé
2021-03-04 22:23 ` [RFC PATCH v2 7/8] cpu: Move CPUClass::has_work() to TCGCPUOps Philippe Mathieu-Daudé
2021-03-04 22:23   ` Philippe Mathieu-Daudé
2021-03-05  1:05   ` David Gibson
2021-03-05  1:05     ` David Gibson
2021-03-04 22:23 ` [RFC PATCH v2 8/8] target/arm: Restrict arm_cpu_has_work() to TCG Philippe Mathieu-Daudé
2021-03-04 22:23   ` Philippe Mathieu-Daudé
2021-03-13 23:55 ` [RFC PATCH v2 0/8] cpu: Move CPUClass::has_work() to TCGCPUOps Philippe Mathieu-Daudé

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