* [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups
@ 2021-03-05 15:36 Ville Syrjala
2021-03-05 15:36 ` [Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask Ville Syrjala
` (8 more replies)
0 siblings, 9 replies; 21+ messages in thread
From: Ville Syrjala @ 2021-03-05 15:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The SAGV watermark handling is still a bit of mess. Let's try to
clean it up a bit more, and in the process fix up a couple of
minor mishaps.
Ville Syrjälä (6):
drm/i915: Fix enabled_planes bitmask
drm/i915: Tighten SAGV constraint for pre-tgl
drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b
drm/i915: Calculate min_ddb_alloc for trans_wm
drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level()
drm/i915: s/plane_res_b/blocks/ etc.
.../gpu/drm/i915/display/intel_atomic_plane.c | 5 +-
drivers/gpu/drm/i915/display/intel_display.c | 24 +-
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/intel_pm.c | 272 ++++++++++--------
4 files changed, 165 insertions(+), 142 deletions(-)
--
2.26.2
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
@ 2021-03-05 15:36 ` Ville Syrjala
2021-03-19 21:17 ` Navare, Manasi
2021-03-05 15:36 ` [Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl Ville Syrjala
` (7 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2021-03-05 15:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The enabled_planes bitmask was supposed to track logically enabled
planes (ie. fb!=NULL and crtc!=NULL), but instead we end up putting
even disabled planes into the bitmask since
intel_plane_atomic_check_with_state() only takes the early exit
if the plane was disabled and stays disabled. I think I misread
the early said codepath to exit whenever the plane is logically
disabled, which is not true.
So let's fix this up properly and set the bit only when the plane
actually is logically enabled.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Fixes: ee42ec19ca2e ("drm/i915: Track logically enabled planes for hw state")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 4683f98f7e54..c3f2962aa1eb 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -317,12 +317,13 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
- new_crtc_state->enabled_planes |= BIT(plane->id);
-
ret = plane->check_plane(new_crtc_state, new_plane_state);
if (ret)
return ret;
+ if (fb)
+ new_crtc_state->enabled_planes |= BIT(plane->id);
+
/* FIXME pre-g4x don't work like this */
if (new_plane_state->uapi.visible)
new_crtc_state->active_planes |= BIT(plane->id);
--
2.26.2
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
2021-03-05 15:36 ` [Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask Ville Syrjala
@ 2021-03-05 15:36 ` Ville Syrjala
2021-03-11 14:36 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 3/6] drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b Ville Syrjala
` (6 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2021-03-05 15:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Say we have two planes enabled with watermarks configured
as follows:
plane A: wm0=enabled/can_sagv=false, wm1=enabled/can_sagv=true
plane B: wm0=enabled/can_sagv=true, wm1=disabled
This is possible since the latency we use to calculate
can_sagv may not be the same for both planes due to
skl_needs_memory_bw_wa().
In this case skl_crtc_can_enable_sagv() will see that
both planes have enabled at least one watermark level
with can_sagv==true, and thus proceeds to allow SAGV.
However, since plane B does not have wm1 enabled
plane A can't actually use it either. Thus we are
now running with SAGV enabled, but plane A can't
actually tolerate the extra latency it imposes.
To remedy this only allow SAGV on if the highest common
enabled watermark level for all active planes can tolerate
the extra SAGV latency.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 854ffecd98d9..b6e34d1701a0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3876,6 +3876,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum plane_id plane_id;
+ int max_level = INT_MAX;
if (!intel_has_sagv(dev_priv))
return false;
@@ -3900,12 +3901,23 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
!wm->wm[level].plane_en; --level)
{ }
+ /* Highest common enabled wm level for all planes */
+ max_level = min(level, max_level);
+ }
+
+ /* No enabled planes? */
+ if (max_level == INT_MAX)
+ return true;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
/*
- * If any of the planes on this pipe don't enable wm levels that
- * incur memory latencies higher than sagv_block_time_us we
- * can't enable SAGV.
+ * All enabled planes must have enabled a common wm level that
+ * can tolerate memory latencies higher than sagv_block_time_us
*/
- if (!wm->wm[level].can_sagv)
+ if (wm->wm[0].plane_en && !wm->wm[max_level].can_sagv)
return false;
}
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/6] drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
2021-03-05 15:36 ` [Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask Ville Syrjala
2021-03-05 15:36 ` [Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl Ville Syrjala
@ 2021-03-05 15:36 ` Ville Syrjala
2021-03-12 12:13 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 4/6] drm/i915: Calculate min_ddb_alloc for trans_wm Ville Syrjala
` (5 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2021-03-05 15:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
For non-transition watermarks we are supposed to check min_ddb_alloc
rather than plane_res_b when determining if we have enough DDB space
for it. A bit too much copy pasta made me check the wrong thing.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: df4a50a35e2c ("drm/i915: Zero out SAGV wm when we don't have enough DDB for it")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b6e34d1701a0..36601e0a5073 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4989,7 +4989,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
if (wm->trans_wm.plane_res_b >= total[plane_id])
memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
- if (wm->sagv.wm0.plane_res_b >= total[plane_id])
+ if (wm->sagv.wm0.min_ddb_alloc > total[plane_id])
memset(&wm->sagv.wm0, 0, sizeof(wm->sagv.wm0));
if (wm->sagv.trans_wm.plane_res_b >= total[plane_id])
--
2.26.2
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 4/6] drm/i915: Calculate min_ddb_alloc for trans_wm
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
` (2 preceding siblings ...)
2021-03-05 15:36 ` [Intel-gfx] [PATCH 3/6] drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b Ville Syrjala
@ 2021-03-05 15:36 ` Ville Syrjala
2021-03-12 12:14 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 5/6] drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level() Ville Syrjala
` (4 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2021-03-05 15:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's make all the "do we have enough DDB for this WM level?"
checks use min_ddb_alloc. To achieve that we need to populate
this for the transition watermarks as well.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 36601e0a5073..38a6feced74f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4986,13 +4986,13 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- if (wm->trans_wm.plane_res_b >= total[plane_id])
+ if (wm->trans_wm.min_ddb_alloc > total[plane_id])
memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
if (wm->sagv.wm0.min_ddb_alloc > total[plane_id])
memset(&wm->sagv.wm0, 0, sizeof(wm->sagv.wm0));
- if (wm->sagv.trans_wm.plane_res_b >= total[plane_id])
+ if (wm->sagv.trans_wm.min_ddb_alloc > total[plane_id])
memset(&wm->sagv.trans_wm, 0, sizeof(wm->sagv.trans_wm));
}
@@ -5404,13 +5404,15 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
} else {
res_blocks = wm0_sel_res_b + trans_offset_b;
}
+ res_blocks++;
/*
* Just assume we can enable the transition watermark. After
* computing the DDB we'll come back and disable it if that
* assumption turns out to be false.
*/
- trans_wm->plane_res_b = res_blocks + 1;
+ trans_wm->plane_res_b = res_blocks;
+ trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, res_blocks + 1);
trans_wm->plane_en = true;
}
--
2.26.2
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 5/6] drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level()
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
` (3 preceding siblings ...)
2021-03-05 15:36 ` [Intel-gfx] [PATCH 4/6] drm/i915: Calculate min_ddb_alloc for trans_wm Ville Syrjala
@ 2021-03-05 15:36 ` Ville Syrjala
2021-03-12 12:25 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc Ville Syrjala
` (3 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2021-03-05 15:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the code more typo proof by extracting small helpers that
do the "do we have enough DDB for the WM level?" checks in
a consistent manner.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 58 ++++++++++++++++++++-------------
1 file changed, 35 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 38a6feced74f..3e26d8b667a1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4782,6 +4782,36 @@ skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
return &wm->trans_wm;
}
+/*
+ * We only disable the watermarks for each plane if
+ * they exceed the ddb allocation of said plane. This
+ * is done so that we don't end up touching cursor
+ * watermarks needlessly when some other plane reduces
+ * our max possible watermark level.
+ *
+ * Bspec has this to say about the PLANE_WM enable bit:
+ * "All the watermarks at this level for all enabled
+ * planes must be enabled before the level will be used."
+ * So this is actually safe to do.
+ */
+static void
+skl_check_wm_level(struct skl_wm_level *wm, u64 total)
+{
+ if (wm->min_ddb_alloc > total)
+ memset(wm, 0, sizeof(*wm));
+}
+
+static void
+skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
+ u64 total, u64 uv_total)
+{
+ if (wm->min_ddb_alloc > total ||
+ uv_wm->min_ddb_alloc > uv_total) {
+ memset(wm, 0, sizeof(*wm));
+ memset(uv_wm, 0, sizeof(*uv_wm));
+ }
+}
+
static int
skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
@@ -4949,21 +4979,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- /*
- * We only disable the watermarks for each plane if
- * they exceed the ddb allocation of said plane. This
- * is done so that we don't end up touching cursor
- * watermarks needlessly when some other plane reduces
- * our max possible watermark level.
- *
- * Bspec has this to say about the PLANE_WM enable bit:
- * "All the watermarks at this level for all enabled
- * planes must be enabled before the level will be used."
- * So this is actually safe to do.
- */
- if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
- wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
- memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+ skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
+ total[plane_id], uv_total[plane_id]);
/*
* Wa_1408961008:icl, ehl
@@ -4986,14 +5003,9 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- if (wm->trans_wm.min_ddb_alloc > total[plane_id])
- memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
-
- if (wm->sagv.wm0.min_ddb_alloc > total[plane_id])
- memset(&wm->sagv.wm0, 0, sizeof(wm->sagv.wm0));
-
- if (wm->sagv.trans_wm.min_ddb_alloc > total[plane_id])
- memset(&wm->sagv.trans_wm, 0, sizeof(wm->sagv.trans_wm));
+ skl_check_wm_level(&wm->trans_wm, total[plane_id]);
+ skl_check_wm_level(&wm->sagv.wm0, total[plane_id]);
+ skl_check_wm_level(&wm->sagv.trans_wm, total[plane_id]);
}
return 0;
--
2.26.2
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc.
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
` (4 preceding siblings ...)
2021-03-05 15:36 ` [Intel-gfx] [PATCH 5/6] drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level() Ville Syrjala
@ 2021-03-05 15:36 ` Ville Syrjala
2021-03-11 14:26 ` Lisovskiy, Stanislav
2021-03-12 12:45 ` Lisovskiy, Stanislav
2021-03-05 16:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: More SAGV related fixes/cleanups Patchwork
` (2 subsequent siblings)
8 siblings, 2 replies; 21+ messages in thread
From: Ville Syrjala @ 2021-03-05 15:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename a bunch of the skl+ watermark struct members to
have sensible names. Avoids me having to think what
plane_res_b/etc. means.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 24 +--
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/intel_pm.c | 198 +++++++++---------
3 files changed, 112 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 076d381d3387..ad6567f04bfa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9433,12 +9433,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
drm_err(&dev_priv->drm,
"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
plane->base.base.id, plane->base.name, level,
- sw_wm_level->plane_en,
- sw_wm_level->plane_res_b,
- sw_wm_level->plane_res_l,
- hw_wm_level->plane_en,
- hw_wm_level->plane_res_b,
- hw_wm_level->plane_res_l);
+ sw_wm_level->enable,
+ sw_wm_level->blocks,
+ sw_wm_level->lines,
+ hw_wm_level->enable,
+ hw_wm_level->blocks,
+ hw_wm_level->lines);
}
hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
@@ -9448,12 +9448,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
drm_err(&dev_priv->drm,
"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
plane->base.base.id, plane->base.name,
- sw_wm_level->plane_en,
- sw_wm_level->plane_res_b,
- sw_wm_level->plane_res_l,
- hw_wm_level->plane_en,
- hw_wm_level->plane_res_b,
- hw_wm_level->plane_res_l);
+ sw_wm_level->enable,
+ sw_wm_level->blocks,
+ sw_wm_level->lines,
+ hw_wm_level->enable,
+ hw_wm_level->blocks,
+ hw_wm_level->lines);
}
/* DDB */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8d9113fa82c7..b6eaa8ee2b66 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -721,9 +721,9 @@ struct intel_pipe_wm {
struct skl_wm_level {
u16 min_ddb_alloc;
- u16 plane_res_b;
- u8 plane_res_l;
- bool plane_en;
+ u16 blocks;
+ u8 lines;
+ bool enable;
bool ignore_lines;
bool can_sagv;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3e26d8b667a1..559bc3ba9a74 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3893,12 +3893,12 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
int level;
/* Skip this plane if it's not enabled */
- if (!wm->wm[0].plane_en)
+ if (!wm->wm[0].enable)
continue;
/* Find the highest enabled wm level for this plane */
for (level = ilk_wm_max_level(dev_priv);
- !wm->wm[level].plane_en; --level)
+ !wm->wm[level].enable; --level)
{ }
/* Highest common enabled wm level for all planes */
@@ -3917,7 +3917,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
* All enabled planes must have enabled a common wm level that
* can tolerate memory latencies higher than sagv_block_time_us
*/
- if (wm->wm[0].plane_en && !wm->wm[max_level].can_sagv)
+ if (wm->wm[0].enable && !wm->wm[max_level].can_sagv)
return false;
}
@@ -3936,7 +3936,7 @@ static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- if (wm->wm[0].plane_en && !wm->sagv.wm0.plane_en)
+ if (wm->wm[0].enable && !wm->sagv.wm0.enable)
return false;
}
@@ -4987,9 +4987,9 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
* Underruns with WM1+ disabled
*/
if (IS_GEN(dev_priv, 11) &&
- level == 1 && wm->wm[0].plane_en) {
- wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
- wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
+ level == 1 && wm->wm[0].enable) {
+ wm->wm[level].blocks = wm->wm[0].blocks;
+ wm->wm[level].lines = wm->wm[0].lines;
wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
}
}
@@ -5210,7 +5210,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
- u32 res_blocks, res_lines, min_ddb_alloc = 0;
+ u32 blocks, lines, min_ddb_alloc = 0;
if (latency == 0) {
/* reject it */
@@ -5256,24 +5256,22 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
}
}
- res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
- res_lines = div_round_up_fixed16(selected_result,
- wp->plane_blocks_per_line);
+ blocks = fixed16_to_u32_round_up(selected_result) + 1;
+ lines = div_round_up_fixed16(selected_result,
+ wp->plane_blocks_per_line);
if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
/* Display WA #1125: skl,bxt,kbl */
if (level == 0 && wp->rc_surface)
- res_blocks +=
- fixed16_to_u32_round_up(wp->y_tile_minimum);
+ blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
/* Display WA #1126: skl,bxt,kbl */
if (level >= 1 && level <= 7) {
if (wp->y_tiled) {
- res_blocks +=
- fixed16_to_u32_round_up(wp->y_tile_minimum);
- res_lines += wp->y_min_scanlines;
+ blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
+ lines += wp->y_min_scanlines;
} else {
- res_blocks++;
+ blocks++;
}
/*
@@ -5282,8 +5280,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
* Assumption in DDB algorithm optimization for special
* cases. Also covers Display WA #1125 for RC.
*/
- if (result_prev->plane_res_b > res_blocks)
- res_blocks = result_prev->plane_res_b;
+ if (result_prev->blocks > blocks)
+ blocks = result_prev->blocks;
}
}
@@ -5291,40 +5289,39 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
if (wp->y_tiled) {
int extra_lines;
- if (res_lines % wp->y_min_scanlines == 0)
+ if (lines % wp->y_min_scanlines == 0)
extra_lines = wp->y_min_scanlines;
else
extra_lines = wp->y_min_scanlines * 2 -
- res_lines % wp->y_min_scanlines;
+ lines % wp->y_min_scanlines;
- min_ddb_alloc = mul_round_up_u32_fixed16(res_lines + extra_lines,
+ min_ddb_alloc = mul_round_up_u32_fixed16(lines + extra_lines,
wp->plane_blocks_per_line);
} else {
- min_ddb_alloc = res_blocks +
- DIV_ROUND_UP(res_blocks, 10);
+ min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10);
}
}
if (!skl_wm_has_lines(dev_priv, level))
- res_lines = 0;
+ lines = 0;
- if (res_lines > 31) {
+ if (lines > 31) {
/* reject it */
result->min_ddb_alloc = U16_MAX;
return;
}
/*
- * If res_lines is valid, assume we can use this watermark level
+ * If lines is valid, assume we can use this watermark level
* for now. We'll come back and disable it after we calculate the
* DDB allocation if it turns out we don't actually have enough
* blocks to satisfy it.
*/
- result->plane_res_b = res_blocks;
- result->plane_res_l = res_lines;
+ result->blocks = blocks;
+ result->lines = lines;
/* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
- result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
- result->plane_en = true;
+ result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
+ result->enable = true;
if (INTEL_GEN(dev_priv) < 12)
result->can_sagv = latency >= dev_priv->sagv_block_time_us;
@@ -5370,7 +5367,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
const struct skl_wm_params *wp)
{
u16 trans_min, trans_amount, trans_y_tile_min;
- u16 wm0_sel_res_b, trans_offset_b, res_blocks;
+ u16 wm0_blocks, trans_offset, blocks;
/* Transition WM don't make any sense if ipc is disabled */
if (!dev_priv->ipc_enabled)
@@ -5394,38 +5391,37 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
else
trans_amount = 10; /* This is configurable amount */
- trans_offset_b = trans_min + trans_amount;
+ trans_offset = trans_min + trans_amount;
/*
* The spec asks for Selected Result Blocks for wm0 (the real value),
* not Result Blocks (the integer value). Pay attention to the capital
- * letters. The value wm_l0->plane_res_b is actually Result Blocks, but
+ * letters. The value wm_l0->blocks is actually Result Blocks, but
* since Result Blocks is the ceiling of Selected Result Blocks plus 1,
* and since we later will have to get the ceiling of the sum in the
* transition watermarks calculation, we can just pretend Selected
* Result Blocks is Result Blocks minus 1 and it should work for the
* current platforms.
*/
- wm0_sel_res_b = wm0->plane_res_b - 1;
+ wm0_blocks = wm0->blocks - 1;
if (wp->y_tiled) {
trans_y_tile_min =
(u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
- res_blocks = max(wm0_sel_res_b, trans_y_tile_min) +
- trans_offset_b;
+ blocks = max(wm0_blocks, trans_y_tile_min) + trans_offset;
} else {
- res_blocks = wm0_sel_res_b + trans_offset_b;
+ blocks = wm0_blocks + trans_offset;
}
- res_blocks++;
+ blocks++;
/*
* Just assume we can enable the transition watermark. After
* computing the DDB we'll come back and disable it if that
* assumption turns out to be false.
*/
- trans_wm->plane_res_b = res_blocks;
- trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, res_blocks + 1);
- trans_wm->plane_en = true;
+ trans_wm->blocks = blocks;
+ trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1);
+ trans_wm->enable = true;
}
static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
@@ -5600,12 +5596,12 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
{
u32 val = 0;
- if (level->plane_en)
+ if (level->enable)
val |= PLANE_WM_EN;
if (level->ignore_lines)
val |= PLANE_WM_IGNORE_LINES;
- val |= level->plane_res_b;
- val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
+ val |= level->blocks;
+ val |= level->lines << PLANE_WM_LINES_SHIFT;
intel_de_write_fw(dev_priv, reg, val);
}
@@ -5670,10 +5666,10 @@ void skl_write_cursor_wm(struct intel_plane *plane,
bool skl_wm_level_equals(const struct skl_wm_level *l1,
const struct skl_wm_level *l2)
{
- return l1->plane_en == l2->plane_en &&
+ return l1->enable == l2->enable &&
l1->ignore_lines == l2->ignore_lines &&
- l1->plane_res_l == l2->plane_res_l &&
- l1->plane_res_b == l2->plane_res_b;
+ l1->lines == l2->lines &&
+ l1->blocks == l2->blocks;
}
static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
@@ -5927,66 +5923,66 @@ skl_print_wm_changes(struct intel_atomic_state *state)
"[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
" -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
plane->base.base.id, plane->base.name,
- enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
- enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
- enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
- enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
- enast(old_wm->trans_wm.plane_en),
- enast(old_wm->sagv.wm0.plane_en),
- enast(old_wm->sagv.trans_wm.plane_en),
- enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
- enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
- enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
- enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
- enast(new_wm->trans_wm.plane_en),
- enast(new_wm->sagv.wm0.plane_en),
- enast(new_wm->sagv.trans_wm.plane_en));
+ enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
+ enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable),
+ enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable),
+ enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable),
+ enast(old_wm->trans_wm.enable),
+ enast(old_wm->sagv.wm0.enable),
+ enast(old_wm->sagv.trans_wm.enable),
+ enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable),
+ enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable),
+ enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable),
+ enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable),
+ enast(new_wm->trans_wm.enable),
+ enast(new_wm->sagv.wm0.enable),
+ enast(new_wm->sagv.trans_wm.enable));
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
plane->base.base.id, plane->base.name,
- enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
- enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
- enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
- enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
- enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,
- enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,
- enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
- enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
- enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
- enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.plane_res_l,
- enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.plane_res_l,
- enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
- enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
- enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
- enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
- enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,
- enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
- enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
- enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
- enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l,
- enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.plane_res_l,
- enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.plane_res_l);
+ enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
+ enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines,
+ enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines,
+ enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines,
+ enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines,
+ enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines,
+ enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines,
+ enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines,
+ enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines,
+ enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines,
+ enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines,
+ enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines,
+ enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines,
+ enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines,
+ enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines,
+ enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines,
+ enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines,
+ enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines,
+ enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines,
+ enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines,
+ enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines,
+ enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
plane->base.base.id, plane->base.name,
- old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
- old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
- old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
- old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
- old_wm->trans_wm.plane_res_b,
- old_wm->sagv.wm0.plane_res_b,
- old_wm->sagv.trans_wm.plane_res_b,
- new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
- new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
- new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
- new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
- new_wm->trans_wm.plane_res_b,
- new_wm->sagv.wm0.plane_res_b,
- new_wm->sagv.trans_wm.plane_res_b);
+ old_wm->wm[0].blocks, old_wm->wm[1].blocks,
+ old_wm->wm[2].blocks, old_wm->wm[3].blocks,
+ old_wm->wm[4].blocks, old_wm->wm[5].blocks,
+ old_wm->wm[6].blocks, old_wm->wm[7].blocks,
+ old_wm->trans_wm.blocks,
+ old_wm->sagv.wm0.blocks,
+ old_wm->sagv.trans_wm.blocks,
+ new_wm->wm[0].blocks, new_wm->wm[1].blocks,
+ new_wm->wm[2].blocks, new_wm->wm[3].blocks,
+ new_wm->wm[4].blocks, new_wm->wm[5].blocks,
+ new_wm->wm[6].blocks, new_wm->wm[7].blocks,
+ new_wm->trans_wm.blocks,
+ new_wm->sagv.wm0.blocks,
+ new_wm->sagv.trans_wm.blocks);
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
@@ -6210,10 +6206,10 @@ static void ilk_optimize_watermarks(struct intel_atomic_state *state,
static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
{
- level->plane_en = val & PLANE_WM_EN;
+ level->enable = val & PLANE_WM_EN;
level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
- level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
- level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
+ level->blocks = val & PLANE_WM_BLOCKS_MASK;
+ level->lines = (val >> PLANE_WM_LINES_SHIFT) &
PLANE_WM_LINES_MASK;
}
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: More SAGV related fixes/cleanups
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
` (5 preceding siblings ...)
2021-03-05 15:36 ` [Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc Ville Syrjala
@ 2021-03-05 16:22 ` Patchwork
2021-03-05 16:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-05 20:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2021-03-05 16:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: More SAGV related fixes/cleanups
URL : https://patchwork.freedesktop.org/series/87699/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5c14f9d5eac8 drm/i915: Fix enabled_planes bitmask
ebc6a3e5fe6d drm/i915: Tighten SAGV constraint for pre-tgl
6316c8608f20 drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b
dca8ca1685be drm/i915: Calculate min_ddb_alloc for trans_wm
0531f5094e07 drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level()
42e654ae9c91 drm/i915: s/plane_res_b/blocks/ etc.
-:385: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#385: FILE: drivers/gpu/drm/i915/intel_pm.c:5955:
+ enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines,
-:396: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#396: FILE: drivers/gpu/drm/i915/intel_pm.c:5966:
+ enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
total: 0 errors, 2 warnings, 0 checks, 402 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: More SAGV related fixes/cleanups
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
` (6 preceding siblings ...)
2021-03-05 16:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: More SAGV related fixes/cleanups Patchwork
@ 2021-03-05 16:49 ` Patchwork
2021-03-05 20:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2021-03-05 16:49 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6035 bytes --]
== Series Details ==
Series: drm/i915: More SAGV related fixes/cleanups
URL : https://patchwork.freedesktop.org/series/87699/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19760
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19760:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@active:
- {fi-ehl-1}: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-ehl-1/igt@i915_selftest@live@active.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-ehl-1/igt@i915_selftest@live@active.html
Known issues
------------
Here are the changes found in Patchwork_19760 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +23 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_exec_gttfill@basic:
- fi-kbl-8809g: [PASS][4] -> [TIMEOUT][5] ([i915#3145]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_exec_gttfill@basic.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-8809g/igt@gem_exec_gttfill@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@client:
- fi-glk-dsi: [PASS][7] -> [DMESG-FAIL][8] ([i915#3047])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-glk-dsi/igt@i915_selftest@live@client.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-glk-dsi/igt@i915_selftest@live@client.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-kbl-soraka: NOTRUN -> [FAIL][11] ([i915#49])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@gem_linear_blits@basic:
- fi-kbl-8809g: [TIMEOUT][13] ([i915#2502]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_linear_blits@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-8809g/igt@gem_linear_blits@basic.html
#### Warnings ####
* igt@gem_tiled_blits@basic:
- fi-kbl-8809g: [TIMEOUT][15] ([i915#3145]) -> [TIMEOUT][16] ([i915#2502] / [i915#3145])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_tiled_blits@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-8809g/igt@gem_tiled_blits@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2089]: https://gitlab.freedesktop.org/drm/intel/issues/2089
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#3047]: https://gitlab.freedesktop.org/drm/intel/issues/3047
[i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (43 -> 39)
------------------------------
Additional (1): fi-kbl-soraka
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9836 -> Patchwork_19760
CI-20190529: 20190529
CI_DRM_9836: 8449e42c5aab6666ce79a2c9f5e75ddd31b9b50e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6024: d8e03fe437f0c328c96717a92ad97719c02ba2cd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19760: 42e654ae9c91f8adea0742e7a1ff4b36e4a8c7f7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
42e654ae9c91 drm/i915: s/plane_res_b/blocks/ etc.
0531f5094e07 drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level()
dca8ca1685be drm/i915: Calculate min_ddb_alloc for trans_wm
6316c8608f20 drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b
ebc6a3e5fe6d drm/i915: Tighten SAGV constraint for pre-tgl
5c14f9d5eac8 drm/i915: Fix enabled_planes bitmask
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: More SAGV related fixes/cleanups
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
` (7 preceding siblings ...)
2021-03-05 16:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-03-05 20:11 ` Patchwork
8 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2021-03-05 20:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30261 bytes --]
== Series Details ==
Series: drm/i915: More SAGV related fixes/cleanups
URL : https://patchwork.freedesktop.org/series/87699/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19760_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19760_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19760_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19760_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-skl: NOTRUN -> [TIMEOUT][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl1/igt@gem_eio@in-flight-contexts-10ms.html
* igt@i915_selftest@live@reset:
- shard-skl: [PASS][2] -> [DMESG-FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl9/igt@i915_selftest@live@reset.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl3/igt@i915_selftest@live@reset.html
* igt@kms_atomic_transition@plane-all-transition-nonblocking@edp-1-pipe-b:
- shard-iclb: [PASS][4] -> [FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb7/igt@kms_atomic_transition@plane-all-transition-nonblocking@edp-1-pipe-b.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb5/igt@kms_atomic_transition@plane-all-transition-nonblocking@edp-1-pipe-b.html
Known issues
------------
Here are the changes found in Patchwork_19760_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-4x:
- shard-iclb: NOTRUN -> [SKIP][6] ([i915#1839])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb7/igt@feature_discovery@display-4x.html
* igt@gem_create@create-massive:
- shard-snb: NOTRUN -> [DMESG-WARN][7] ([i915#3002]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb5/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#180]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_persistence@engines-mixed:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099]) +4 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb7/igt@gem_ctx_persistence@engines-mixed.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb: NOTRUN -> [SKIP][17] ([fdo#109271]) +294 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb7/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-snb: NOTRUN -> [FAIL][18] ([i915#2389]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb5/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-apl: NOTRUN -> [FAIL][19] ([i915#2389]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl6/igt@gem_exec_reloc@basic-wide-active@bcs0.html
* igt@gem_exec_schedule@u-fairslice@vecs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][20] ([i915#1610] / [i915#2803])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl2/igt@gem_exec_schedule@u-fairslice@vecs0.html
* igt@gem_exec_whisper@basic-fds-forked:
- shard-glk: [PASS][21] -> [DMESG-WARN][22] ([i915#118] / [i915#95])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk5/igt@gem_exec_whisper@basic-fds-forked.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-glk7/igt@gem_exec_whisper@basic-fds-forked.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#2190])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl4/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [PASS][24] -> [FAIL][25] ([i915#307])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb3/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][26] ([i915#2658])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb7/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][27] ([i915#2658])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl1/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][28] ([i915#2724])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb7/igt@gem_userptr_blits@vma-merge.html
* igt@gem_workarounds@suspend-resume:
- shard-tglb: [PASS][29] -> [INCOMPLETE][30] ([i915#456])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb8/igt@gem_workarounds@suspend-resume.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-tglb8/igt@gem_workarounds@suspend-resume.html
* igt@gen7_exec_parse@basic-offset:
- shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271]) +88 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl4/igt@gen7_exec_parse@basic-offset.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#658])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl7/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109293] / [fdo#109506])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_suspend@forcewake:
- shard-kbl: NOTRUN -> [DMESG-WARN][34] ([i915#180])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl4/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271]) +54 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl3/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#110723])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_joiner@basic:
- shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#2705]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl7/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-c-bad-rotation-90:
- shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111304])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl4/igt@kms_ccs@pipe-c-bad-rotation-90.html
* igt@kms_chamelium@dp-crc-single:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109284] / [fdo#111827]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb7/igt@kms_chamelium@dp-crc-single.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +8 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl7/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +9 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl4/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +22 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl8/igt@kms_chamelium@vga-hpd.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-iclb: NOTRUN -> [FAIL][43] ([i915#1149] / [i915#315])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@kms_color@pipe-a-ctm-0-75.html
- shard-skl: NOTRUN -> [DMESG-WARN][44] ([i915#1982])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl4/igt@kms_color@pipe-a-ctm-0-75.html
* igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-snb: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +20 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb7/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen:
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109278] / [fdo#109279])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][47] ([i915#180])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109278]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: NOTRUN -> [DMESG-FAIL][49] ([IGT#6])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
- shard-kbl: NOTRUN -> [DMESG-FAIL][50] ([IGT#6])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl7/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-kbl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][53] -> [FAIL][54] ([i915#79])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-wf_vblank-ts-check:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109274])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@kms_flip@2x-wf_vblank-ts-check.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [PASS][56] -> [FAIL][57] ([i915#2122])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-apl: NOTRUN -> [FAIL][58] ([i915#2641])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
- shard-skl: NOTRUN -> [FAIL][59] ([i915#2628])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-skl: [PASS][60] -> [DMESG-WARN][61] ([i915#1982])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109280]) +5 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][63] -> [FAIL][64] ([i915#1188])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl1/igt@kms_hdr@bpc-switch.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl6/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-apl: [PASS][66] -> [DMESG-WARN][67] ([i915#180])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][69] ([fdo#108145] / [i915#265]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +9 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-skl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
- shard-iclb: NOTRUN -> [SKIP][73] ([i915#658])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][74] -> [SKIP][75] ([fdo#109441])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb2/igt@kms_psr@psr2_dpms.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb6/igt@kms_psr@psr2_dpms.html
* igt@kms_setmode@basic:
- shard-snb: NOTRUN -> [FAIL][76] ([i915#31])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb5/igt@kms_setmode@basic.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][77] ([IGT#2])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl1/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271]) +214 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl2/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2437])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl3/igt@kms_writeback@writeback-check-output.html
* igt@nouveau_crc@pipe-a-ctx-flip-detection:
- shard-iclb: NOTRUN -> [SKIP][80] ([i915#2530])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@nouveau_crc@pipe-a-ctx-flip-detection.html
* igt@perf@per-context-mode-unprivileged:
- shard-iclb: NOTRUN -> [SKIP][81] ([fdo#109289]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@perf@per-context-mode-unprivileged.html
* igt@runner@aborted:
- shard-snb: NOTRUN -> ([FAIL][82], [FAIL][83]) ([i915#3002] / [i915#698])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb6/igt@runner@aborted.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb5/igt@runner@aborted.html
* igt@sysfs_clients@recycle-many:
- shard-skl: [PASS][84] -> [FAIL][85] ([i915#3028])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl1/igt@sysfs_clients@recycle-many.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl1/igt@sysfs_clients@recycle-many.html
- shard-kbl: [PASS][86] -> [FAIL][87] ([i915#3028])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl4/igt@sysfs_clients@recycle-many.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl3/igt@sysfs_clients@recycle-many.html
- shard-snb: NOTRUN -> [FAIL][88] ([i915#3028])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb5/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@sema-10@bcs0:
- shard-iclb: [PASS][89] -> [SKIP][90] ([i915#3026])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb1/igt@sysfs_clients@sema-10@bcs0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb1/igt@sysfs_clients@sema-10@bcs0.html
* igt@sysfs_clients@split-10@bcs0:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#3026])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl7/igt@sysfs_clients@split-10@bcs0.html
* igt@sysfs_clients@split-10@vcs0:
- shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#3026]) +3 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl1/igt@sysfs_clients@split-10@vcs0.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][93] ([i915#658]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb5/igt@feature_discovery@psr2.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][95] ([i915#2369] / [i915#3063]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb3/igt@gem_eio@unwedge-stress.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-tglb3/igt@gem_eio@unwedge-stress.html
- shard-skl: [TIMEOUT][97] ([i915#2369] / [i915#2771]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl1/igt@gem_eio@unwedge-stress.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@hang:
- shard-iclb: [INCOMPLETE][99] ([i915#1895] / [i915#3031]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb4/igt@gem_exec_balancer@hang.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb7/igt@gem_exec_balancer@hang.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][101] ([i915#2846]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [FAIL][103] ([i915#2842]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][105] ([i915#2842]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][107] ([i915#2842]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][109] ([i915#2849]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-iclb: [DMESG-WARN][111] ([i915#2803]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb8/igt@gem_exec_schedule@u-fairslice@rcs0.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb3/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk: [DMESG-WARN][113] ([i915#118] / [i915#95]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk7/igt@gem_exec_whisper@basic-queues-forked-all.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-glk4/igt@gem_exec_whisper@basic-queues-forked-all.html
* {igt@kms_ccs@pipe-a-random-ccs-data}:
- shard-iclb: [DMESG-WARN][115] -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb1/igt@kms_ccs@pipe-a-random-ccs-data.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb8/igt@kms_ccs@pipe-a-random-ccs-data.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-random:
- shard-skl: [FAIL][117] ([i915#54]) -> [PASS][118] +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][119] ([i915#180]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [FAIL][121] ([i915#79]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [FAIL][123] ([i915#2598]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][125] ([i915#180]) -> [PASS][126] +6 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][127] ([i915#180]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-apl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [FAIL][129] ([i915#2122]) -> [PASS][130] +2 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt:
- shard-iclb: [SKIP][131] ([i915#668]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][133] ([i915#1188]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_lowres@pipe-b-tiling-none:
- shard-snb: [SKIP][135] ([fdo#109271]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-snb2/igt@kms_plane_lowres@pipe-b-tiling-none.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb7/igt@kms_plane_lowres@pipe-b-tiling-none.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][137] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][139] ([fdo#109441]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][141] ([i915#1542]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl1/igt@perf@polling-parameterized.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl6/igt@perf@polling-parameterized.html
* igt@sysfs_clients@recycle-many:
- shard-glk: [FAIL][143] ([i915#3028]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk9/igt@sysfs_clients@recycle-many.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-glk4/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@sema-25@rcs0:
- shard-skl: [SKIP][145] ([fdo#109271]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl1/igt@sysfs_clients@sema-25@rcs0.html
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/index.html
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* Re: [Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc.
2021-03-05 15:36 ` [Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc Ville Syrjala
@ 2021-03-11 14:26 ` Lisovskiy, Stanislav
2021-03-12 12:45 ` Lisovskiy, Stanislav
1 sibling, 0 replies; 21+ messages in thread
From: Lisovskiy, Stanislav @ 2021-03-11 14:26 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Mar 05, 2021 at 05:36:10PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename a bunch of the skl+ watermark struct members to
> have sensible names. Avoids me having to think what
> plane_res_b/etc. means.
Nice idea, was always wondering why such tricky names :)
plane_res_b => blocks etc, makes huge difference for readability.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 24 +--
> .../drm/i915/display/intel_display_types.h | 6 +-
> drivers/gpu/drm/i915/intel_pm.c | 198 +++++++++---------
> 3 files changed, 112 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 076d381d3387..ad6567f04bfa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9433,12 +9433,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
> drm_err(&dev_priv->drm,
> "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> plane->base.base.id, plane->base.name, level,
> - sw_wm_level->plane_en,
> - sw_wm_level->plane_res_b,
> - sw_wm_level->plane_res_l,
> - hw_wm_level->plane_en,
> - hw_wm_level->plane_res_b,
> - hw_wm_level->plane_res_l);
> + sw_wm_level->enable,
> + sw_wm_level->blocks,
> + sw_wm_level->lines,
> + hw_wm_level->enable,
> + hw_wm_level->blocks,
> + hw_wm_level->lines);
> }
>
> hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
> @@ -9448,12 +9448,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
> drm_err(&dev_priv->drm,
> "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> plane->base.base.id, plane->base.name,
> - sw_wm_level->plane_en,
> - sw_wm_level->plane_res_b,
> - sw_wm_level->plane_res_l,
> - hw_wm_level->plane_en,
> - hw_wm_level->plane_res_b,
> - hw_wm_level->plane_res_l);
> + sw_wm_level->enable,
> + sw_wm_level->blocks,
> + sw_wm_level->lines,
> + hw_wm_level->enable,
> + hw_wm_level->blocks,
> + hw_wm_level->lines);
> }
>
> /* DDB */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8d9113fa82c7..b6eaa8ee2b66 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -721,9 +721,9 @@ struct intel_pipe_wm {
>
> struct skl_wm_level {
> u16 min_ddb_alloc;
> - u16 plane_res_b;
> - u8 plane_res_l;
> - bool plane_en;
> + u16 blocks;
> + u8 lines;
> + bool enable;
> bool ignore_lines;
> bool can_sagv;
> };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3e26d8b667a1..559bc3ba9a74 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3893,12 +3893,12 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> int level;
>
> /* Skip this plane if it's not enabled */
> - if (!wm->wm[0].plane_en)
> + if (!wm->wm[0].enable)
> continue;
>
> /* Find the highest enabled wm level for this plane */
> for (level = ilk_wm_max_level(dev_priv);
> - !wm->wm[level].plane_en; --level)
> + !wm->wm[level].enable; --level)
> { }
>
> /* Highest common enabled wm level for all planes */
> @@ -3917,7 +3917,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> * All enabled planes must have enabled a common wm level that
> * can tolerate memory latencies higher than sagv_block_time_us
> */
> - if (wm->wm[0].plane_en && !wm->wm[max_level].can_sagv)
> + if (wm->wm[0].enable && !wm->wm[max_level].can_sagv)
> return false;
> }
>
> @@ -3936,7 +3936,7 @@ static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (wm->wm[0].plane_en && !wm->sagv.wm0.plane_en)
> + if (wm->wm[0].enable && !wm->sagv.wm0.enable)
> return false;
> }
>
> @@ -4987,9 +4987,9 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> * Underruns with WM1+ disabled
> */
> if (IS_GEN(dev_priv, 11) &&
> - level == 1 && wm->wm[0].plane_en) {
> - wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
> - wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
> + level == 1 && wm->wm[0].enable) {
> + wm->wm[level].blocks = wm->wm[0].blocks;
> + wm->wm[level].lines = wm->wm[0].lines;
> wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
> }
> }
> @@ -5210,7 +5210,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> - u32 res_blocks, res_lines, min_ddb_alloc = 0;
> + u32 blocks, lines, min_ddb_alloc = 0;
>
> if (latency == 0) {
> /* reject it */
> @@ -5256,24 +5256,22 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> }
> }
>
> - res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
> - res_lines = div_round_up_fixed16(selected_result,
> - wp->plane_blocks_per_line);
> + blocks = fixed16_to_u32_round_up(selected_result) + 1;
> + lines = div_round_up_fixed16(selected_result,
> + wp->plane_blocks_per_line);
>
> if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
> /* Display WA #1125: skl,bxt,kbl */
> if (level == 0 && wp->rc_surface)
> - res_blocks +=
> - fixed16_to_u32_round_up(wp->y_tile_minimum);
> + blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
>
> /* Display WA #1126: skl,bxt,kbl */
> if (level >= 1 && level <= 7) {
> if (wp->y_tiled) {
> - res_blocks +=
> - fixed16_to_u32_round_up(wp->y_tile_minimum);
> - res_lines += wp->y_min_scanlines;
> + blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
> + lines += wp->y_min_scanlines;
> } else {
> - res_blocks++;
> + blocks++;
> }
>
> /*
> @@ -5282,8 +5280,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> * Assumption in DDB algorithm optimization for special
> * cases. Also covers Display WA #1125 for RC.
> */
> - if (result_prev->plane_res_b > res_blocks)
> - res_blocks = result_prev->plane_res_b;
> + if (result_prev->blocks > blocks)
> + blocks = result_prev->blocks;
> }
> }
>
> @@ -5291,40 +5289,39 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> if (wp->y_tiled) {
> int extra_lines;
>
> - if (res_lines % wp->y_min_scanlines == 0)
> + if (lines % wp->y_min_scanlines == 0)
> extra_lines = wp->y_min_scanlines;
> else
> extra_lines = wp->y_min_scanlines * 2 -
> - res_lines % wp->y_min_scanlines;
> + lines % wp->y_min_scanlines;
>
> - min_ddb_alloc = mul_round_up_u32_fixed16(res_lines + extra_lines,
> + min_ddb_alloc = mul_round_up_u32_fixed16(lines + extra_lines,
> wp->plane_blocks_per_line);
> } else {
> - min_ddb_alloc = res_blocks +
> - DIV_ROUND_UP(res_blocks, 10);
> + min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10);
> }
> }
>
> if (!skl_wm_has_lines(dev_priv, level))
> - res_lines = 0;
> + lines = 0;
>
> - if (res_lines > 31) {
> + if (lines > 31) {
> /* reject it */
> result->min_ddb_alloc = U16_MAX;
> return;
> }
>
> /*
> - * If res_lines is valid, assume we can use this watermark level
> + * If lines is valid, assume we can use this watermark level
> * for now. We'll come back and disable it after we calculate the
> * DDB allocation if it turns out we don't actually have enough
> * blocks to satisfy it.
> */
> - result->plane_res_b = res_blocks;
> - result->plane_res_l = res_lines;
> + result->blocks = blocks;
> + result->lines = lines;
> /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
> - result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
> - result->plane_en = true;
> + result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
> + result->enable = true;
>
> if (INTEL_GEN(dev_priv) < 12)
> result->can_sagv = latency >= dev_priv->sagv_block_time_us;
> @@ -5370,7 +5367,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
> const struct skl_wm_params *wp)
> {
> u16 trans_min, trans_amount, trans_y_tile_min;
> - u16 wm0_sel_res_b, trans_offset_b, res_blocks;
> + u16 wm0_blocks, trans_offset, blocks;
>
> /* Transition WM don't make any sense if ipc is disabled */
> if (!dev_priv->ipc_enabled)
> @@ -5394,38 +5391,37 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
> else
> trans_amount = 10; /* This is configurable amount */
>
> - trans_offset_b = trans_min + trans_amount;
> + trans_offset = trans_min + trans_amount;
>
> /*
> * The spec asks for Selected Result Blocks for wm0 (the real value),
> * not Result Blocks (the integer value). Pay attention to the capital
> - * letters. The value wm_l0->plane_res_b is actually Result Blocks, but
> + * letters. The value wm_l0->blocks is actually Result Blocks, but
> * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
> * and since we later will have to get the ceiling of the sum in the
> * transition watermarks calculation, we can just pretend Selected
> * Result Blocks is Result Blocks minus 1 and it should work for the
> * current platforms.
> */
> - wm0_sel_res_b = wm0->plane_res_b - 1;
> + wm0_blocks = wm0->blocks - 1;
>
> if (wp->y_tiled) {
> trans_y_tile_min =
> (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
> - res_blocks = max(wm0_sel_res_b, trans_y_tile_min) +
> - trans_offset_b;
> + blocks = max(wm0_blocks, trans_y_tile_min) + trans_offset;
> } else {
> - res_blocks = wm0_sel_res_b + trans_offset_b;
> + blocks = wm0_blocks + trans_offset;
> }
> - res_blocks++;
> + blocks++;
>
> /*
> * Just assume we can enable the transition watermark. After
> * computing the DDB we'll come back and disable it if that
> * assumption turns out to be false.
> */
> - trans_wm->plane_res_b = res_blocks;
> - trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, res_blocks + 1);
> - trans_wm->plane_en = true;
> + trans_wm->blocks = blocks;
> + trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1);
> + trans_wm->enable = true;
> }
>
> static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> @@ -5600,12 +5596,12 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
> {
> u32 val = 0;
>
> - if (level->plane_en)
> + if (level->enable)
> val |= PLANE_WM_EN;
> if (level->ignore_lines)
> val |= PLANE_WM_IGNORE_LINES;
> - val |= level->plane_res_b;
> - val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
> + val |= level->blocks;
> + val |= level->lines << PLANE_WM_LINES_SHIFT;
>
> intel_de_write_fw(dev_priv, reg, val);
> }
> @@ -5670,10 +5666,10 @@ void skl_write_cursor_wm(struct intel_plane *plane,
> bool skl_wm_level_equals(const struct skl_wm_level *l1,
> const struct skl_wm_level *l2)
> {
> - return l1->plane_en == l2->plane_en &&
> + return l1->enable == l2->enable &&
> l1->ignore_lines == l2->ignore_lines &&
> - l1->plane_res_l == l2->plane_res_l &&
> - l1->plane_res_b == l2->plane_res_b;
> + l1->lines == l2->lines &&
> + l1->blocks == l2->blocks;
> }
>
> static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
> @@ -5927,66 +5923,66 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
> " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
> plane->base.base.id, plane->base.name,
> - enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
> - enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
> - enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
> - enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
> - enast(old_wm->trans_wm.plane_en),
> - enast(old_wm->sagv.wm0.plane_en),
> - enast(old_wm->sagv.trans_wm.plane_en),
> - enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
> - enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
> - enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
> - enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
> - enast(new_wm->trans_wm.plane_en),
> - enast(new_wm->sagv.wm0.plane_en),
> - enast(new_wm->sagv.trans_wm.plane_en));
> + enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
> + enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable),
> + enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable),
> + enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable),
> + enast(old_wm->trans_wm.enable),
> + enast(old_wm->sagv.wm0.enable),
> + enast(old_wm->sagv.trans_wm.enable),
> + enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable),
> + enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable),
> + enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable),
> + enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable),
> + enast(new_wm->trans_wm.enable),
> + enast(new_wm->sagv.wm0.enable),
> + enast(new_wm->sagv.trans_wm.enable));
>
> drm_dbg_kms(&dev_priv->drm,
> "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
> " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
> plane->base.base.id, plane->base.name,
> - enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
> - enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
> - enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
> - enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
> - enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,
> - enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,
> - enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
> - enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
> - enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
> - enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.plane_res_l,
> - enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.plane_res_l,
> - enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
> - enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
> - enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
> - enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
> - enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,
> - enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
> - enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
> - enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> - enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l,
> - enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.plane_res_l,
> - enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.plane_res_l);
> + enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
> + enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines,
> + enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines,
> + enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines,
> + enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines,
> + enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines,
> + enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines,
> + enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines,
> + enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines,
> + enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines,
> + enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines,
> + enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines,
> + enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines,
> + enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines,
> + enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines,
> + enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines,
> + enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines,
> + enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines,
> + enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines,
> + enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines,
> + enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines,
> + enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
>
> drm_dbg_kms(&dev_priv->drm,
> "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
> plane->base.base.id, plane->base.name,
> - old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
> - old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
> - old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
> - old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
> - old_wm->trans_wm.plane_res_b,
> - old_wm->sagv.wm0.plane_res_b,
> - old_wm->sagv.trans_wm.plane_res_b,
> - new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
> - new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
> - new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
> - new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> - new_wm->trans_wm.plane_res_b,
> - new_wm->sagv.wm0.plane_res_b,
> - new_wm->sagv.trans_wm.plane_res_b);
> + old_wm->wm[0].blocks, old_wm->wm[1].blocks,
> + old_wm->wm[2].blocks, old_wm->wm[3].blocks,
> + old_wm->wm[4].blocks, old_wm->wm[5].blocks,
> + old_wm->wm[6].blocks, old_wm->wm[7].blocks,
> + old_wm->trans_wm.blocks,
> + old_wm->sagv.wm0.blocks,
> + old_wm->sagv.trans_wm.blocks,
> + new_wm->wm[0].blocks, new_wm->wm[1].blocks,
> + new_wm->wm[2].blocks, new_wm->wm[3].blocks,
> + new_wm->wm[4].blocks, new_wm->wm[5].blocks,
> + new_wm->wm[6].blocks, new_wm->wm[7].blocks,
> + new_wm->trans_wm.blocks,
> + new_wm->sagv.wm0.blocks,
> + new_wm->sagv.trans_wm.blocks);
>
> drm_dbg_kms(&dev_priv->drm,
> "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> @@ -6210,10 +6206,10 @@ static void ilk_optimize_watermarks(struct intel_atomic_state *state,
>
> static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
> {
> - level->plane_en = val & PLANE_WM_EN;
> + level->enable = val & PLANE_WM_EN;
> level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
> - level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
> - level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
> + level->blocks = val & PLANE_WM_BLOCKS_MASK;
> + level->lines = (val >> PLANE_WM_LINES_SHIFT) &
> PLANE_WM_LINES_MASK;
> }
>
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl
2021-03-05 15:36 ` [Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl Ville Syrjala
@ 2021-03-11 14:36 ` Lisovskiy, Stanislav
2021-03-11 15:28 ` Ville Syrjälä
0 siblings, 1 reply; 21+ messages in thread
From: Lisovskiy, Stanislav @ 2021-03-11 14:36 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Mar 05, 2021 at 05:36:06PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Say we have two planes enabled with watermarks configured
> as follows:
> plane A: wm0=enabled/can_sagv=false, wm1=enabled/can_sagv=true
> plane B: wm0=enabled/can_sagv=true, wm1=disabled
Was thinking about this, always thought its not possible, i.e
wm1 kinda requires more resources, so if we can do wm1, should
always be able to do wm0..
>
> This is possible since the latency we use to calculate
> can_sagv may not be the same for both planes due to
> skl_needs_memory_bw_wa().
The current code, which I see in internal at least looks like this:
/*
* FIXME: We still don't have the proper code detect if we need to apply the WA,
* so assume we'll always need it in order to avoid underruns.
*/
static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
{
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
i.e I think it will return same latency for all planes.
Or am I missing something?..
Stan
>
> In this case skl_crtc_can_enable_sagv() will see that
> both planes have enabled at least one watermark level
> with can_sagv==true, and thus proceeds to allow SAGV.
> However, since plane B does not have wm1 enabled
> plane A can't actually use it either. Thus we are
> now running with SAGV enabled, but plane A can't
> actually tolerate the extra latency it imposes.
>
> To remedy this only allow SAGV on if the highest common
> enabled watermark level for all active planes can tolerate
> the extra SAGV latency.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++----
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 854ffecd98d9..b6e34d1701a0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3876,6 +3876,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum plane_id plane_id;
> + int max_level = INT_MAX;
>
> if (!intel_has_sagv(dev_priv))
> return false;
> @@ -3900,12 +3901,23 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> !wm->wm[level].plane_en; --level)
> { }
>
> + /* Highest common enabled wm level for all planes */
> + max_level = min(level, max_level);
> + }
> +
> + /* No enabled planes? */
> + if (max_level == INT_MAX)
> + return true;
> +
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + const struct skl_plane_wm *wm =
> + &crtc_state->wm.skl.optimal.planes[plane_id];
> +
> /*
> - * If any of the planes on this pipe don't enable wm levels that
> - * incur memory latencies higher than sagv_block_time_us we
> - * can't enable SAGV.
> + * All enabled planes must have enabled a common wm level that
> + * can tolerate memory latencies higher than sagv_block_time_us
> */
> - if (!wm->wm[level].can_sagv)
> + if (wm->wm[0].plane_en && !wm->wm[max_level].can_sagv)
> return false;
> }
>
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl
2021-03-11 14:36 ` Lisovskiy, Stanislav
@ 2021-03-11 15:28 ` Ville Syrjälä
2021-03-12 12:12 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2021-03-11 15:28 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Mar 11, 2021 at 04:36:05PM +0200, Lisovskiy, Stanislav wrote:
> On Fri, Mar 05, 2021 at 05:36:06PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Say we have two planes enabled with watermarks configured
> > as follows:
> > plane A: wm0=enabled/can_sagv=false, wm1=enabled/can_sagv=true
> > plane B: wm0=enabled/can_sagv=true, wm1=disabled
>
> Was thinking about this, always thought its not possible, i.e
> wm1 kinda requires more resources, so if we can do wm1, should
> always be able to do wm0..
>
> >
> > This is possible since the latency we use to calculate
> > can_sagv may not be the same for both planes due to
> > skl_needs_memory_bw_wa().
>
> The current code, which I see in internal at least looks like this:
>
> /*
> * FIXME: We still don't have the proper code detect if we need to apply the WA,
> * so assume we'll always need it in order to avoid underruns.
> */
> static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> {
> return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> }
>
> i.e I think it will return same latency for all planes.
>
> Or am I missing something?..
We do stuff like
if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled)
latency += 15;
so different latencies for different tilings.
Also the fact that eg. Y vs. X/linear do the method1 vs. method2
selection differently could mean we get different set of wm levels
even w/o any latency adjustments. Or at least it's impossible for
me to see from the code that it couldn't happen.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl
2021-03-11 15:28 ` Ville Syrjälä
@ 2021-03-12 12:12 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 21+ messages in thread
From: Lisovskiy, Stanislav @ 2021-03-12 12:12 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Mar 11, 2021 at 05:28:43PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 11, 2021 at 04:36:05PM +0200, Lisovskiy, Stanislav wrote:
> > On Fri, Mar 05, 2021 at 05:36:06PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Say we have two planes enabled with watermarks configured
> > > as follows:
> > > plane A: wm0=enabled/can_sagv=false, wm1=enabled/can_sagv=true
> > > plane B: wm0=enabled/can_sagv=true, wm1=disabled
> >
> > Was thinking about this, always thought its not possible, i.e
> > wm1 kinda requires more resources, so if we can do wm1, should
> > always be able to do wm0..
> >
> > >
> > > This is possible since the latency we use to calculate
> > > can_sagv may not be the same for both planes due to
> > > skl_needs_memory_bw_wa().
> >
> > The current code, which I see in internal at least looks like this:
> >
> > /*
> > * FIXME: We still don't have the proper code detect if we need to apply the WA,
> > * so assume we'll always need it in order to avoid underruns.
> > */
> > static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> > {
> > return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> > }
> >
> > i.e I think it will return same latency for all planes.
> >
> > Or am I missing something?..
>
> We do stuff like
> if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled)
> latency += 15;
> so different latencies for different tilings.
>
> Also the fact that eg. Y vs. X/linear do the method1 vs. method2
> selection differently could mean we get different set of wm levels
> even w/o any latency adjustments. Or at least it's impossible for
> me to see from the code that it couldn't happen.
Ah ok, so it is based on tiling basically.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 3/6] drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b
2021-03-05 15:36 ` [Intel-gfx] [PATCH 3/6] drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b Ville Syrjala
@ 2021-03-12 12:13 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 21+ messages in thread
From: Lisovskiy, Stanislav @ 2021-03-12 12:13 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Mar 05, 2021 at 05:36:07PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> For non-transition watermarks we are supposed to check min_ddb_alloc
> rather than plane_res_b when determining if we have enough DDB space
> for it. A bit too much copy pasta made me check the wrong thing.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Fixes: df4a50a35e2c ("drm/i915: Zero out SAGV wm when we don't have enough DDB for it")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b6e34d1701a0..36601e0a5073 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4989,7 +4989,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> if (wm->trans_wm.plane_res_b >= total[plane_id])
> memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
>
> - if (wm->sagv.wm0.plane_res_b >= total[plane_id])
> + if (wm->sagv.wm0.min_ddb_alloc > total[plane_id])
> memset(&wm->sagv.wm0, 0, sizeof(wm->sagv.wm0));
>
> if (wm->sagv.trans_wm.plane_res_b >= total[plane_id])
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Calculate min_ddb_alloc for trans_wm
2021-03-05 15:36 ` [Intel-gfx] [PATCH 4/6] drm/i915: Calculate min_ddb_alloc for trans_wm Ville Syrjala
@ 2021-03-12 12:14 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 21+ messages in thread
From: Lisovskiy, Stanislav @ 2021-03-12 12:14 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Mar 05, 2021 at 05:36:08PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's make all the "do we have enough DDB for this WM level?"
> checks use min_ddb_alloc. To achieve that we need to populate
> this for the transition watermarks as well.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 36601e0a5073..38a6feced74f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4986,13 +4986,13 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (wm->trans_wm.plane_res_b >= total[plane_id])
> + if (wm->trans_wm.min_ddb_alloc > total[plane_id])
> memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
>
> if (wm->sagv.wm0.min_ddb_alloc > total[plane_id])
> memset(&wm->sagv.wm0, 0, sizeof(wm->sagv.wm0));
>
> - if (wm->sagv.trans_wm.plane_res_b >= total[plane_id])
> + if (wm->sagv.trans_wm.min_ddb_alloc > total[plane_id])
> memset(&wm->sagv.trans_wm, 0, sizeof(wm->sagv.trans_wm));
> }
>
> @@ -5404,13 +5404,15 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
> } else {
> res_blocks = wm0_sel_res_b + trans_offset_b;
> }
> + res_blocks++;
>
> /*
> * Just assume we can enable the transition watermark. After
> * computing the DDB we'll come back and disable it if that
> * assumption turns out to be false.
> */
> - trans_wm->plane_res_b = res_blocks + 1;
> + trans_wm->plane_res_b = res_blocks;
> + trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, res_blocks + 1);
> trans_wm->plane_en = true;
> }
>
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 5/6] drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level()
2021-03-05 15:36 ` [Intel-gfx] [PATCH 5/6] drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level() Ville Syrjala
@ 2021-03-12 12:25 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 21+ messages in thread
From: Lisovskiy, Stanislav @ 2021-03-12 12:25 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Mar 05, 2021 at 05:36:09PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make the code more typo proof by extracting small helpers that
> do the "do we have enough DDB for the WM level?" checks in
> a consistent manner.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 58 ++++++++++++++++++++-------------
> 1 file changed, 35 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 38a6feced74f..3e26d8b667a1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4782,6 +4782,36 @@ skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
> return &wm->trans_wm;
> }
>
> +/*
> + * We only disable the watermarks for each plane if
> + * they exceed the ddb allocation of said plane. This
> + * is done so that we don't end up touching cursor
> + * watermarks needlessly when some other plane reduces
> + * our max possible watermark level.
> + *
> + * Bspec has this to say about the PLANE_WM enable bit:
> + * "All the watermarks at this level for all enabled
> + * planes must be enabled before the level will be used."
> + * So this is actually safe to do.
> + */
> +static void
> +skl_check_wm_level(struct skl_wm_level *wm, u64 total)
> +{
> + if (wm->min_ddb_alloc > total)
> + memset(wm, 0, sizeof(*wm));
> +}
> +
> +static void
> +skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
> + u64 total, u64 uv_total)
> +{
> + if (wm->min_ddb_alloc > total ||
> + uv_wm->min_ddb_alloc > uv_total) {
> + memset(wm, 0, sizeof(*wm));
> + memset(uv_wm, 0, sizeof(*uv_wm));
> + }
> +}
> +
> static int
> skl_allocate_plane_ddb(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> @@ -4949,21 +4979,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - /*
> - * We only disable the watermarks for each plane if
> - * they exceed the ddb allocation of said plane. This
> - * is done so that we don't end up touching cursor
> - * watermarks needlessly when some other plane reduces
> - * our max possible watermark level.
> - *
> - * Bspec has this to say about the PLANE_WM enable bit:
> - * "All the watermarks at this level for all enabled
> - * planes must be enabled before the level will be used."
> - * So this is actually safe to do.
> - */
> - if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
> - wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
> - memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
> + skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
> + total[plane_id], uv_total[plane_id]);
>
> /*
> * Wa_1408961008:icl, ehl
> @@ -4986,14 +5003,9 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (wm->trans_wm.min_ddb_alloc > total[plane_id])
> - memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
> -
> - if (wm->sagv.wm0.min_ddb_alloc > total[plane_id])
> - memset(&wm->sagv.wm0, 0, sizeof(wm->sagv.wm0));
> -
> - if (wm->sagv.trans_wm.min_ddb_alloc > total[plane_id])
> - memset(&wm->sagv.trans_wm, 0, sizeof(wm->sagv.trans_wm));
> + skl_check_wm_level(&wm->trans_wm, total[plane_id]);
> + skl_check_wm_level(&wm->sagv.wm0, total[plane_id]);
> + skl_check_wm_level(&wm->sagv.trans_wm, total[plane_id]);
> }
>
> return 0;
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc.
2021-03-05 15:36 ` [Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc Ville Syrjala
2021-03-11 14:26 ` Lisovskiy, Stanislav
@ 2021-03-12 12:45 ` Lisovskiy, Stanislav
1 sibling, 0 replies; 21+ messages in thread
From: Lisovskiy, Stanislav @ 2021-03-12 12:45 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Mar 05, 2021 at 05:36:10PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename a bunch of the skl+ watermark struct members to
> have sensible names. Avoids me having to think what
> plane_res_b/etc. means.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 24 +--
> .../drm/i915/display/intel_display_types.h | 6 +-
> drivers/gpu/drm/i915/intel_pm.c | 198 +++++++++---------
> 3 files changed, 112 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 076d381d3387..ad6567f04bfa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9433,12 +9433,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
> drm_err(&dev_priv->drm,
> "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> plane->base.base.id, plane->base.name, level,
> - sw_wm_level->plane_en,
> - sw_wm_level->plane_res_b,
> - sw_wm_level->plane_res_l,
> - hw_wm_level->plane_en,
> - hw_wm_level->plane_res_b,
> - hw_wm_level->plane_res_l);
> + sw_wm_level->enable,
> + sw_wm_level->blocks,
> + sw_wm_level->lines,
> + hw_wm_level->enable,
> + hw_wm_level->blocks,
> + hw_wm_level->lines);
> }
>
> hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
> @@ -9448,12 +9448,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
> drm_err(&dev_priv->drm,
> "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> plane->base.base.id, plane->base.name,
> - sw_wm_level->plane_en,
> - sw_wm_level->plane_res_b,
> - sw_wm_level->plane_res_l,
> - hw_wm_level->plane_en,
> - hw_wm_level->plane_res_b,
> - hw_wm_level->plane_res_l);
> + sw_wm_level->enable,
> + sw_wm_level->blocks,
> + sw_wm_level->lines,
> + hw_wm_level->enable,
> + hw_wm_level->blocks,
> + hw_wm_level->lines);
> }
>
> /* DDB */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8d9113fa82c7..b6eaa8ee2b66 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -721,9 +721,9 @@ struct intel_pipe_wm {
>
> struct skl_wm_level {
> u16 min_ddb_alloc;
> - u16 plane_res_b;
> - u8 plane_res_l;
> - bool plane_en;
> + u16 blocks;
> + u8 lines;
> + bool enable;
> bool ignore_lines;
> bool can_sagv;
> };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3e26d8b667a1..559bc3ba9a74 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3893,12 +3893,12 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> int level;
>
> /* Skip this plane if it's not enabled */
> - if (!wm->wm[0].plane_en)
> + if (!wm->wm[0].enable)
> continue;
>
> /* Find the highest enabled wm level for this plane */
> for (level = ilk_wm_max_level(dev_priv);
> - !wm->wm[level].plane_en; --level)
> + !wm->wm[level].enable; --level)
> { }
>
> /* Highest common enabled wm level for all planes */
> @@ -3917,7 +3917,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> * All enabled planes must have enabled a common wm level that
> * can tolerate memory latencies higher than sagv_block_time_us
> */
> - if (wm->wm[0].plane_en && !wm->wm[max_level].can_sagv)
> + if (wm->wm[0].enable && !wm->wm[max_level].can_sagv)
> return false;
> }
>
> @@ -3936,7 +3936,7 @@ static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (wm->wm[0].plane_en && !wm->sagv.wm0.plane_en)
> + if (wm->wm[0].enable && !wm->sagv.wm0.enable)
> return false;
> }
>
> @@ -4987,9 +4987,9 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> * Underruns with WM1+ disabled
> */
> if (IS_GEN(dev_priv, 11) &&
> - level == 1 && wm->wm[0].plane_en) {
> - wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
> - wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
> + level == 1 && wm->wm[0].enable) {
> + wm->wm[level].blocks = wm->wm[0].blocks;
> + wm->wm[level].lines = wm->wm[0].lines;
> wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
> }
> }
> @@ -5210,7 +5210,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> - u32 res_blocks, res_lines, min_ddb_alloc = 0;
> + u32 blocks, lines, min_ddb_alloc = 0;
>
> if (latency == 0) {
> /* reject it */
> @@ -5256,24 +5256,22 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> }
> }
>
> - res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
> - res_lines = div_round_up_fixed16(selected_result,
> - wp->plane_blocks_per_line);
> + blocks = fixed16_to_u32_round_up(selected_result) + 1;
> + lines = div_round_up_fixed16(selected_result,
> + wp->plane_blocks_per_line);
>
> if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
> /* Display WA #1125: skl,bxt,kbl */
> if (level == 0 && wp->rc_surface)
> - res_blocks +=
> - fixed16_to_u32_round_up(wp->y_tile_minimum);
> + blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
>
> /* Display WA #1126: skl,bxt,kbl */
> if (level >= 1 && level <= 7) {
> if (wp->y_tiled) {
> - res_blocks +=
> - fixed16_to_u32_round_up(wp->y_tile_minimum);
> - res_lines += wp->y_min_scanlines;
> + blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
> + lines += wp->y_min_scanlines;
> } else {
> - res_blocks++;
> + blocks++;
> }
>
> /*
> @@ -5282,8 +5280,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> * Assumption in DDB algorithm optimization for special
> * cases. Also covers Display WA #1125 for RC.
> */
> - if (result_prev->plane_res_b > res_blocks)
> - res_blocks = result_prev->plane_res_b;
> + if (result_prev->blocks > blocks)
> + blocks = result_prev->blocks;
> }
> }
>
> @@ -5291,40 +5289,39 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> if (wp->y_tiled) {
> int extra_lines;
>
> - if (res_lines % wp->y_min_scanlines == 0)
> + if (lines % wp->y_min_scanlines == 0)
> extra_lines = wp->y_min_scanlines;
> else
> extra_lines = wp->y_min_scanlines * 2 -
> - res_lines % wp->y_min_scanlines;
> + lines % wp->y_min_scanlines;
>
> - min_ddb_alloc = mul_round_up_u32_fixed16(res_lines + extra_lines,
> + min_ddb_alloc = mul_round_up_u32_fixed16(lines + extra_lines,
> wp->plane_blocks_per_line);
> } else {
> - min_ddb_alloc = res_blocks +
> - DIV_ROUND_UP(res_blocks, 10);
> + min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10);
> }
> }
>
> if (!skl_wm_has_lines(dev_priv, level))
> - res_lines = 0;
> + lines = 0;
>
> - if (res_lines > 31) {
> + if (lines > 31) {
> /* reject it */
> result->min_ddb_alloc = U16_MAX;
> return;
> }
>
> /*
> - * If res_lines is valid, assume we can use this watermark level
> + * If lines is valid, assume we can use this watermark level
> * for now. We'll come back and disable it after we calculate the
> * DDB allocation if it turns out we don't actually have enough
> * blocks to satisfy it.
> */
> - result->plane_res_b = res_blocks;
> - result->plane_res_l = res_lines;
> + result->blocks = blocks;
> + result->lines = lines;
> /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
> - result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
> - result->plane_en = true;
> + result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
> + result->enable = true;
>
> if (INTEL_GEN(dev_priv) < 12)
> result->can_sagv = latency >= dev_priv->sagv_block_time_us;
> @@ -5370,7 +5367,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
> const struct skl_wm_params *wp)
> {
> u16 trans_min, trans_amount, trans_y_tile_min;
> - u16 wm0_sel_res_b, trans_offset_b, res_blocks;
> + u16 wm0_blocks, trans_offset, blocks;
>
> /* Transition WM don't make any sense if ipc is disabled */
> if (!dev_priv->ipc_enabled)
> @@ -5394,38 +5391,37 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
> else
> trans_amount = 10; /* This is configurable amount */
>
> - trans_offset_b = trans_min + trans_amount;
> + trans_offset = trans_min + trans_amount;
>
> /*
> * The spec asks for Selected Result Blocks for wm0 (the real value),
> * not Result Blocks (the integer value). Pay attention to the capital
> - * letters. The value wm_l0->plane_res_b is actually Result Blocks, but
> + * letters. The value wm_l0->blocks is actually Result Blocks, but
> * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
> * and since we later will have to get the ceiling of the sum in the
> * transition watermarks calculation, we can just pretend Selected
> * Result Blocks is Result Blocks minus 1 and it should work for the
> * current platforms.
> */
> - wm0_sel_res_b = wm0->plane_res_b - 1;
> + wm0_blocks = wm0->blocks - 1;
>
> if (wp->y_tiled) {
> trans_y_tile_min =
> (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
> - res_blocks = max(wm0_sel_res_b, trans_y_tile_min) +
> - trans_offset_b;
> + blocks = max(wm0_blocks, trans_y_tile_min) + trans_offset;
> } else {
> - res_blocks = wm0_sel_res_b + trans_offset_b;
> + blocks = wm0_blocks + trans_offset;
> }
> - res_blocks++;
> + blocks++;
>
> /*
> * Just assume we can enable the transition watermark. After
> * computing the DDB we'll come back and disable it if that
> * assumption turns out to be false.
> */
> - trans_wm->plane_res_b = res_blocks;
> - trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, res_blocks + 1);
> - trans_wm->plane_en = true;
> + trans_wm->blocks = blocks;
> + trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1);
> + trans_wm->enable = true;
> }
>
> static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> @@ -5600,12 +5596,12 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
> {
> u32 val = 0;
>
> - if (level->plane_en)
> + if (level->enable)
> val |= PLANE_WM_EN;
> if (level->ignore_lines)
> val |= PLANE_WM_IGNORE_LINES;
> - val |= level->plane_res_b;
> - val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
> + val |= level->blocks;
> + val |= level->lines << PLANE_WM_LINES_SHIFT;
>
> intel_de_write_fw(dev_priv, reg, val);
> }
> @@ -5670,10 +5666,10 @@ void skl_write_cursor_wm(struct intel_plane *plane,
> bool skl_wm_level_equals(const struct skl_wm_level *l1,
> const struct skl_wm_level *l2)
> {
> - return l1->plane_en == l2->plane_en &&
> + return l1->enable == l2->enable &&
> l1->ignore_lines == l2->ignore_lines &&
> - l1->plane_res_l == l2->plane_res_l &&
> - l1->plane_res_b == l2->plane_res_b;
> + l1->lines == l2->lines &&
> + l1->blocks == l2->blocks;
> }
>
> static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
> @@ -5927,66 +5923,66 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
> " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
> plane->base.base.id, plane->base.name,
> - enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
> - enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
> - enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
> - enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
> - enast(old_wm->trans_wm.plane_en),
> - enast(old_wm->sagv.wm0.plane_en),
> - enast(old_wm->sagv.trans_wm.plane_en),
> - enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
> - enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
> - enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
> - enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
> - enast(new_wm->trans_wm.plane_en),
> - enast(new_wm->sagv.wm0.plane_en),
> - enast(new_wm->sagv.trans_wm.plane_en));
> + enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
> + enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable),
> + enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable),
> + enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable),
> + enast(old_wm->trans_wm.enable),
> + enast(old_wm->sagv.wm0.enable),
> + enast(old_wm->sagv.trans_wm.enable),
> + enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable),
> + enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable),
> + enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable),
> + enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable),
> + enast(new_wm->trans_wm.enable),
> + enast(new_wm->sagv.wm0.enable),
> + enast(new_wm->sagv.trans_wm.enable));
>
> drm_dbg_kms(&dev_priv->drm,
> "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
> " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
> plane->base.base.id, plane->base.name,
> - enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
> - enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
> - enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
> - enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
> - enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,
> - enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,
> - enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
> - enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
> - enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
> - enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.plane_res_l,
> - enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.plane_res_l,
> - enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
> - enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
> - enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
> - enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
> - enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,
> - enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
> - enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
> - enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> - enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l,
> - enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.plane_res_l,
> - enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.plane_res_l);
> + enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
> + enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines,
> + enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines,
> + enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines,
> + enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines,
> + enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines,
> + enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines,
> + enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines,
> + enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines,
> + enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines,
> + enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines,
> + enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines,
> + enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines,
> + enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines,
> + enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines,
> + enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines,
> + enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines,
> + enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines,
> + enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines,
> + enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines,
> + enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines,
> + enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
>
> drm_dbg_kms(&dev_priv->drm,
> "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
> plane->base.base.id, plane->base.name,
> - old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
> - old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
> - old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
> - old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
> - old_wm->trans_wm.plane_res_b,
> - old_wm->sagv.wm0.plane_res_b,
> - old_wm->sagv.trans_wm.plane_res_b,
> - new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
> - new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
> - new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
> - new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> - new_wm->trans_wm.plane_res_b,
> - new_wm->sagv.wm0.plane_res_b,
> - new_wm->sagv.trans_wm.plane_res_b);
> + old_wm->wm[0].blocks, old_wm->wm[1].blocks,
> + old_wm->wm[2].blocks, old_wm->wm[3].blocks,
> + old_wm->wm[4].blocks, old_wm->wm[5].blocks,
> + old_wm->wm[6].blocks, old_wm->wm[7].blocks,
> + old_wm->trans_wm.blocks,
> + old_wm->sagv.wm0.blocks,
> + old_wm->sagv.trans_wm.blocks,
> + new_wm->wm[0].blocks, new_wm->wm[1].blocks,
> + new_wm->wm[2].blocks, new_wm->wm[3].blocks,
> + new_wm->wm[4].blocks, new_wm->wm[5].blocks,
> + new_wm->wm[6].blocks, new_wm->wm[7].blocks,
> + new_wm->trans_wm.blocks,
> + new_wm->sagv.wm0.blocks,
> + new_wm->sagv.trans_wm.blocks);
>
> drm_dbg_kms(&dev_priv->drm,
> "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> @@ -6210,10 +6206,10 @@ static void ilk_optimize_watermarks(struct intel_atomic_state *state,
>
> static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
> {
> - level->plane_en = val & PLANE_WM_EN;
> + level->enable = val & PLANE_WM_EN;
> level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
> - level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
> - level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
> + level->blocks = val & PLANE_WM_BLOCKS_MASK;
> + level->lines = (val >> PLANE_WM_LINES_SHIFT) &
> PLANE_WM_LINES_MASK;
> }
>
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask
2021-03-05 15:36 ` [Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask Ville Syrjala
@ 2021-03-19 21:17 ` Navare, Manasi
2021-03-19 21:20 ` Ville Syrjälä
0 siblings, 1 reply; 21+ messages in thread
From: Navare, Manasi @ 2021-03-19 21:17 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Mar 05, 2021 at 05:36:05PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The enabled_planes bitmask was supposed to track logically enabled
> planes (ie. fb!=NULL and crtc!=NULL), but instead we end up putting
> even disabled planes into the bitmask since
> intel_plane_atomic_check_with_state() only takes the early exit
> if the plane was disabled and stays disabled. I think I misread
> the early said codepath to exit whenever the plane is logically
> disabled, which is not true.
>
> So let's fix this up properly and set the bit only when the plane
> actually is logically enabled.
Hmm yes makes sense, I guess I added the check in skl_plane_check_fb to return if !fb
but I think thats a bug there since I return 0 there instead of return a -EINVAL or something.
Because if we return a negative value there then if !fb, skl_plane_check will return that
and we will return from plane->check_plane so just moving the enabled planes bitmask assignment
to after the check_plane will do no need to check for if (fb) there again right?
Manasi
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Fixes: ee42ec19ca2e ("drm/i915: Track logically enabled planes for hw state")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 4683f98f7e54..c3f2962aa1eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -317,12 +317,13 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
> return 0;
>
> - new_crtc_state->enabled_planes |= BIT(plane->id);
> -
> ret = plane->check_plane(new_crtc_state, new_plane_state);
> if (ret)
> return ret;
>
> + if (fb)
> + new_crtc_state->enabled_planes |= BIT(plane->id);
> +
> /* FIXME pre-g4x don't work like this */
> if (new_plane_state->uapi.visible)
> new_crtc_state->active_planes |= BIT(plane->id);
> --
> 2.26.2
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask
2021-03-19 21:17 ` Navare, Manasi
@ 2021-03-19 21:20 ` Ville Syrjälä
2021-03-19 21:30 ` Navare, Manasi
0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2021-03-19 21:20 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx
On Fri, Mar 19, 2021 at 02:17:18PM -0700, Navare, Manasi wrote:
> On Fri, Mar 05, 2021 at 05:36:05PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The enabled_planes bitmask was supposed to track logically enabled
> > planes (ie. fb!=NULL and crtc!=NULL), but instead we end up putting
> > even disabled planes into the bitmask since
> > intel_plane_atomic_check_with_state() only takes the early exit
> > if the plane was disabled and stays disabled. I think I misread
> > the early said codepath to exit whenever the plane is logically
> > disabled, which is not true.
> >
> > So let's fix this up properly and set the bit only when the plane
> > actually is logically enabled.
>
> Hmm yes makes sense, I guess I added the check in skl_plane_check_fb to return if !fb
> but I think thats a bug there since I return 0 there instead of return a -EINVAL or something.
No. Return 0 is the correct there. It just means we have nothing to
check, and all is well. I suppose we could move the whole thing later
and not have the fb check at all, but I kinda like doing that early
to make sure no funky stuff leaks into the later checks.
>
> Because if we return a negative value there then if !fb, skl_plane_check will return that
> and we will return from plane->check_plane so just moving the enabled planes bitmask assignment
> to after the check_plane will do no need to check for if (fb) there again right?
>
> Manasi
>
> >
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Fixes: ee42ec19ca2e ("drm/i915: Track logically enabled planes for hw state")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index 4683f98f7e54..c3f2962aa1eb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -317,12 +317,13 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> > if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
> > return 0;
> >
> > - new_crtc_state->enabled_planes |= BIT(plane->id);
> > -
> > ret = plane->check_plane(new_crtc_state, new_plane_state);
> > if (ret)
> > return ret;
> >
> > + if (fb)
> > + new_crtc_state->enabled_planes |= BIT(plane->id);
> > +
> > /* FIXME pre-g4x don't work like this */
> > if (new_plane_state->uapi.visible)
> > new_crtc_state->active_planes |= BIT(plane->id);
> > --
> > 2.26.2
> >
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask
2021-03-19 21:20 ` Ville Syrjälä
@ 2021-03-19 21:30 ` Navare, Manasi
0 siblings, 0 replies; 21+ messages in thread
From: Navare, Manasi @ 2021-03-19 21:30 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Mar 19, 2021 at 11:20:07PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 19, 2021 at 02:17:18PM -0700, Navare, Manasi wrote:
> > On Fri, Mar 05, 2021 at 05:36:05PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The enabled_planes bitmask was supposed to track logically enabled
> > > planes (ie. fb!=NULL and crtc!=NULL), but instead we end up putting
> > > even disabled planes into the bitmask since
> > > intel_plane_atomic_check_with_state() only takes the early exit
> > > if the plane was disabled and stays disabled. I think I misread
> > > the early said codepath to exit whenever the plane is logically
> > > disabled, which is not true.
> > >
> > > So let's fix this up properly and set the bit only when the plane
> > > actually is logically enabled.
> >
> > Hmm yes makes sense, I guess I added the check in skl_plane_check_fb to return if !fb
> > but I think thats a bug there since I return 0 there instead of return a -EINVAL or something.
>
> No. Return 0 is the correct there. It just means we have nothing to
> check, and all is well. I suppose we could move the whole thing later
> and not have the fb check at all, but I kinda like doing that early
> to make sure no funky stuff leaks into the later checks.
>
Okay so in that case this pathc check looks good
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> >
> > Because if we return a negative value there then if !fb, skl_plane_check will return that
> > and we will return from plane->check_plane so just moving the enabled planes bitmask assignment
> > to after the check_plane will do no need to check for if (fb) there again right?
> >
> > Manasi
> >
> > >
> > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > Fixes: ee42ec19ca2e ("drm/i915: Track logically enabled planes for hw state")
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++--
> > > 1 file changed, 3 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > index 4683f98f7e54..c3f2962aa1eb 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > @@ -317,12 +317,13 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> > > if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
> > > return 0;
> > >
> > > - new_crtc_state->enabled_planes |= BIT(plane->id);
> > > -
> > > ret = plane->check_plane(new_crtc_state, new_plane_state);
> > > if (ret)
> > > return ret;
> > >
> > > + if (fb)
> > > + new_crtc_state->enabled_planes |= BIT(plane->id);
> > > +
> > > /* FIXME pre-g4x don't work like this */
> > > if (new_plane_state->uapi.visible)
> > > new_crtc_state->active_planes |= BIT(plane->id);
> > > --
> > > 2.26.2
> > >
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2021-03-19 21:24 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
2021-03-05 15:36 ` [Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask Ville Syrjala
2021-03-19 21:17 ` Navare, Manasi
2021-03-19 21:20 ` Ville Syrjälä
2021-03-19 21:30 ` Navare, Manasi
2021-03-05 15:36 ` [Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl Ville Syrjala
2021-03-11 14:36 ` Lisovskiy, Stanislav
2021-03-11 15:28 ` Ville Syrjälä
2021-03-12 12:12 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 3/6] drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b Ville Syrjala
2021-03-12 12:13 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 4/6] drm/i915: Calculate min_ddb_alloc for trans_wm Ville Syrjala
2021-03-12 12:14 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 5/6] drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level() Ville Syrjala
2021-03-12 12:25 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc Ville Syrjala
2021-03-11 14:26 ` Lisovskiy, Stanislav
2021-03-12 12:45 ` Lisovskiy, Stanislav
2021-03-05 16:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: More SAGV related fixes/cleanups Patchwork
2021-03-05 16:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-05 20:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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