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* [PATCH] MIPS: pci-mt7620: fix PLL lock check
@ 2021-03-07  4:17 ` Ilya Lipnitskiy
  0 siblings, 0 replies; 4+ messages in thread
From: Ilya Lipnitskiy @ 2021-03-07  4:17 UTC (permalink / raw)
  To: Thomas Bogendoerfer, Matthias Brugger
  Cc: Ilya Lipnitskiy, John Crispin, linux-mips, linux-mediatek,
	linux-kernel, stable

Upstream a long-standing OpenWrt patch [0] that fixes MT7620 PCIe PLL
lock check. The existing code checks the wrong register bit: PPLL_SW_SET
is not defined in PPLL_CFG1 and bit 31 of PPLL_CFG1 is marked as reserved
in the MT7620 Programming Guide. The correct bit to check for PLL lock
is PPLL_LD (bit 23).

Also reword the error message for clarity.

Without this change it is unlikely that this driver ever worked with
mainline kernel.

[0]: https://lists.infradead.org/pipermail/lede-commits/2017-July/004441.html

Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Cc: John Crispin <john@phrozen.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: stable@vger.kernel.org
---
 arch/mips/pci/pci-mt7620.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c
index d36061603752..e032932348d6 100644
--- a/arch/mips/pci/pci-mt7620.c
+++ b/arch/mips/pci/pci-mt7620.c
@@ -30,6 +30,7 @@
 #define RALINK_GPIOMODE			0x60
 
 #define PPLL_CFG1			0x9c
+#define PPLL_LD				BIT(23)
 
 #define PPLL_DRV			0xa0
 #define PDRV_SW_SET			BIT(31)
@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct platform_device *pdev)
 	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 	mdelay(100);
 
-	if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
-		dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
+	if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
+		dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");
 		reset_control_assert(rstpcie0);
 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 		return -1;
-- 
2.30.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH] MIPS: pci-mt7620: fix PLL lock check
@ 2021-03-07  4:17 ` Ilya Lipnitskiy
  0 siblings, 0 replies; 4+ messages in thread
From: Ilya Lipnitskiy @ 2021-03-07  4:17 UTC (permalink / raw)
  To: Thomas Bogendoerfer, Matthias Brugger
  Cc: Ilya Lipnitskiy, John Crispin, linux-mips, linux-mediatek,
	linux-kernel, stable

Upstream a long-standing OpenWrt patch [0] that fixes MT7620 PCIe PLL
lock check. The existing code checks the wrong register bit: PPLL_SW_SET
is not defined in PPLL_CFG1 and bit 31 of PPLL_CFG1 is marked as reserved
in the MT7620 Programming Guide. The correct bit to check for PLL lock
is PPLL_LD (bit 23).

Also reword the error message for clarity.

Without this change it is unlikely that this driver ever worked with
mainline kernel.

[0]: https://lists.infradead.org/pipermail/lede-commits/2017-July/004441.html

Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Cc: John Crispin <john@phrozen.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: stable@vger.kernel.org
---
 arch/mips/pci/pci-mt7620.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c
index d36061603752..e032932348d6 100644
--- a/arch/mips/pci/pci-mt7620.c
+++ b/arch/mips/pci/pci-mt7620.c
@@ -30,6 +30,7 @@
 #define RALINK_GPIOMODE			0x60
 
 #define PPLL_CFG1			0x9c
+#define PPLL_LD				BIT(23)
 
 #define PPLL_DRV			0xa0
 #define PDRV_SW_SET			BIT(31)
@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct platform_device *pdev)
 	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 	mdelay(100);
 
-	if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
-		dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
+	if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
+		dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");
 		reset_control_assert(rstpcie0);
 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 		return -1;
-- 
2.30.1


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] MIPS: pci-mt7620: fix PLL lock check
  2021-03-07  4:17 ` Ilya Lipnitskiy
@ 2021-03-12 10:27   ` Thomas Bogendoerfer
  -1 siblings, 0 replies; 4+ messages in thread
From: Thomas Bogendoerfer @ 2021-03-12 10:27 UTC (permalink / raw)
  To: Ilya Lipnitskiy
  Cc: Matthias Brugger, John Crispin, linux-mips, linux-mediatek,
	linux-kernel, stable

On Sat, Mar 06, 2021 at 08:17:24PM -0800, Ilya Lipnitskiy wrote:
> Upstream a long-standing OpenWrt patch [0] that fixes MT7620 PCIe PLL
> lock check. The existing code checks the wrong register bit: PPLL_SW_SET
> is not defined in PPLL_CFG1 and bit 31 of PPLL_CFG1 is marked as reserved
> in the MT7620 Programming Guide. The correct bit to check for PLL lock
> is PPLL_LD (bit 23).
> 
> Also reword the error message for clarity.
> 
> Without this change it is unlikely that this driver ever worked with
> mainline kernel.
> 
> [0]: https://lists.infradead.org/pipermail/lede-commits/2017-July/004441.html
> 
> Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
> Cc: John Crispin <john@phrozen.org>
> Cc: linux-mips@vger.kernel.org
> Cc: linux-mediatek@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: stable@vger.kernel.org
> ---
>  arch/mips/pci/pci-mt7620.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] MIPS: pci-mt7620: fix PLL lock check
@ 2021-03-12 10:27   ` Thomas Bogendoerfer
  0 siblings, 0 replies; 4+ messages in thread
From: Thomas Bogendoerfer @ 2021-03-12 10:27 UTC (permalink / raw)
  To: Ilya Lipnitskiy
  Cc: Matthias Brugger, John Crispin, linux-mips, linux-mediatek,
	linux-kernel, stable

On Sat, Mar 06, 2021 at 08:17:24PM -0800, Ilya Lipnitskiy wrote:
> Upstream a long-standing OpenWrt patch [0] that fixes MT7620 PCIe PLL
> lock check. The existing code checks the wrong register bit: PPLL_SW_SET
> is not defined in PPLL_CFG1 and bit 31 of PPLL_CFG1 is marked as reserved
> in the MT7620 Programming Guide. The correct bit to check for PLL lock
> is PPLL_LD (bit 23).
> 
> Also reword the error message for clarity.
> 
> Without this change it is unlikely that this driver ever worked with
> mainline kernel.
> 
> [0]: https://lists.infradead.org/pipermail/lede-commits/2017-July/004441.html
> 
> Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
> Cc: John Crispin <john@phrozen.org>
> Cc: linux-mips@vger.kernel.org
> Cc: linux-mediatek@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: stable@vger.kernel.org
> ---
>  arch/mips/pci/pci-mt7620.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-03-12 10:35 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-07  4:17 [PATCH] MIPS: pci-mt7620: fix PLL lock check Ilya Lipnitskiy
2021-03-07  4:17 ` Ilya Lipnitskiy
2021-03-12 10:27 ` Thomas Bogendoerfer
2021-03-12 10:27   ` Thomas Bogendoerfer

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