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Mon, 8 Mar 2021 22:54:28 +0000 (GMT) Received: from v0005c16.aus.stglabs.ibm.com (unknown [9.211.41.147]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 8 Mar 2021 22:54:28 +0000 (GMT) From: Eddie James To: openbmc@lists.ozlabs.org Subject: [PATCH linux dev-5.10 29/35] hwmon: (pmbus) Add a PMBUS_NO_CAPABILITY platform data flag Date: Mon, 8 Mar 2021 16:54:13 -0600 Message-Id: <20210308225419.46530-30-eajames@linux.ibm.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210308225419.46530-1-eajames@linux.ibm.com> References: <20210308225419.46530-1-eajames@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-08_20:2021-03-08, 2021-03-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxscore=0 suspectscore=0 adultscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103080118 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Sender: "openbmc" Some PMBus chips don't respond with valid data when reading the CAPABILITY register. Add a flag that device drivers can set so that the PMBus core driver doesn't use CAPABILITY to determine it's behavior. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20201222152640.27749-2-eajames@linux.ibm.com Signed-off-by: Guenter Roeck --- drivers/hwmon/pmbus/pmbus_core.c | 8 +++++--- include/linux/pmbus.h | 9 +++++++++ 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c index 60ea917936a7..44c1a0a07509 100644 --- a/drivers/hwmon/pmbus/pmbus_core.c +++ b/drivers/hwmon/pmbus/pmbus_core.c @@ -2214,9 +2214,11 @@ static int pmbus_init_common(struct i2c_client *client, struct pmbus_data *data, } /* Enable PEC if the controller supports it */ - ret = i2c_smbus_read_byte_data(client, PMBUS_CAPABILITY); - if (ret >= 0 && (ret & PB_CAPABILITY_ERROR_CHECK)) - client->flags |= I2C_CLIENT_PEC; + if (!(data->flags & PMBUS_NO_CAPABILITY)) { + ret = i2c_smbus_read_byte_data(client, PMBUS_CAPABILITY); + if (ret >= 0 && (ret & PB_CAPABILITY_ERROR_CHECK)) + client->flags |= I2C_CLIENT_PEC; + } /* * Check if the chip is write protected. If it is, we can not clear diff --git a/include/linux/pmbus.h b/include/linux/pmbus.h index 1ea5bae708a1..12cbbf305969 100644 --- a/include/linux/pmbus.h +++ b/include/linux/pmbus.h @@ -34,6 +34,15 @@ */ #define PMBUS_WRITE_PROTECTED BIT(1) +/* + * PMBUS_NO_CAPABILITY + * + * Some PMBus chips don't respond with valid data when reading the CAPABILITY + * register. For such chips, this flag should be set so that the PMBus core + * driver doesn't use CAPABILITY to determine it's behavior. + */ +#define PMBUS_NO_CAPABILITY BIT(2) + struct pmbus_platform_data { u32 flags; /* Device specific flags */ -- 2.27.0