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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id b17sm8149195ejj.9.2021.03.09.06.27.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 06:27:03 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH RESEND 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower 512MiB hole Date: Tue, 9 Mar 2021 15:26:30 +0100 Message-Id: <20210309142630.728014-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309142630.728014-1-f4bug@amsat.org> References: <20210309142630.728014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Per the comment in the Malta board, the [0x0000.0000-0x2000.0000] range is decoded by the GT64120, so move the "empty_slot" there. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/gt64xxx_pci.c | 8 ++++++++ hw/mips/malta.c | 7 ------- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 43349d6837d..a3926e5cb8a 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -29,6 +29,7 @@ #include "hw/mips/mips.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" +#include "hw/misc/empty_slot.h" #include "hw/southbridge/piix.h" #include "migration/vmstate.h" #include "hw/intc/i8259.h" @@ -1206,6 +1207,13 @@ static void gt64120_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s, "gt64120-isd", 0x1000); + + /* + * The whole address space decoded by the GT-64120A doesn't generate + * exception when accessing invalid memory. Create an empty slot to + * emulate this feature. + */ + empty_slot_init("GT64120", 0, 0x20000000); } PCIBus *gt64120_register(qemu_irq *pic) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 9afc0b427bf..b2469f8ee78 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -56,7 +56,6 @@ #include "sysemu/runstate.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/misc/empty_slot.h" #include "sysemu/kvm.h" #include "hw/semihosting/semihost.h" #include "hw/mips/cps.h" @@ -1396,12 +1395,6 @@ void mips_malta_init(MachineState *machine) /* Northbridge */ pci_bus = gt64120_register(s->i8259); - /* - * The whole address space decoded by the GT-64120A doesn't generate - * exception when accessing invalid memory. Create an empty slot to - * emulate this feature. - */ - empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ dev = piix4_create(pci_bus, &isa_bus, &smbus); -- 2.26.2