All of lore.kernel.org
 help / color / mirror / Atom feed
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
	Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Swapnil Jakhade <sjakhade@cadence.com>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	Lokesh Vutla <lokeshvutla@ti.com>
Subject: [PATCH v6 11/13] dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock provider
Date: Wed, 10 Mar 2021 21:15:56 +0530	[thread overview]
Message-ID: <20210310154558.32078-12-kishon@ti.com> (raw)
In-Reply-To: <20210310154558.32078-1-kishon@ti.com>

Add #clock-cells binding to model Sierra as clock provider and include
clock IDs for PLL_CMNLC and PLL_CMNLC1.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/phy/phy-cadence-sierra.yaml        | 17 ++++++++++++++++-
 include/dt-bindings/phy/phy-cadence.h           |  4 ++++
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
index d210843863df..84383e2e0b34 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
@@ -26,6 +26,9 @@ properties:
   '#size-cells':
     const: 0
 
+  '#clock-cells':
+    const: 1
+
   resets:
     minItems: 1
     maxItems: 2
@@ -49,12 +52,24 @@ properties:
     const: serdes
 
   clocks:
-    maxItems: 2
+    minItems: 2
+    maxItems: 4
 
   clock-names:
+    minItems: 2
     items:
       - const: cmn_refclk_dig_div
       - const: cmn_refclk1_dig_div
+      - const: pll0_refclk
+      - const: pll1_refclk
+
+  assigned-clocks:
+    minItems: 1
+    maxItems: 2
+
+  assigned-clock-parents:
+    minItems: 1
+    maxItems: 2
 
   cdns,autoconf:
     type: boolean
diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h
index 4a5ea52a856f..4652bcb86265 100644
--- a/include/dt-bindings/phy/phy-cadence.h
+++ b/include/dt-bindings/phy/phy-cadence.h
@@ -13,4 +13,8 @@
 
 #define CDNS_TORRENT_REFCLK_DRIVER      0
 
+/* Sierra */
+#define CDNS_SIERRA_PLL_CMNLC		0
+#define CDNS_SIERRA_PLL_CMNLC1		1
+
 #endif /* _DT_BINDINGS_CADENCE_SERDES_H */
-- 
2.17.1


  parent reply	other threads:[~2021-03-10 15:47 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-10 15:45 [PATCH v6 00/13] PHY: Add support in Sierra to use external clock Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 01/13] phy: cadence: Sierra: Fix PHY power_on sequence Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 02/13] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() Kishon Vijay Abraham I
2021-03-15  5:47   ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 03/13] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes Kishon Vijay Abraham I
2021-03-15  5:50   ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 04/13] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 05/13] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Kishon Vijay Abraham I
2021-03-15  5:50   ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 06/13] phy: cadence: cadence-sierra: Move all reset_control_get*() " Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 07/13] phy: cadence: cadence-sierra: Explicitly request exclusive reset control Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 08/13] phy: cadence-torrent: Use a common header file for Cadence SERDES Kishon Vijay Abraham I
2021-03-15  5:51   ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 09/13] phy: cadence: cadence-sierra: Add array of input clocks in "struct cdns_sierra_phy" Kishon Vijay Abraham I
2021-03-15  5:52   ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 10/13] phy: cadence: cadence-sierra: Add missing clk_disable_unprepare() in .remove callback Kishon Vijay Abraham I
2021-03-10 15:45 ` Kishon Vijay Abraham I [this message]
2021-03-10 15:45 ` [PATCH v6 12/13] phy: cadence: phy-cadence-sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Kishon Vijay Abraham I
2021-03-15  6:15   ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 13/13] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Kishon Vijay Abraham I
2021-03-15  5:54   ` Swapnil Kashinath Jakhade

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210310154558.32078-12-kishon@ti.com \
    --to=kishon@ti.com \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=lokeshvutla@ti.com \
    --cc=p.zabel@pengutronix.de \
    --cc=robh+dt@kernel.org \
    --cc=sjakhade@cadence.com \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.