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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 14/27] target/mips: Rename decode_opc_mxu() as decode_ase_mxu()
Date: Sat, 13 Mar 2021 20:48:16 +0100	[thread overview]
Message-ID: <20210313194829.2193621-15-f4bug@amsat.org> (raw)
In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org>

Use "decode_{isa,ase,ext}_$name()" function name pattern for
public decodetree entrypoints.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 17cf608d0bd..5c1909f0ba4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -25779,7 +25779,7 @@ static void decode_opc_mxu__pool19(DisasContext *ctx)
 /*
  * Main MXU decoding function
  */
-static void decode_opc_mxu(DisasContext *ctx, uint32_t insn)
+static void decode_ase_mxu(DisasContext *ctx, uint32_t insn)
 {
     uint32_t opcode = extract32(insn, 0, 6);
 
@@ -26984,7 +26984,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
             if (MASK_SPECIAL2(ctx->opcode) == OPC_MUL) {
                 gen_arith(ctx, OPC_MUL, rd, rs, rt);
             } else {
-                decode_opc_mxu(ctx, ctx->opcode);
+                decode_ase_mxu(ctx, ctx->opcode);
             }
             break;
         }
-- 
2.26.2



  parent reply	other threads:[~2021-03-13 19:54 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-13 19:48 [PULL 00/27] MIPS patches for 2021-03-13 Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 01/27] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize() Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 02/27] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 03/27] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 04/27] hw/mips/gt64xxx: Rename trace events related to interrupt registers Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 05/27] hw/mips/gt64xxx: Trace accesses to ISD registers Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 06/27] target/mips/meson: Introduce mips_tcg source set Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 07/27] target/mips/meson: Restrict mips-semi.c to TCG Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 08/27] target/mips: Rewrite complex ifdef'ry Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 09/27] target/mips: Remove XBurst Media eXtension Unit dead code Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 10/27] target/mips: Remove unused CPUMIPSState* from MXU functions Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 11/27] target/mips: Pass instruction opcode to decode_opc_mxu() Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 12/27] target/mips: Use OPC_MUL instead of OPC__MXU_MUL Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 13/27] target/mips: Move MUL opcode check from decode_mxu() to decode_legacy() Philippe Mathieu-Daudé
2021-03-13 19:48 ` Philippe Mathieu-Daudé [this message]
2021-03-13 19:48 ` [PULL 15/27] target/mips: Convert decode_ase_mxu() to decodetree prototype Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 16/27] target/mips: Simplify decode_opc_mxu() ifdef'ry Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 17/27] target/mips: Introduce mxu_translate_init() helper Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 18/27] target/mips: Extract MXU code to new mxu_translate.c file Philippe Mathieu-Daudé
2021-03-15 21:33   ` Peter Maydell
2021-03-15 22:43     ` Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 19/27] target/mips: Use gen_load_gpr[_hi]() when possible Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 20/27] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 21/27] target/mips/tx79: Move MTHI1 / MTLO1 " Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 22/27] target/mips/translate: Make gen_rdhwr() public Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 23/27] target/mips/translate: Simplify PCPYH using deposit_i64() Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 24/27] target/mips/tx79: Move PCPYH opcode to decodetree Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 25/27] target/mips/tx79: Move PCPYLD / PCPYUD opcodes " Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 26/27] target/mips: Remove 'C790 Multimedia Instructions' dead code Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 27/27] target/mips/tx79: Salvage instructions description comment Philippe Mathieu-Daudé
2021-03-15 15:34 ` [PULL 00/27] MIPS patches for 2021-03-13 Peter Maydell

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