From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A40B4C433DB for ; Wed, 17 Mar 2021 04:13:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C68C64EE2 for ; Wed, 17 Mar 2021 04:13:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4C68C64EE2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6902F6E4C9; Wed, 17 Mar 2021 04:13:51 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 45C216E4C9; Wed, 17 Mar 2021 04:13:50 +0000 (UTC) IronPort-SDR: M4cTSEfzZusDJGPC8YSlmuMjrQPgHg/7fGRkKwwLH5rsRPBUpSQfYcommXCOCIi4SCUg2dorgS S3+wdJW4EF+g== X-IronPort-AV: E=McAfee;i="6000,8403,9925"; a="188746440" X-IronPort-AV: E=Sophos;i="5.81,254,1610438400"; d="scan'208";a="188746440" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2021 21:13:49 -0700 IronPort-SDR: nlQL0RdzOSERrOoBCLE1E14gmCnaKUHvj7Z/M53qI9Obsi8h/G2EAeDH/WA5lwstdN6GBqqmHO 2DOWICF9O8iw== X-IronPort-AV: E=Sophos;i="5.81,254,1610438400"; d="scan'208";a="511595975" Received: from mlarue-mobl.amr.corp.intel.com (HELO ldmartin-desk2) ([10.212.239.229]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2021 21:13:49 -0700 Date: Tue, 16 Mar 2021 21:13:47 -0700 From: Lucas De Marchi To: Swathi Dhanavanthri Subject: Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_14011060649 Message-ID: <20210317041347.fdogwipcpk2pjj4n@ldmartin-desk2> X-Patchwork-Hint: comment References: <20210316235746.19900-1-swathi.dhanavanthri@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210316235746.19900-1-swathi.dhanavanthri@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" +Daniel On Tue, Mar 16, 2021 at 04:57:46PM -0700, Swathi Dhanavanthri wrote: >This is a permanent workaround for TGL,RKL,DG1 and ADLS. > >Signed-off-by: Swathi Dhanavanthri >--- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > 2 files changed, 30 insertions(+) > >diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >index 3b4a7da60f0b..01f34a6bdf3e 100644 >--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >@@ -1117,11 +1117,38 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); > } > >+/* >+ * Though there are per-engine instances of these registers, >+ * they retain their value through engine resets and should >+ * only be provided on the GT workaround list rather than >+ * the engine-specific workaround list. >+ * extra blank line here. Otherwise: Reviewed-by: Lucas De Marchi Daniel, where/how should we land this and next pending WAs? I have 3 more already reviewed that I need to re-submit to dri-devel. Should we get an ack and merge intel-gt-next? Or maybe create a topic branch to be merged somewhere later? thanks Lucas De Marchi >+ */ >+static void >+wa_14011060649(struct drm_i915_private *i915, struct i915_wa_list *wal) >+{ >+ struct intel_engine_cs *engine; >+ struct intel_gt *gt = &i915->gt; >+ int id; >+ >+ for_each_engine(engine, gt, id) { >+ if ((engine->class != VIDEO_DECODE_CLASS) || >+ (engine->instance % 2)) >+ continue; >+ >+ wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), >+ IECPUNIT_CLKGATE_DIS); >+ } >+} >+ > static void > gen12_gt_workarounds_init(struct drm_i915_private *i915, > struct i915_wa_list *wal) > { > wa_init_mcr(i915, wal); >+ >+ /* Wa_14011060649:tgl,rkl,dg1,adls */ >+ wa_14011060649(i915, wal); > } > > static void >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >index e5dd0203991b..cc60556306e2 100644 >--- a/drivers/gpu/drm/i915/i915_reg.h >+++ b/drivers/gpu/drm/i915/i915_reg.h >@@ -2715,6 +2715,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ > #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ > >+#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) >+#define IECPUNIT_CLKGATE_DIS REG_BIT(22) >+ > #define ERROR_GEN6 _MMIO(0x40a0) > #define GEN7_ERR_INT _MMIO(0x44040) > #define ERR_INT_POISON (1 << 31) >-- >2.20.1 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA860C433E0 for ; Wed, 17 Mar 2021 04:13:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B10664E4E for ; Wed, 17 Mar 2021 04:13:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8B10664E4E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F02B6E4CA; Wed, 17 Mar 2021 04:13:51 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 45C216E4C9; Wed, 17 Mar 2021 04:13:50 +0000 (UTC) IronPort-SDR: M4cTSEfzZusDJGPC8YSlmuMjrQPgHg/7fGRkKwwLH5rsRPBUpSQfYcommXCOCIi4SCUg2dorgS S3+wdJW4EF+g== X-IronPort-AV: E=McAfee;i="6000,8403,9925"; a="188746440" X-IronPort-AV: E=Sophos;i="5.81,254,1610438400"; d="scan'208";a="188746440" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2021 21:13:49 -0700 IronPort-SDR: nlQL0RdzOSERrOoBCLE1E14gmCnaKUHvj7Z/M53qI9Obsi8h/G2EAeDH/WA5lwstdN6GBqqmHO 2DOWICF9O8iw== X-IronPort-AV: E=Sophos;i="5.81,254,1610438400"; d="scan'208";a="511595975" Received: from mlarue-mobl.amr.corp.intel.com (HELO ldmartin-desk2) ([10.212.239.229]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2021 21:13:49 -0700 Date: Tue, 16 Mar 2021 21:13:47 -0700 From: Lucas De Marchi To: Swathi Dhanavanthri Message-ID: <20210317041347.fdogwipcpk2pjj4n@ldmartin-desk2> X-Patchwork-Hint: comment References: <20210316235746.19900-1-swathi.dhanavanthri@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210316235746.19900-1-swathi.dhanavanthri@intel.com> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_14011060649 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" +Daniel On Tue, Mar 16, 2021 at 04:57:46PM -0700, Swathi Dhanavanthri wrote: >This is a permanent workaround for TGL,RKL,DG1 and ADLS. > >Signed-off-by: Swathi Dhanavanthri >--- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > 2 files changed, 30 insertions(+) > >diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >index 3b4a7da60f0b..01f34a6bdf3e 100644 >--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >@@ -1117,11 +1117,38 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); > } > >+/* >+ * Though there are per-engine instances of these registers, >+ * they retain their value through engine resets and should >+ * only be provided on the GT workaround list rather than >+ * the engine-specific workaround list. >+ * extra blank line here. Otherwise: Reviewed-by: Lucas De Marchi Daniel, where/how should we land this and next pending WAs? I have 3 more already reviewed that I need to re-submit to dri-devel. Should we get an ack and merge intel-gt-next? Or maybe create a topic branch to be merged somewhere later? thanks Lucas De Marchi >+ */ >+static void >+wa_14011060649(struct drm_i915_private *i915, struct i915_wa_list *wal) >+{ >+ struct intel_engine_cs *engine; >+ struct intel_gt *gt = &i915->gt; >+ int id; >+ >+ for_each_engine(engine, gt, id) { >+ if ((engine->class != VIDEO_DECODE_CLASS) || >+ (engine->instance % 2)) >+ continue; >+ >+ wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), >+ IECPUNIT_CLKGATE_DIS); >+ } >+} >+ > static void > gen12_gt_workarounds_init(struct drm_i915_private *i915, > struct i915_wa_list *wal) > { > wa_init_mcr(i915, wal); >+ >+ /* Wa_14011060649:tgl,rkl,dg1,adls */ >+ wa_14011060649(i915, wal); > } > > static void >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >index e5dd0203991b..cc60556306e2 100644 >--- a/drivers/gpu/drm/i915/i915_reg.h >+++ b/drivers/gpu/drm/i915/i915_reg.h >@@ -2715,6 +2715,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ > #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ > >+#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) >+#define IECPUNIT_CLKGATE_DIS REG_BIT(22) >+ > #define ERROR_GEN6 _MMIO(0x40a0) > #define GEN7_ERR_INT _MMIO(0x44040) > #define ERR_INT_POISON (1 << 31) >-- >2.20.1 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx