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[84.3.50.134]) by smtp.gmail.com with ESMTPSA id h10sm24764669wrp.22.2021.03.17.02.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 02:18:03 -0700 (PDT) Sender: Ingo Molnar Date: Wed, 17 Mar 2021 10:18:00 +0100 From: Ingo Molnar To: "Yu, Yu-cheng" Cc: Peter Zijlstra , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin , Weijiang Yang , Pengfei Xu , Haitao Huang Subject: Re: [PATCH v23 00/28] Control-flow Enforcement: Shadow Stack Message-ID: <20210317091800.GA1461644@gmail.com> References: <20210316151054.5405-1-yu-cheng.yu@intel.com> <20210316211552.GU4746@worktop.programming.kicks-ass.net> <90e453ee-377b-0342-55f9-9412940262f2@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <90e453ee-377b-0342-55f9-9412940262f2@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Yu, Yu-cheng wrote: > On 3/16/2021 2:15 PM, Peter Zijlstra wrote: > > On Tue, Mar 16, 2021 at 08:10:26AM -0700, Yu-cheng Yu wrote: > > > Control-flow Enforcement (CET) is a new Intel processor feature that blocks > > > return/jump-oriented programming attacks. Details are in "Intel 64 and > > > IA-32 Architectures Software Developer's Manual" [1]. > > > > > > CET can protect applications and the kernel. This series enables only > > > application-level protection, and has three parts: > > > > > > - Shadow stack [2], > > > - Indirect branch tracking [3], and > > > - Selftests [4]. > > > > CET is marketing; afaict SS and IBT are 100% independent and there's no > > reason what so ever to have them share any code, let alone a Kconfig > > knob. > > We used to have shadow stack and ibt under separate Kconfig options, but in > a few places they actually share same code path, such as the XSAVES > supervisor states and ELF header for example. Anyways I will be happy to > make changes again if there is agreement. I was look at: x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states didn't see any IBT logic - it's essentially all shadow stack state. Which is not surprising, forward call edge integrity protection (IBT) requires very little state, does it? With IBT there's no nesting, no stack - the IBT state machine basically requires the next instruction to be and ENDBR instruction, and that's essentially it, right? Thanks, Ingo