All of lore.kernel.org
 help / color / mirror / Atom feed
From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Roman Bolshakov <r.bolshakov@yadro.com>,
	Claudio Fontana <cfontana@suse.de>,
	Eduardo Habkost <ehabkost@redhat.com>,
	qemu-devel@nongnu.org
Subject: [RFC v9 40/50] accel: add double dispatch mechanism for class initialization
Date: Wed, 17 Mar 2021 19:30:03 +0100	[thread overview]
Message-ID: <20210317183013.25772-41-cfontana@suse.de> (raw)
In-Reply-To: <20210317183013.25772-1-cfontana@suse.de>

while on x86 all CPU classes can use the same set of TCGCPUOps,
on ARM the right accel behavior depends on the type of the CPU.

So we need a way to specialize the accel behavior according to
the CPU. Therefore, add a second initialization, after the
accel_cpu->cpu_class_init, that allows to do this.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Cc: Paolo Bonzini <pbonzini@redhat.com>
---
 include/hw/core/cpu.h     |  6 ++++++
 accel/accel-common.c      | 12 ++++++++++++
 target/i386/tcg/tcg-cpu.c |  8 +++++++-
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c68bc3ba8a..d45f78290e 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -192,6 +192,12 @@ struct CPUClass {
 
     /* when TCG is not available, this pointer is NULL */
     struct TCGCPUOps *tcg_ops;
+
+    /*
+     * if not NULL, this is called in order for the CPUClass to initialize
+     * class data that depends on the accelerator, see accel/accel-common.c.
+     */
+    void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc);
 };
 
 /*
diff --git a/accel/accel-common.c b/accel/accel-common.c
index d77c09d7b5..2103397d5e 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -54,10 +54,22 @@ static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)
     CPUClass *cc = CPU_CLASS(klass);
     AccelCPUClass *accel_cpu = opaque;
 
+    /*
+     * double dispatch. The first callback allows the accel cpu
+     * to run initializations for the CPU,
+     * the second one allows the CPU to customize the accel cpu
+     * behavior according to the CPU.
+     *
+     * The second is currently only used by TCG, to specialize the
+     * TCGCPUOps depending on the CPU type.
+     */
     cc->accel_cpu = accel_cpu;
     if (accel_cpu->cpu_class_init) {
         accel_cpu->cpu_class_init(cc);
     }
+    if (cc->init_accel_cpu) {
+        cc->init_accel_cpu(accel_cpu, cc);
+    }
 }
 
 /* initialize the arch-specific accel CpuClass interfaces */
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index e311f52855..ba39531aa5 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -69,11 +69,17 @@ static struct TCGCPUOps x86_tcg_ops = {
 #endif /* !CONFIG_USER_ONLY */
 };
 
-static void tcg_cpu_class_init(CPUClass *cc)
+static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
 {
+    /* for x86, all cpus use the same set of operations */
     cc->tcg_ops = &x86_tcg_ops;
 }
 
+static void tcg_cpu_class_init(CPUClass *cc)
+{
+    cc->init_accel_cpu = tcg_cpu_init_ops;
+}
+
 /*
  * TCG-specific defaults that override all CPU models when using TCG
  */
-- 
2.26.2



  parent reply	other threads:[~2021-03-17 19:04 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-17 18:29 [RFC v9 00/50] arm cleanup experiment for kvm-only build Claudio Fontana
2021-03-17 18:29 ` [RFC v9 01/50] target/arm: move translate modules to tcg/ Claudio Fontana
2021-03-17 18:29 ` [RFC v9 02/50] target/arm: move helpers " Claudio Fontana
2021-03-17 18:29 ` [RFC v9 03/50] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-03-17 18:29 ` [RFC v9 04/50] target/arm: tcg: add sysemu and user subsirs Claudio Fontana
2021-03-17 18:29 ` [RFC v9 05/50] target/arm: only build psci for TCG Claudio Fontana
2021-03-17 18:29 ` [RFC v9 06/50] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-03-17 18:29 ` [RFC v9 07/50] target/arm: move physical address translation to cpu-mmu Claudio Fontana
2021-03-17 18:29 ` [RFC v9 08/50] target/arm: cpu-mmu: fix comment style Claudio Fontana
2021-03-17 18:29 ` [RFC v9 09/50] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-03-17 18:29 ` [RFC v9 10/50] target/arm: cpregs: fix style (mostly just comments) Claudio Fontana
2021-03-17 18:29 ` [RFC v9 11/50] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-03-17 18:29 ` [RFC v9 12/50] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-03-17 18:29 ` [RFC v9 13/50] target/arm: kvm: add stubs for some helpers Claudio Fontana
2021-03-17 18:29 ` [RFC v9 14/50] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-03-17 18:29 ` [RFC v9 15/50] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-03-17 18:29 ` [RFC v9 16/50] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-03-17 18:29 ` [RFC v9 17/50] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-03-17 18:29 ` [RFC v9 18/50] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-03-17 18:29 ` [RFC v9 19/50] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-03-17 18:29 ` [RFC v9 20/50] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-03-17 18:29 ` [RFC v9 21/50] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-03-17 18:29 ` [RFC v9 22/50] target/arm: split a15 cpu model and 32bit class functions to cpu32.c Claudio Fontana
2021-03-17 18:29 ` [RFC v9 23/50] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-03-17 18:29 ` [RFC v9 24/50] target/arm: refactor exception and cpu code Claudio Fontana
2021-03-17 18:29 ` [RFC v9 25/50] target/arm: cpu: fix style Claudio Fontana
2021-03-17 18:29 ` [RFC v9 26/50] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-03-17 18:29 ` [RFC v9 27/50] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-03-17 18:29 ` [RFC v9 28/50] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-03-17 18:29 ` [RFC v9 29/50] target/arm: cleanup cpu includes Claudio Fontana
2021-03-17 19:01   ` Philippe Mathieu-Daudé
2021-03-18  8:32     ` Claudio Fontana
2021-03-17 18:29 ` [RFC v9 30/50] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-03-17 18:29 ` [RFC v9 31/50] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-03-17 18:29 ` [RFC v9 32/50] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-03-17 18:29 ` [RFC v9 33/50] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-03-17 18:29 ` [RFC v9 34/50] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-03-17 18:29 ` [RFC v9 35/50] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-03-17 18:29 ` [RFC v9 36/50] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-03-17 18:30 ` [RFC v9 37/50] target/arm: create kvm cpu accel class Claudio Fontana
2021-03-17 18:30 ` [RFC v9 38/50] target/arm: move kvm cpu properties setting to kvm-cpu Claudio Fontana
2021-03-18 10:46   ` Claudio Fontana
2021-03-17 18:30 ` [RFC v9 39/50] accel: move call to accel_init_interfaces Claudio Fontana
2021-03-17 18:30 ` Claudio Fontana [this message]
2021-03-17 18:30 ` [RFC v9 41/50] target/arm: add tcg cpu accel class Claudio Fontana
2021-03-17 18:30 ` [RFC v9 42/50] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-03-17 18:30 ` [RFC v9 43/50] target/arm: cpu-sve: new module Claudio Fontana
2021-03-17 18:30 ` [RFC v9 44/50] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-03-17 18:30 ` [RFC v9 45/50] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-03-17 18:30 ` [RFC v9 46/50] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-03-17 18:30 ` [RFC v9 47/50] target/arm: cpu-exceptions: new module Claudio Fontana
2021-03-17 18:30 ` [RFC v9 48/50] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-03-17 18:30 ` [RFC v9 49/50] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-03-17 18:30 ` [RFC v9 50/50] target/arm: refactor arm_cpu_finalize_features into cpu64 Claudio Fontana

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210317183013.25772-41-cfontana@suse.de \
    --to=cfontana@suse.de \
    --cc=alex.bennee@linaro.org \
    --cc=ehabkost@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=philmd@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=r.bolshakov@yadro.com \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.