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From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Roman Bolshakov <r.bolshakov@yadro.com>,
	Claudio Fontana <cfontana@suse.de>,
	Eduardo Habkost <ehabkost@redhat.com>,
	qemu-devel@nongnu.org
Subject: [RFC v10 40/49] target/arm: move TCG gt timer creation code in tcg/
Date: Mon, 22 Mar 2021 15:01:57 +0100	[thread overview]
Message-ID: <20210322140206.9513-41-cfontana@suse.de> (raw)
In-Reply-To: <20210322140206.9513-1-cfontana@suse.de>

we need to be careful not to use

if (tcg_enabled())

here, because of the VMSTATE definitions in machine.c,
which are only protected by CONFIG_TCG, and thus
it would break the --enable-tcg --enable-kvm build.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
 target/arm/tcg/tcg-cpu.h        |  1 +
 target/arm/cpu.c                | 28 +++-------------------
 target/arm/tcg/sysemu/tcg-cpu.c | 41 +++++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+), 25 deletions(-)

diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h
index dd08587949..3e4ce2c355 100644
--- a/target/arm/tcg/tcg-cpu.h
+++ b/target/arm/tcg/tcg-cpu.h
@@ -33,6 +33,7 @@ void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu, CPUClass *cc);
 /* Do semihosting call and set the appropriate return value. */
 void tcg_handle_semihosting(CPUState *cs);
 bool tcg_cpu_realizefn(CPUState *cs, Error **errp);
+bool tcg_cpu_realize_gt_timers(CPUState *cs, Error **errp);
 
 #endif /* !CONFIG_USER_ONLY */
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 9248e096df..d523d9b68d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -859,32 +859,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     bool no_aa32 = false;
 
 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
-    {
-        uint64_t scale;
-
-        if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
-            if (!cpu->gt_cntfrq_hz) {
-                error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
-                           cpu->gt_cntfrq_hz);
-                return;
-            }
-            scale = gt_cntfrq_period_ns(cpu);
-        } else {
-            scale = GTIMER_SCALE;
-        }
-
-        cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
-                                               arm_gt_ptimer_cb, cpu);
-        cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
-                                               arm_gt_vtimer_cb, cpu);
-        cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
-                                              arm_gt_htimer_cb, cpu);
-        cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
-                                              arm_gt_stimer_cb, cpu);
-        cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
-                                                  arm_gt_hvtimer_cb, cpu);
+    if (!tcg_cpu_realize_gt_timers(cs, errp)) {
+        return;
     }
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
+#endif
 
     cpu_exec_realizefn(cs, &local_err);
     if (local_err != NULL) {
diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cpu.c
index 115ac523dc..777eb948df 100644
--- a/target/arm/tcg/sysemu/tcg-cpu.c
+++ b/target/arm/tcg/sysemu/tcg-cpu.c
@@ -54,6 +54,46 @@ void tcg_handle_semihosting(CPUState *cs)
     }
 }
 
+/*
+ * we cannot use tcg_enabled() to condition the call to this function,
+ * due to the fields VMSTATE definitions in machine.c : it would break
+ * the --enable-tcg --enable-kvm build. We need to run this code whenever
+ * CONFIG_TCG is true, regardless of the chosen accelerator.
+ *
+ * So we cannot call this from tcg_cpu_realizefn, as this needs to
+ * be called whenever TCG is built-in, regardless of whether it is
+ * enabled or not.
+ */
+bool tcg_cpu_realize_gt_timers(CPUState *cs, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    uint64_t scale;
+
+    if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
+        if (!cpu->gt_cntfrq_hz) {
+            error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
+                       cpu->gt_cntfrq_hz);
+            return false;
+        }
+        scale = gt_cntfrq_period_ns(cpu);
+    } else {
+        scale = GTIMER_SCALE;
+    }
+
+    cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+                                           arm_gt_ptimer_cb, cpu);
+    cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+                                           arm_gt_vtimer_cb, cpu);
+    cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+                                          arm_gt_htimer_cb, cpu);
+    cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+                                          arm_gt_stimer_cb, cpu);
+    cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+                                              arm_gt_hvtimer_cb, cpu);
+    return true;
+}
+
 bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
 {
     ARMCPU *cpu = ARM_CPU(cs);
@@ -75,5 +115,6 @@ bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
             return false;
         }
     }
+
     return true;
 }
-- 
2.26.2



  parent reply	other threads:[~2021-03-22 14:42 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-22 14:01 [RFC v10 00/49] arm cleanup experiment for kvm-only build Claudio Fontana
2021-03-22 14:01 ` [RFC v10 01/49] target/arm: move translate modules to tcg/ Claudio Fontana
2021-03-22 16:27   ` Alex Bennée
2021-03-22 14:01 ` [RFC v10 02/49] target/arm: move helpers " Claudio Fontana
2021-03-22 16:29   ` Alex Bennée
2021-03-22 14:01 ` [RFC v10 03/49] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-03-22 16:32   ` Alex Bennée
2021-03-22 14:01 ` [RFC v10 04/49] target/arm: tcg: add sysemu and user subsirs Claudio Fontana
2021-03-22 16:32   ` Alex Bennée
2021-03-22 14:01 ` [RFC v10 05/49] target/arm: only build psci for TCG Claudio Fontana
2021-03-22 14:01 ` [RFC v10 06/49] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-03-22 17:17   ` Alex Bennée
2021-03-22 14:01 ` [RFC v10 07/49] target/arm: move physical address translation to cpu-mmu Claudio Fontana
2021-03-22 14:01 ` [RFC v10 08/49] target/arm: cpu-mmu: fix comment style Claudio Fontana
2021-03-22 14:01 ` [RFC v10 09/49] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-03-22 14:01 ` [RFC v10 10/49] target/arm: cpregs: fix style (mostly just comments) Claudio Fontana
2021-03-22 14:01 ` [RFC v10 11/49] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-03-22 14:01 ` [RFC v10 12/49] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-03-22 14:01 ` [RFC v10 13/49] target/arm: kvm: add stubs for some helpers Claudio Fontana
2021-03-22 14:01 ` [RFC v10 14/49] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-03-22 14:01 ` [RFC v10 15/49] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-03-22 14:01 ` [RFC v10 16/49] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-03-22 14:01 ` [RFC v10 17/49] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-03-22 14:01 ` [RFC v10 18/49] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-03-22 14:01 ` [RFC v10 19/49] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-03-22 14:01 ` [RFC v10 20/49] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-03-22 14:01 ` [RFC v10 21/49] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-03-22 14:01 ` [RFC v10 22/49] target/arm: split a15 cpu model and 32bit class functions to cpu32.c Claudio Fontana
2021-03-22 14:01 ` [RFC v10 23/49] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-03-22 14:01 ` [RFC v10 24/49] target/arm: refactor exception and cpu code Claudio Fontana
2021-03-22 14:01 ` [RFC v10 25/49] target/arm: cpu: fix style Claudio Fontana
2021-03-22 14:01 ` [RFC v10 26/49] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-03-22 14:01 ` [RFC v10 27/49] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-03-22 14:01 ` [RFC v10 28/49] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-03-22 14:01 ` [RFC v10 29/49] target/arm: cleanup cpu includes Claudio Fontana
2021-03-22 14:01 ` [RFC v10 30/49] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-03-22 14:01 ` [RFC v10 31/49] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-03-22 14:01 ` [RFC v10 32/49] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-03-22 14:01 ` [RFC v10 33/49] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-03-22 14:01 ` [RFC v10 34/49] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-03-22 14:01 ` [RFC v10 35/49] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-03-22 14:01 ` [RFC v10 36/49] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-03-22 14:01 ` [RFC v10 37/49] target/arm: create kvm cpu accel class Claudio Fontana
2021-03-22 14:01 ` [RFC v10 38/49] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-03-22 14:01 ` [RFC v10 39/49] target/arm: add tcg cpu accel class Claudio Fontana
2021-03-23 19:26   ` Alex Bennée
2021-03-23 19:33     ` Claudio Fontana
2021-03-22 14:01 ` Claudio Fontana [this message]
2021-03-22 14:01 ` [RFC v10 41/49] target/arm: cpu-sve: new module Claudio Fontana
2021-03-22 14:01 ` [RFC v10 42/49] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-03-22 14:02 ` [RFC v10 43/49] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-03-22 14:02 ` [RFC v10 44/49] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-03-22 14:02 ` [RFC v10 45/49] target/arm: cpu-exceptions: new module Claudio Fontana
2021-03-22 14:02 ` [RFC v10 46/49] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-03-22 14:02 ` [RFC v10 47/49] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-03-22 14:02 ` [RFC v10 48/49] target/arm: refactor arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-03-22 14:02 ` [RFC v10 49/49] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-03-23 18:35 ` [RFC v10 00/49] arm cleanup experiment for kvm-only build Alex Bennée
2021-03-23 19:20   ` Claudio Fontana
2021-03-23 19:38     ` Richard Henderson

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