[PATCH v2 0/3] AM64x HwSpinlock and Mailbox DT nodes

[PATCH v2 0/3] AM64x HwSpinlock and Mailbox DT nodes

[Suman Anna]

Hi Nishanth,

The following is a minor revision of the HwSpinlock and Mailbox DT nodes
series [1] for AM64x SoCs on both AM64x-EVM and AM64x-SK boards. The main
change is the squashing of the individual board dts patches into a single
patch as per your request, and rebasing on your current latest ti-k3-dts-next
branch HEAD commit e4e4e89482ea ("arm64: dts: ti: k3-am64-evm/sk: Add OSPI
flash DT node"). I have also picked up Gowtham's Reviewed-by tags.

The code changes are exactly identical to v1, other than the rebase and
squash.

regards
Suman

[1] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210317230946.23675-1-s-anna@ti.com/

Suman Anna (3):
  arm64: dts: ti: k3-am64-main: Add hwspinlock node
  arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes
  arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes

 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 64 ++++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-evm.dts  | 43 ++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts   | 43 ++++++++++++++++
 3 files changed, 150 insertions(+)

-- 
2.30.1

[PATCH v2 0/3] AM64x HwSpinlock and Mailbox DT nodes

[Suman Anna]

Hi Nishanth,

The following is a minor revision of the HwSpinlock and Mailbox DT nodes
series [1] for AM64x SoCs on both AM64x-EVM and AM64x-SK boards. The main
change is the squashing of the individual board dts patches into a single
patch as per your request, and rebasing on your current latest ti-k3-dts-next
branch HEAD commit e4e4e89482ea ("arm64: dts: ti: k3-am64-evm/sk: Add OSPI
flash DT node"). I have also picked up Gowtham's Reviewed-by tags.

The code changes are exactly identical to v1, other than the rebase and
squash.

regards
Suman

[1] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210317230946.23675-1-s-anna@ti.com/

Suman Anna (3):
  arm64: dts: ti: k3-am64-main: Add hwspinlock node
  arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes
  arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes

 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 64 ++++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-evm.dts  | 43 ++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts   | 43 ++++++++++++++++
 3 files changed, 150 insertions(+)

-- 
2.30.1


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[PATCH v2 1/3] arm64: dts: ti: k3-am64-main: Add hwspinlock node

[Suman Anna]

The AM64x SoC contains a HwSpinlock IP instance that is a minor variant
of the IP on existing TI K3 SoCs such as AM65x, J721E or J7200 SoCs.
Add the DT node for this on AM64x SoCs. The node is present within the
MAIN domain, and is added as a child node under the cbass_main node.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Gowtham Tammana <g-tammana@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index a03b66456062..b34b98969b47 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -563,4 +563,10 @@ ospi0: spi@fc40000 {
 			power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 		};
 	};
+
+	hwspinlock: spinlock@2a000000 {
+		compatible = "ti,am64-hwspinlock";
+		reg = <0x00 0x2a000000 0x00 0x1000>;
+		#hwlock-cells = <1>;
+	};
 };
-- 
2.30.1

[PATCH v2 1/3] arm64: dts: ti: k3-am64-main: Add hwspinlock node

[Suman Anna]

The AM64x SoC contains a HwSpinlock IP instance that is a minor variant
of the IP on existing TI K3 SoCs such as AM65x, J721E or J7200 SoCs.
Add the DT node for this on AM64x SoCs. The node is present within the
MAIN domain, and is added as a child node under the cbass_main node.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Gowtham Tammana <g-tammana@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index a03b66456062..b34b98969b47 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -563,4 +563,10 @@ ospi0: spi@fc40000 {
 			power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 		};
 	};
+
+	hwspinlock: spinlock@2a000000 {
+		compatible = "ti,am64-hwspinlock";
+		reg = <0x00 0x2a000000 0x00 0x1000>;
+		#hwlock-cells = <1>;
+	};
 };
-- 
2.30.1


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[PATCH v2 2/3] arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes

[Suman Anna]

The AM64 MAIN domain contains a Mailbox IP instance with multiple
clusters, and is a variant of the IP on current AM65x and J721E
SoCs. The AM64x SoC has only 8 clusters with no interrupts routed
to the A53 core on the first 2 clusters. The interrupt outputs
from the IP do not go through any Interrupt Routers and are
hard-wired to each processor, with only couple of interrupts
from each cluster reaching the A53 core.

Add all the Mailbox clusters that generate interrupts towards the
A53 core as their own nodes under the cbass_main node instead of
creating an almost empty parent node for the Mailbox IP and the
clusters as its child nodes. All these nodes are enabled by default
in the base dtsi file, but any cluster that does not define any
child sub-mailbox nodes should be disabled in the corresponding
board dts files.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Gowtham Tammana <g-tammana@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 58 ++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index b34b98969b47..139179b24635 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -569,4 +569,62 @@ hwspinlock: spinlock@2a000000 {
 		reg = <0x00 0x2a000000 0x00 0x1000>;
 		#hwlock-cells = <1>;
 	};
+
+	mailbox0_cluster2: mailbox@29020000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29020000 0x00 0x200>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster3: mailbox@29030000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29030000 0x00 0x200>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster4: mailbox@29040000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29040000 0x00 0x200>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster5: mailbox@29050000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29050000 0x00 0x200>;
+		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster6: mailbox@29060000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29060000 0x00 0x200>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster7: mailbox@29070000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29070000 0x00 0x200>;
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
 };
-- 
2.30.1

[PATCH v2 2/3] arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes

[Suman Anna]

The AM64 MAIN domain contains a Mailbox IP instance with multiple
clusters, and is a variant of the IP on current AM65x and J721E
SoCs. The AM64x SoC has only 8 clusters with no interrupts routed
to the A53 core on the first 2 clusters. The interrupt outputs
from the IP do not go through any Interrupt Routers and are
hard-wired to each processor, with only couple of interrupts
from each cluster reaching the A53 core.

Add all the Mailbox clusters that generate interrupts towards the
A53 core as their own nodes under the cbass_main node instead of
creating an almost empty parent node for the Mailbox IP and the
clusters as its child nodes. All these nodes are enabled by default
in the base dtsi file, but any cluster that does not define any
child sub-mailbox nodes should be disabled in the corresponding
board dts files.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Gowtham Tammana <g-tammana@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 58 ++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index b34b98969b47..139179b24635 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -569,4 +569,62 @@ hwspinlock: spinlock@2a000000 {
 		reg = <0x00 0x2a000000 0x00 0x1000>;
 		#hwlock-cells = <1>;
 	};
+
+	mailbox0_cluster2: mailbox@29020000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29020000 0x00 0x200>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster3: mailbox@29030000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29030000 0x00 0x200>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster4: mailbox@29040000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29040000 0x00 0x200>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster5: mailbox@29050000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29050000 0x00 0x200>;
+		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster6: mailbox@29060000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29060000 0x00 0x200>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster7: mailbox@29070000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29070000 0x00 0x200>;
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
 };
-- 
2.30.1


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[PATCH v2 3/3] arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes

[Suman Anna]

Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the AM64x SoCs for the AM642 EVM
and AM642 SK boards. These include the R5F remote processors in the two
dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; and a
M4 processor in the MCU safety island.

These sub-mailbox nodes utilize the System Mailbox clusters 2, 4 and 6.
The remaining clusters 3, 5 and 7 are currently not used, and so are
disabled. Clusters 0 and 1 were never added to the dts file as they do
not support interrupts towards the A53 core.

The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. The R5F processor
sub-systems are assumed to be running in Split mode, so a sub-mailbox
node is used by each of the R5F cores. Only the sub-mailbox node for
the first R5F core in each cluster is used in case of a Single-CPU mode
for that R5F cluster.

NOTE:
The cluster nodes only have the Mailbox IP interrupt outputs that are
routed to the GIC_SPI. The sub-mailbox nodes' irq-id are indexing into
the listed interrupts, with the usr-id using the actual interrupt output
line number from the Mailbox IP.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Gowtham Tammana <g-tammana@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 43 +++++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts  | 43 +++++++++++++++++++++++++
 2 files changed, 86 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 9522f104d979..0ebdd7981853 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -418,3 +418,46 @@ flash@0{
 		#size-cells = <1>;
 	};
 };
+
+&mailbox0_cluster2 {
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster3 {
+	status = "disabled";
+};
+
+&mailbox0_cluster4 {
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 3a5bee4b0b0c..5503fc6ddc0d 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -284,3 +284,46 @@ flash@0{
 		#size-cells = <1>;
 	};
 };
+
+&mailbox0_cluster2 {
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster3 {
+	status = "disabled";
+};
+
+&mailbox0_cluster4 {
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
-- 
2.30.1

[PATCH v2 3/3] arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes

[Suman Anna]

Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the AM64x SoCs for the AM642 EVM
and AM642 SK boards. These include the R5F remote processors in the two
dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; and a
M4 processor in the MCU safety island.

These sub-mailbox nodes utilize the System Mailbox clusters 2, 4 and 6.
The remaining clusters 3, 5 and 7 are currently not used, and so are
disabled. Clusters 0 and 1 were never added to the dts file as they do
not support interrupts towards the A53 core.

The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. The R5F processor
sub-systems are assumed to be running in Split mode, so a sub-mailbox
node is used by each of the R5F cores. Only the sub-mailbox node for
the first R5F core in each cluster is used in case of a Single-CPU mode
for that R5F cluster.

NOTE:
The cluster nodes only have the Mailbox IP interrupt outputs that are
routed to the GIC_SPI. The sub-mailbox nodes' irq-id are indexing into
the listed interrupts, with the usr-id using the actual interrupt output
line number from the Mailbox IP.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Gowtham Tammana <g-tammana@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 43 +++++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts  | 43 +++++++++++++++++++++++++
 2 files changed, 86 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 9522f104d979..0ebdd7981853 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -418,3 +418,46 @@ flash@0{
 		#size-cells = <1>;
 	};
 };
+
+&mailbox0_cluster2 {
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster3 {
+	status = "disabled";
+};
+
+&mailbox0_cluster4 {
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 3a5bee4b0b0c..5503fc6ddc0d 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -284,3 +284,46 @@ flash@0{
 		#size-cells = <1>;
 	};
 };
+
+&mailbox0_cluster2 {
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster3 {
+	status = "disabled";
+};
+
+&mailbox0_cluster4 {
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
-- 
2.30.1


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Re: [PATCH v2 0/3] AM64x HwSpinlock and Mailbox DT nodes

[Nishanth Menon]

On Mon, 22 Mar 2021 13:54:27 -0500, Suman Anna wrote:
> The following is a minor revision of the HwSpinlock and Mailbox DT nodes
> series [1] for AM64x SoCs on both AM64x-EVM and AM64x-SK boards. The main
> change is the squashing of the individual board dts patches into a single
> patch as per your request, and rebasing on your current latest ti-k3-dts-next
> branch HEAD commit e4e4e89482ea ("arm64: dts: ti: k3-am64-evm/sk: Add OSPI
> flash DT node"). I have also picked up Gowtham's Reviewed-by tags.
> 
> [...]

Hi Suman Anna,

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/3] arm64: dts: ti: k3-am64-main: Add hwspinlock node
      commit: 8248d5b3249c8a361c6906e73513769064854252
[2/3] arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes
      commit: ef1525761477c18b6b8fd420abb712e38492b480
[3/3] arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes
      commit: 7dd847523ed527cc8e90ca670675ea63d6239f64


All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v2 0/3] AM64x HwSpinlock and Mailbox DT nodes

[Nishanth Menon]

On Mon, 22 Mar 2021 13:54:27 -0500, Suman Anna wrote:
> The following is a minor revision of the HwSpinlock and Mailbox DT nodes
> series [1] for AM64x SoCs on both AM64x-EVM and AM64x-SK boards. The main
> change is the squashing of the individual board dts patches into a single
> patch as per your request, and rebasing on your current latest ti-k3-dts-next
> branch HEAD commit e4e4e89482ea ("arm64: dts: ti: k3-am64-evm/sk: Add OSPI
> flash DT node"). I have also picked up Gowtham's Reviewed-by tags.
> 
> [...]

Hi Suman Anna,

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/3] arm64: dts: ti: k3-am64-main: Add hwspinlock node
      commit: 8248d5b3249c8a361c6906e73513769064854252
[2/3] arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes
      commit: ef1525761477c18b6b8fd420abb712e38492b480
[3/3] arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes
      commit: 7dd847523ed527cc8e90ca670675ea63d6239f64


All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D


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