From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FB10C433DB for ; Mon, 22 Mar 2021 21:21:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6CDD161934 for ; Mon, 22 Mar 2021 21:21:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230113AbhCVVVW (ORCPT ); Mon, 22 Mar 2021 17:21:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229992AbhCVVUu (ORCPT ); Mon, 22 Mar 2021 17:20:50 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADD46C061574 for ; Mon, 22 Mar 2021 14:20:50 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id l3so12037615pfc.7 for ; Mon, 22 Mar 2021 14:20:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=iQ3MR3pIpBpekX6itg9dx4Nv4sSLl+GAinmP3XP/rag=; b=Qa4al1wO3hx0Wz1hABtDYi2AZu8Q1dRMeszbeM7VXMqahmn0DSdSm1F+OqWk0WsIXg W4Lw+Trzwrzq7r7UP2CGohdyJTB1i1kgxu1m09LAisdRqHUn3mSDovUqr0hogxNjt3fx UxRfycce2tuNv7QHZLrMGxtUzpPuIdsZ0/k5m68E0krZQsm7da1deho7EUk8mZvst6P0 R3EIMFP4iGqKJ4ZxVNwKLR+wXbhRGIBRC9mLL+dKDGuArxPw6m6q+vac/VYQg4yi+Hb+ jiLjcZioEOTO6ZBrUQ3PKVBibNeIWGujLfTRIe1/t/ZR6XHyzacXgCkz24uHmJn5nHEG YzPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=iQ3MR3pIpBpekX6itg9dx4Nv4sSLl+GAinmP3XP/rag=; b=ljveqgHfHrON/7UKC15ALEYCs5qUjz/9DPz2Hqc5Sq4g9ajbuzhQxPyQ93oTpZFava b7nQ/upHLS1IGhnb/SFoJ4N6bMVihP3doPal7j3SG8PsZ/H1wCxFhGeUe3WairLOG5JY BhzXVcUpCm1t8+zb8tC6KeKmRMZmmgSRr5+Gpp6lOvnckryE/oJrmDaDsqEfHOajFudC gEjN5IY2H70ruM+KrbUmeL7wQANSPiKlIJUeqbXdmqwo6yYCgDkr2CyCGre/ltYxqQw0 7bckgk1YEPw60JrsFrqbihZQy5u/pS6cfyoipRDtcI4rLrCx6xtOUGrRsYgltETv7E+S k+YA== X-Gm-Message-State: AOAM5322SBaT4Q+9la7OJTybgdONo/0A7EXPEvU+I0pbrZrBh3y1gEGW QOTB22OOuTIugXMF2BAm1Eujgg== X-Google-Smtp-Source: ABdhPJwUrDyed61o/S8LoRZp3mZYhkx1npYyAHJUqzFytgNxanjDXd6xM/cF/YTGI2wScufOyYVDEw== X-Received: by 2002:aa7:9989:0:b029:1f5:aa05:94af with SMTP id k9-20020aa799890000b02901f5aa0594afmr1767101pfh.34.1616448050228; Mon, 22 Mar 2021 14:20:50 -0700 (PDT) Received: from xps15 (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id l2sm298268pji.45.2021.03.22.14.20.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Mar 2021 14:20:49 -0700 (PDT) Date: Mon, 22 Mar 2021 15:20:47 -0600 From: Mathieu Poirier To: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mike.leach@linaro.org, anshuman.khandual@arm.com, leo.yan@linaro.org Subject: Re: [PATCH v4 18/19] coresight: sink: Add TRBE driver Message-ID: <20210322212047.GA1684006@xps15> References: <20210225193543.2920532-1-suzuki.poulose@arm.com> <20210225193543.2920532-19-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210225193543.2920532-19-suzuki.poulose@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Feb 25, 2021 at 07:35:42PM +0000, Suzuki K Poulose wrote: > From: Anshuman Khandual > > Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is > accessible via the system registers. The TRBE supports different addressing > modes including CPU virtual address and buffer modes including the circular > buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1), > an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the > access to the trace buffer could be prohibited by a higher exception level > (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU > private interrupt (PPI) on address translation errors and when the buffer > is full. Overall implementation here is inspired from the Arm SPE driver. > > Cc: Mathieu Poirier > Cc: Mike Leach > Cc: Suzuki K Poulose > Signed-off-by: Anshuman Khandual > Signed-off-by: Suzuki K Poulose > --- > Changes: > - Replaced TRBLIMITR_LIMIT_SHIFT with TRBBASER_BASE_SHIFT in set_trbe_base_pointer() > - Dropped TRBBASER_BASE_MASK and TRBBASER_BASE_SHIFT from get_trbe_base_pointer() > - Indentation changes for TRBE_BSC_NOT_[STOPPED|FILLED|TRIGGERED] definitions > - Moved DECLARE_PER_CPU(...., csdev_sink) into coresight-priv.h > - Moved isb() from trbe_enable_hw() into set_trbe_limit_pointer_enabled() > - Dropped the space after type casting before vmap() > - Return 0 instead of EINVAL in arm_trbe_update_buffer() > - Add a comment in trbe_handle_overflow() > - Add a comment in arm_trbe_cpu_startup() > - Unregister coresight TRBE device when not supported > - Fix potential NULL handle dereference in IRQ handler with a spurious IRQ > - Read TRBIDR after is_trbe_programmable() in arm_trbe_probe_coresight_cpu() > - Replaced and modified trbe_drain_and_disable_local() in IRQ handler > - Updated arm_trbe_update_buffer() for handling a missing interrupt > - Dropped kfree() for all devm_xxx() allocated buffer > - Dropped additional blank line in documentation coresight/coresight-trbe.rst > - Added Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe > - Changed CONFIG_CORESIGHT_TRBE options, dependencies and helper write up > - Added comment for irq_work_run() > - Updated comment for minumum buffer length in arm_trbe_alloc_buffer() > - Dropped redundant smp_processor_id() from arm_trbe_probe_coresight_cpu() > - Fixed indentation in arm_trbe_probe_cpuhp() > - Added static for arm_trbe_free_buffer() > - Added comment for trbe_base element in trbe_buf structure > - Dropped IS_ERR() check from vmap() returned pointer > - Added WARN_ON(trbe_csdev) in arm_trbe_probe_coresight_cpu() > - Changed TRBE device names from arm_trbeX to just trbeX > - Dropped unused argument perf_output_handle from trbe_get_fault_act() > - Dropped IS_ERR() from kzalloc_node()/kcalloc() buffer in arm_trbe_alloc_buffer() > - Dropped IS_ERR() and return -ENOMEM in arm_trbe_probe_coresight() > - Moved TRBE HW disabling before coresight cleanup in arm_trbe_remove_coresight_cpu() > - Changed error return codes from arm_trbe_probe_irq() > - Changed error return codes from arm_trbe_device_probe() > - Changed arm_trbe_remove_coresight() order in arm_trbe_device_remove() > - Changed TRBE CPU support probe/remove sequence with for_each_cpu() iterator > - Changed coresight_register() in arm_trbe_probe_coresight_cpu() > - Changed error return code when cpuhp_setup_state_multi() fails in arm_trbe_probe_cpuhp() > - Changed error return code when cpuhp_state_add_instance() fails in arm_trbe_probe_cpuhp() > - Changed trbe_dbm as trbe_flag including its sysfs interface > - Handle race between update_buffer & IRQ handler > - Rework and split the TRBE probe to avoid lockdep due to memory allocation > from IPI calls (via coresight_register()) > - Fix handle->head updat for snapshot mode. All of the above make this driver much easier to read. > --- > .../testing/sysfs-bus-coresight-devices-trbe | 14 + > .../trace/coresight/coresight-trbe.rst | 38 + > drivers/hwtracing/coresight/Kconfig | 14 + > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-trbe.c | 1149 +++++++++++++++++ > drivers/hwtracing/coresight/coresight-trbe.h | 153 +++ > 6 files changed, 1369 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe > create mode 100644 Documentation/trace/coresight/coresight-trbe.rst > create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c > create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h > [...] > + > +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev, > + struct perf_event *event, void **pages, > + int nr_pages, bool snapshot) > +{ > + struct trbe_buf *buf; > + struct page **pglist; > + int i; > + > + /* > + * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with > + * just a single page, there would not be any room left while writing > + * into a partially filled TRBE buffer after the page size alignment. > + * Hence restrict the minimum buffer size as two pages. > + */ > + if (nr_pages < 2) > + return NULL; > + > + buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event)); > + if (!buf) > + return ERR_PTR(-ENOMEM); > + > + pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL); > + if (!pglist) { > + kfree(buf); > + return ERR_PTR(-ENOMEM); > + } > + > + for (i = 0; i < nr_pages; i++) > + pglist[i] = virt_to_page(pages[i]); > + > + buf->trbe_base = (unsigned long)vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL); > + if (!buf->trbe_base) { > + kfree(pglist); > + kfree(buf); > + return ERR_PTR(buf->trbe_base); return ERR_PTR(-ENOMEM); > + } > + buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE; > + buf->trbe_write = buf->trbe_base; > + buf->snapshot = snapshot; > + buf->nr_pages = nr_pages; > + buf->pages = pages; > + kfree(pglist); > + return buf; > +} > + From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E466CC433C1 for ; Mon, 22 Mar 2021 21:22:58 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5BD2A61984 for ; Mon, 22 Mar 2021 21:22:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5BD2A61984 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=f9UG8nAy6vC0F5VNoyJWEPXE0Qv+9uVymRWeVhqIu94=; b=BnxuYNPffIYJ34Kz2SostwJn9 gPgsQOwCis5KsW71wYiKNHvVEkzmYuuGpidhaucRFlZ7WDUKRUbBOETP9LLHHt+JF+UP9jaSnwdaN HKKI51HHMFv6lYfoPVNnZnWX67Te0w097eYWWHXhzKYiRFlD0D4jwmI1AsprXlzx+B3P8V4+ZPm2h ARjyMBmMAZqlNy60jdBq5+aDcaZlldkNFG/I9PywIcVO/ww2PPVv9PUJrV9fe37wZ6vnAAjzEbs9e hVPV6YRjeomh8dnAynuu8jlGjHY94aZz/bkNbqgnvRrUdtJqkChUvVJvj+8Uq3ikCYpy3dqO+4EoX 8wIR0CBKw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lORyu-00CZbP-Qp; Mon, 22 Mar 2021 21:21:01 +0000 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lORym-00CZZY-VV for linux-arm-kernel@lists.infradead.org; Mon, 22 Mar 2021 21:20:56 +0000 Received: by mail-pg1-x52d.google.com with SMTP id f10so2528240pgl.9 for ; Mon, 22 Mar 2021 14:20:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=iQ3MR3pIpBpekX6itg9dx4Nv4sSLl+GAinmP3XP/rag=; b=Qa4al1wO3hx0Wz1hABtDYi2AZu8Q1dRMeszbeM7VXMqahmn0DSdSm1F+OqWk0WsIXg W4Lw+Trzwrzq7r7UP2CGohdyJTB1i1kgxu1m09LAisdRqHUn3mSDovUqr0hogxNjt3fx UxRfycce2tuNv7QHZLrMGxtUzpPuIdsZ0/k5m68E0krZQsm7da1deho7EUk8mZvst6P0 R3EIMFP4iGqKJ4ZxVNwKLR+wXbhRGIBRC9mLL+dKDGuArxPw6m6q+vac/VYQg4yi+Hb+ jiLjcZioEOTO6ZBrUQ3PKVBibNeIWGujLfTRIe1/t/ZR6XHyzacXgCkz24uHmJn5nHEG YzPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=iQ3MR3pIpBpekX6itg9dx4Nv4sSLl+GAinmP3XP/rag=; b=o5MDLXCvELOTRBknIvYNUsOHPG/ZJ3nz+ayird6RCiif2uIcoEYDAJ/9HZlIYMpg1C t+AQQ8ifhLpSGqQkAdbttPHFmxDdJmTUnUytl4AGbBoqyH0lJuqn6NxfgSccePMuG2h5 Ak8iVqaIU5oWbt1416l580AEQ95JT/KVOIKGiA9ZcqlxonROb4zDDZGed1i74HPlQXFL F3GLWLE6fuFmFQEybxQODvKMUE9yndR6Z1VvhtJ8inXUgb+x2TeU07EOExGQbnKIb7kT 0Mc1wctEZX/58bUB7CVe95LiA1N3EVn6gRjXvV/NjxWEVLa+jDUt7mU36tIv8xJnzfd0 Ar4g== X-Gm-Message-State: AOAM532o6wlYqAApM7rYDnnaIufA4ITJe4zYYzHhHOi3+tgSTfQ+AeOV N+Yh0jWShcp9Iy6Ctyj3MVQkIg== X-Google-Smtp-Source: ABdhPJwUrDyed61o/S8LoRZp3mZYhkx1npYyAHJUqzFytgNxanjDXd6xM/cF/YTGI2wScufOyYVDEw== X-Received: by 2002:aa7:9989:0:b029:1f5:aa05:94af with SMTP id k9-20020aa799890000b02901f5aa0594afmr1767101pfh.34.1616448050228; Mon, 22 Mar 2021 14:20:50 -0700 (PDT) Received: from xps15 (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id l2sm298268pji.45.2021.03.22.14.20.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Mar 2021 14:20:49 -0700 (PDT) Date: Mon, 22 Mar 2021 15:20:47 -0600 From: Mathieu Poirier To: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mike.leach@linaro.org, anshuman.khandual@arm.com, leo.yan@linaro.org Subject: Re: [PATCH v4 18/19] coresight: sink: Add TRBE driver Message-ID: <20210322212047.GA1684006@xps15> References: <20210225193543.2920532-1-suzuki.poulose@arm.com> <20210225193543.2920532-19-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210225193543.2920532-19-suzuki.poulose@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210322_212053_158726_2636A7EF X-CRM114-Status: GOOD ( 31.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Feb 25, 2021 at 07:35:42PM +0000, Suzuki K Poulose wrote: > From: Anshuman Khandual > > Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is > accessible via the system registers. The TRBE supports different addressing > modes including CPU virtual address and buffer modes including the circular > buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1), > an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the > access to the trace buffer could be prohibited by a higher exception level > (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU > private interrupt (PPI) on address translation errors and when the buffer > is full. Overall implementation here is inspired from the Arm SPE driver. > > Cc: Mathieu Poirier > Cc: Mike Leach > Cc: Suzuki K Poulose > Signed-off-by: Anshuman Khandual > Signed-off-by: Suzuki K Poulose > --- > Changes: > - Replaced TRBLIMITR_LIMIT_SHIFT with TRBBASER_BASE_SHIFT in set_trbe_base_pointer() > - Dropped TRBBASER_BASE_MASK and TRBBASER_BASE_SHIFT from get_trbe_base_pointer() > - Indentation changes for TRBE_BSC_NOT_[STOPPED|FILLED|TRIGGERED] definitions > - Moved DECLARE_PER_CPU(...., csdev_sink) into coresight-priv.h > - Moved isb() from trbe_enable_hw() into set_trbe_limit_pointer_enabled() > - Dropped the space after type casting before vmap() > - Return 0 instead of EINVAL in arm_trbe_update_buffer() > - Add a comment in trbe_handle_overflow() > - Add a comment in arm_trbe_cpu_startup() > - Unregister coresight TRBE device when not supported > - Fix potential NULL handle dereference in IRQ handler with a spurious IRQ > - Read TRBIDR after is_trbe_programmable() in arm_trbe_probe_coresight_cpu() > - Replaced and modified trbe_drain_and_disable_local() in IRQ handler > - Updated arm_trbe_update_buffer() for handling a missing interrupt > - Dropped kfree() for all devm_xxx() allocated buffer > - Dropped additional blank line in documentation coresight/coresight-trbe.rst > - Added Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe > - Changed CONFIG_CORESIGHT_TRBE options, dependencies and helper write up > - Added comment for irq_work_run() > - Updated comment for minumum buffer length in arm_trbe_alloc_buffer() > - Dropped redundant smp_processor_id() from arm_trbe_probe_coresight_cpu() > - Fixed indentation in arm_trbe_probe_cpuhp() > - Added static for arm_trbe_free_buffer() > - Added comment for trbe_base element in trbe_buf structure > - Dropped IS_ERR() check from vmap() returned pointer > - Added WARN_ON(trbe_csdev) in arm_trbe_probe_coresight_cpu() > - Changed TRBE device names from arm_trbeX to just trbeX > - Dropped unused argument perf_output_handle from trbe_get_fault_act() > - Dropped IS_ERR() from kzalloc_node()/kcalloc() buffer in arm_trbe_alloc_buffer() > - Dropped IS_ERR() and return -ENOMEM in arm_trbe_probe_coresight() > - Moved TRBE HW disabling before coresight cleanup in arm_trbe_remove_coresight_cpu() > - Changed error return codes from arm_trbe_probe_irq() > - Changed error return codes from arm_trbe_device_probe() > - Changed arm_trbe_remove_coresight() order in arm_trbe_device_remove() > - Changed TRBE CPU support probe/remove sequence with for_each_cpu() iterator > - Changed coresight_register() in arm_trbe_probe_coresight_cpu() > - Changed error return code when cpuhp_setup_state_multi() fails in arm_trbe_probe_cpuhp() > - Changed error return code when cpuhp_state_add_instance() fails in arm_trbe_probe_cpuhp() > - Changed trbe_dbm as trbe_flag including its sysfs interface > - Handle race between update_buffer & IRQ handler > - Rework and split the TRBE probe to avoid lockdep due to memory allocation > from IPI calls (via coresight_register()) > - Fix handle->head updat for snapshot mode. All of the above make this driver much easier to read. > --- > .../testing/sysfs-bus-coresight-devices-trbe | 14 + > .../trace/coresight/coresight-trbe.rst | 38 + > drivers/hwtracing/coresight/Kconfig | 14 + > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-trbe.c | 1149 +++++++++++++++++ > drivers/hwtracing/coresight/coresight-trbe.h | 153 +++ > 6 files changed, 1369 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe > create mode 100644 Documentation/trace/coresight/coresight-trbe.rst > create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c > create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h > [...] > + > +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev, > + struct perf_event *event, void **pages, > + int nr_pages, bool snapshot) > +{ > + struct trbe_buf *buf; > + struct page **pglist; > + int i; > + > + /* > + * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with > + * just a single page, there would not be any room left while writing > + * into a partially filled TRBE buffer after the page size alignment. > + * Hence restrict the minimum buffer size as two pages. > + */ > + if (nr_pages < 2) > + return NULL; > + > + buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event)); > + if (!buf) > + return ERR_PTR(-ENOMEM); > + > + pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL); > + if (!pglist) { > + kfree(buf); > + return ERR_PTR(-ENOMEM); > + } > + > + for (i = 0; i < nr_pages; i++) > + pglist[i] = virt_to_page(pages[i]); > + > + buf->trbe_base = (unsigned long)vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL); > + if (!buf->trbe_base) { > + kfree(pglist); > + kfree(buf); > + return ERR_PTR(buf->trbe_base); return ERR_PTR(-ENOMEM); > + } > + buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE; > + buf->trbe_write = buf->trbe_base; > + buf->snapshot = snapshot; > + buf->nr_pages = nr_pages; > + buf->pages = pages; > + kfree(pglist); > + return buf; > +} > + _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel