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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id y1sm7976686wmq.29.2021.03.25.17.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Mar 2021 17:28:06 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH-for-6.1 07/10] hw/block/pflash_cfi02: Simplify pflash_cfi02_register() prototype Date: Fri, 26 Mar 2021 01:27:25 +0100 Message-Id: <20210326002728.1069834-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210326002728.1069834-1-f4bug@amsat.org> References: <20210326002728.1069834-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Peter Maydell , Magnus Damm , Jan Kiszka , "open list:Block layer core" , Yoshinori Sato , Mark Cave-Ayland , Alistair Francis , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Michael Walle , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Antony Pavlov , "Edgar E. Iglesias" , Greg Kurz , Max Reitz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The previous commit removed the mapping code from TYPE_PFLASH_CFI02. pflash_cfi02_register() doesn't use the 'nb_mappings' argument anymore. Simply remove it to simplify. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/block/flash.h | 1 - hw/arm/digic_boards.c | 1 - hw/arm/musicpal.c | 1 - hw/arm/xilinx_zynq.c | 2 +- hw/block/pflash_cfi02.c | 3 +-- hw/lm32/lm32_boards.c | 4 ++-- hw/ppc/ppc405_boards.c | 6 +++--- hw/sh4/r2d.c | 2 +- 8 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 7dde0adcee7..0e5dd818a9d 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -36,7 +36,6 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base, hwaddr size, BlockBackend *blk, uint32_t sector_len, - int nb_mappings, int width, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3, diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 293402b1240..eb694c70d4c 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -128,7 +128,6 @@ static void digic4_add_k8p3215uqb_rom(DigicState *s, hwaddr addr, FLASH_K8P3215UQB_SIZE / FLASH_K8P3215UQB_SECTOR_SIZE); qdev_prop_set_uint32(dev, "sector-length", FLASH_K8P3215UQB_SECTOR_SIZE); qdev_prop_set_uint8(dev, "width", 4); /* 32-bit */ - qdev_prop_set_uint8(dev, "mappings", 0); qdev_prop_set_uint8(dev, "big-endian", 0); qdev_prop_set_uint16(dev, "id0", 0x00ec); qdev_prop_set_uint16(dev, "id1", 0x007e); diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 7d1f2f3fb3f..e882e11df36 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1657,7 +1657,6 @@ static void musicpal_init(MachineState *machine) qdev_prop_set_uint32(dev, "num-blocks", flash_size / sector_size); qdev_prop_set_uint32(dev, "sector-length", sector_size); qdev_prop_set_uint8(dev, "width", 2); /* 16-bit */ - qdev_prop_set_uint8(dev, "mappings", 0); qdev_prop_set_uint8(dev, "big-endian", 0); qdev_prop_set_uint16(dev, "id0", 0x00bf); qdev_prop_set_uint16(dev, "id1", 0x236d); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 8db6cfd47f5..d12b00e7648 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -220,7 +220,7 @@ static void zynq_init(MachineState *machine) pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, FLASH_SECTOR_SIZE, 1, - 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, + 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 0); /* Create the main clock source, and feed slcr with it */ diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 6f4b3e3c3fe..2b412402fac 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -968,7 +968,7 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base, hwaddr size, BlockBackend *blk, uint32_t sector_len, - int nb_mappings, int width, + int width, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3, uint16_t unlock_addr0, @@ -977,7 +977,6 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base, { DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02); - assert(nb_mappings <= 1); if (blk) { qdev_prop_set_drive(dev, "drive", blk); } diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c index b5d97dd53ed..96877ba7cfb 100644 --- a/hw/lm32/lm32_boards.c +++ b/hw/lm32/lm32_boards.c @@ -121,7 +121,7 @@ static void lm32_evr_init(MachineState *machine) pflash_cfi02_register(flash_base, "lm32_evr.flash", flash_size, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, flash_sector_size, - 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); + 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); /* create irq lines */ env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0)); @@ -218,7 +218,7 @@ static void lm32_uclinux_init(MachineState *machine) pflash_cfi02_register(flash_base, "lm32_uclinux.flash", flash_size, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, flash_sector_size, - 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); + 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); /* create irq lines */ env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0)); diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 8f77887fb18..2503e033497 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -198,7 +198,7 @@ static void ref405ep_init(MachineState *machine) pflash_cfi02_register((uint32_t)(-bios_size), "ef405ep.bios", bios_size, blk_by_legacy_dinfo(dinfo), - 64 * KiB, 1, + 64 * KiB, 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 1); } else @@ -469,7 +469,7 @@ static void taihu_405ep_init(MachineState *machine) pflash_cfi02_register(0xFFE00000, "taihu_405ep.bios", bios_size, blk_by_legacy_dinfo(dinfo), - 64 * KiB, 1, + 64 * KiB, 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 1); fl_idx++; @@ -502,7 +502,7 @@ static void taihu_405ep_init(MachineState *machine) bios_size = 32 * MiB; pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size, blk_by_legacy_dinfo(dinfo), - 64 * KiB, 1, + 64 * KiB, 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 1); fl_idx++; diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 443820901d4..b7288dcba80 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -301,7 +301,7 @@ static void r2d_init(MachineState *machine) dinfo = drive_get(IF_PFLASH, 0, 0); pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200, + 64 * KiB, 2, 0x0001, 0x227e, 0x2220, 0x2200, 0x555, 0x2aa, 0); /* NIC: rtl8139 on-board, and 2 slots. */ -- 2.26.2