From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0EBBC433E1 for ; Fri, 26 Mar 2021 23:13:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9259161A2A for ; Fri, 26 Mar 2021 23:13:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230299AbhCZXNI (ORCPT ); Fri, 26 Mar 2021 19:13:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230266AbhCZXNG (ORCPT ); Fri, 26 Mar 2021 19:13:06 -0400 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 647E3C0613B2 for ; Fri, 26 Mar 2021 16:13:06 -0700 (PDT) Received: by mail-pg1-x52b.google.com with SMTP id i22so5601598pgl.4 for ; Fri, 26 Mar 2021 16:13:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anholt-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Br5dnsn6qntOpU2U5zqHAGfW5LmzUx9sZjoQtT0uBvA=; b=IEdGgwaqDywiGX1dYZabuHGeCPVqPOmtJ9gWumaiYE8LhpP7TPrmgh9Am25ZaK541g Sd6wCiWEHPLssN/QZZQCUeV+b1jFHBa9vQqdVSP3T3NKxBgV1FzobrzJQk+NKL1vpuLV nEBB9ozh/jSnm0UXI/GzbP33fvZOn8O0AIvyW/rAMtsz/ObcK8gFgtMXwYpCI7Cdziuy hK/y6rYLo5xaOrwm+VBc/5k6KIR1KnM5+EV+9VYRQNJJmPdIwyGNck0fJFpkoeQjmTPC AxTNhc1eE8HVAOr6kzUsbL0Uf0SoOCvwLRALNWIDRuXgHEd9O9L4wwkNJpd+hDPMKjIY 3mKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Br5dnsn6qntOpU2U5zqHAGfW5LmzUx9sZjoQtT0uBvA=; b=Rxm+iJxgjPFTEBbEVa7dkdQbSyTfKRv7zD93Cnq0gk9wFcxe+Q+IJwxjiZyfXUhBBg hTFWxWDdZ8b79wmbxcqiFoLVIXw3eenWpwXTL/KIkmtoPYGsfI/da/nYC+K6lmpJSibM mJf1C1OCynR1SwMvHjpT1ACXNnElCUn82g4mbeiNAqRSojU5h4d5s4WmFYRKH/qlUJLX /ivv5ruNC9noabptFJLb/1JYSdANNCIsupMDVUoYud4PPG64yXE9yI7eJGbgX9uXkvBM NYvZHr/gYXCos3wjUga0gBchFy2SOMxcG/lugDqHgts1ibCwdfKGA3puTNFmiku5Hmmm wl1w== X-Gm-Message-State: AOAM5316lrB8xYSR7SvXHu4beBMbJNy5VlWBouKGgvz2ijvU9DkxILH+ eO33aOyViTQPZ4xH6YDgb7LB6Q== X-Google-Smtp-Source: ABdhPJyNsiHsr3ai4ailFi6BHrwZ2FIzfLry8wAsmSYAHRtFtpb20MzTEwoKOTxny41h4vqVptXooQ== X-Received: by 2002:a65:458f:: with SMTP id o15mr13853926pgq.111.1616800385764; Fri, 26 Mar 2021 16:13:05 -0700 (PDT) Received: from wildbow.anholt.net ([97.115.138.77]) by smtp.gmail.com with ESMTPSA id a144sm10289325pfd.200.2021.03.26.16.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 16:13:05 -0700 (PDT) From: Eric Anholt To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , Jordan Crouse , Robin Murphy , Will Deacon , Rob Herring , Joerg Roedel , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Eric Anholt Subject: [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c. Date: Fri, 26 Mar 2021 16:13:02 -0700 Message-Id: <20210326231303.3071950-1-eric@anholt.net> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org db820c wants to use the qcom smmu path to get HUPCF set (which keeps the GPU from wedging and then sometimes wedging the kernel after a page fault), but it doesn't have separate pagetables support yet in drm/msm so we can't go all the way to the TTBR1 path. Signed-off-by: Eric Anholt --- We've been seeing a flaky test per day or so in Mesa CI where the kernel gets wedged after an iommu fault turns into CP errors. With this patch, the CI isn't throwing the string of CP errors on the faults in any of the ~10 jobs I've run so far. drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index bcda17012aee..51f22193e456 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -130,6 +130,16 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); } +static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) +{ + const struct device_node *np = smmu->dev->of_node; + + if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) + return false; + + return true; +} + static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { @@ -144,7 +154,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, * be AARCH64 stage 1 but double check because the arm-smmu code assumes * that is the case when the TTBR1 quirk is enabled */ - if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && + if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && + (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; -- 2.31.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DD61C433C1 for ; Fri, 26 Mar 2021 23:14:54 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B66561971 for ; Fri, 26 Mar 2021 23:14:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1B66561971 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=anholt.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=RYc6XYvcKFHmCs+xnFE2rCbPzLWH6EBWXCRSd8TVfP0=; b=Vl3V9JkleV19FCHX6NrEXczKii jIIkM/pR89sNw9i3nJil2oqyedtGup1yduGgDXQSLbSXHVsiJ22JmDNNvzYpgbQVNUvY5M7lwoj+g 5X44vP8YNoat04eVBwxdaG0zfmbyeSLA9gAh23LEVpJZW2K0pfhciEZGCrYaRGDskWy4Omke+NZOr 8zTBPU1kTH/ljQL7kwAO41DRm0P/KKJbvnHAt4lG7nE+bi76ycIbWqZsx+nLZkhZiSbXo09zASZxe EI98UtXCMctrHKMk3NpWi5Au4szLXd4+jV/vaHKap6Ntgdp02ah1Xzup9/hMGAEzP5YI3FsmeN2iH Ug72r7dA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lPvdh-004V4L-RQ; Fri, 26 Mar 2021 23:13:14 +0000 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lPvdc-004V3b-Ks for linux-arm-kernel@lists.infradead.org; Fri, 26 Mar 2021 23:13:10 +0000 Received: by mail-pg1-x52c.google.com with SMTP id 32so5619105pgm.1 for ; Fri, 26 Mar 2021 16:13:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anholt-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Br5dnsn6qntOpU2U5zqHAGfW5LmzUx9sZjoQtT0uBvA=; b=IEdGgwaqDywiGX1dYZabuHGeCPVqPOmtJ9gWumaiYE8LhpP7TPrmgh9Am25ZaK541g Sd6wCiWEHPLssN/QZZQCUeV+b1jFHBa9vQqdVSP3T3NKxBgV1FzobrzJQk+NKL1vpuLV nEBB9ozh/jSnm0UXI/GzbP33fvZOn8O0AIvyW/rAMtsz/ObcK8gFgtMXwYpCI7Cdziuy hK/y6rYLo5xaOrwm+VBc/5k6KIR1KnM5+EV+9VYRQNJJmPdIwyGNck0fJFpkoeQjmTPC AxTNhc1eE8HVAOr6kzUsbL0Uf0SoOCvwLRALNWIDRuXgHEd9O9L4wwkNJpd+hDPMKjIY 3mKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Br5dnsn6qntOpU2U5zqHAGfW5LmzUx9sZjoQtT0uBvA=; b=o4WacnRcgQM0SUbpNDeBSBuJqqePiBc7uIxJZacdQoBQPPZeRdbgi+1JQQDrU0NtR8 IIMRBLlYLUUxoE5Ko9fnwbEaRyKLB7rCxVsi6dXbIXBdzi7rP+nUoFW9PJbxEQLMChPY NAqpLAcRdtPXbFTlyVkH3SiYWEdsg0+v65T+t9DIStYH/QBmQxzhkSR5tS+1Gw+VdHmc LtCJ2U7ufIr3U68JlKcOdMBhkC9rRnrZfxxTq8xsmBufc7nJZu45SlQF9rotI2fVlbMZ qVao55wpmTCiOE7iasrmUwrwZV9TSb1+oVPRSR7UI5Xm3VXGmwW1HmW6Ar+LGBZ5YpAW 6Qtg== X-Gm-Message-State: AOAM530pdGBDH2cTBbtAr4i71kpBao/XU1BAcFzfiXdvDgeCvoF0/YFg 7Nd6jQUjBQdw0ttof20gOyE5KQ== X-Google-Smtp-Source: ABdhPJyNsiHsr3ai4ailFi6BHrwZ2FIzfLry8wAsmSYAHRtFtpb20MzTEwoKOTxny41h4vqVptXooQ== X-Received: by 2002:a65:458f:: with SMTP id o15mr13853926pgq.111.1616800385764; Fri, 26 Mar 2021 16:13:05 -0700 (PDT) Received: from wildbow.anholt.net ([97.115.138.77]) by smtp.gmail.com with ESMTPSA id a144sm10289325pfd.200.2021.03.26.16.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 16:13:05 -0700 (PDT) From: Eric Anholt To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , Jordan Crouse , Robin Murphy , Will Deacon , Rob Herring , Joerg Roedel , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Eric Anholt Subject: [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c. Date: Fri, 26 Mar 2021 16:13:02 -0700 Message-Id: <20210326231303.3071950-1-eric@anholt.net> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210326_231309_044436_A7A75402 X-CRM114-Status: GOOD ( 16.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org db820c wants to use the qcom smmu path to get HUPCF set (which keeps the GPU from wedging and then sometimes wedging the kernel after a page fault), but it doesn't have separate pagetables support yet in drm/msm so we can't go all the way to the TTBR1 path. Signed-off-by: Eric Anholt --- We've been seeing a flaky test per day or so in Mesa CI where the kernel gets wedged after an iommu fault turns into CP errors. With this patch, the CI isn't throwing the string of CP errors on the faults in any of the ~10 jobs I've run so far. drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index bcda17012aee..51f22193e456 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -130,6 +130,16 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); } +static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) +{ + const struct device_node *np = smmu->dev->of_node; + + if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) + return false; + + return true; +} + static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { @@ -144,7 +154,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, * be AARCH64 stage 1 but double check because the arm-smmu code assumes * that is the case when the TTBR1 quirk is enabled */ - if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && + if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && + (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; -- 2.31.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90D82C433DB for ; Fri, 26 Mar 2021 23:13:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 45FA961965 for ; Fri, 26 Mar 2021 23:13:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 45FA961965 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=anholt.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A68E06F4F9; Fri, 26 Mar 2021 23:13:07 +0000 (UTC) Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8AAD66F4FA for ; Fri, 26 Mar 2021 23:13:06 +0000 (UTC) Received: by mail-pg1-x536.google.com with SMTP id f10so5586544pgl.9 for ; Fri, 26 Mar 2021 16:13:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anholt-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Br5dnsn6qntOpU2U5zqHAGfW5LmzUx9sZjoQtT0uBvA=; b=IEdGgwaqDywiGX1dYZabuHGeCPVqPOmtJ9gWumaiYE8LhpP7TPrmgh9Am25ZaK541g Sd6wCiWEHPLssN/QZZQCUeV+b1jFHBa9vQqdVSP3T3NKxBgV1FzobrzJQk+NKL1vpuLV nEBB9ozh/jSnm0UXI/GzbP33fvZOn8O0AIvyW/rAMtsz/ObcK8gFgtMXwYpCI7Cdziuy hK/y6rYLo5xaOrwm+VBc/5k6KIR1KnM5+EV+9VYRQNJJmPdIwyGNck0fJFpkoeQjmTPC AxTNhc1eE8HVAOr6kzUsbL0Uf0SoOCvwLRALNWIDRuXgHEd9O9L4wwkNJpd+hDPMKjIY 3mKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Br5dnsn6qntOpU2U5zqHAGfW5LmzUx9sZjoQtT0uBvA=; b=oMeWPyI1N/s89dQmPTXIguOREFUq0c9lMASBhg6cxf1CakObuwoax9wmrDRgMrrEcH Xd/VyQtXR7Ldlcd+u68JMhSBiVqaef7HujCTKdOaF9pMiot0GlfREQIB4Won8Kmtj/uN 1zoM53NHuQJqS4cZ42ZQ77kM5QOoX62ejvuUZTB/3Sed62IGxqD0M7R2bQD0m+hD2gcI 9FuMDP0TBarXHU+rxmZaq0gShIDluQ46cqzbp4LAm5PRp1b4KyFrxP6SeM0G799Y10cE MkVnVjHV3OJOe3V92qgqefT6bAnZPdF40lKMmf6ReFJ2upX9lmGf1TpznjkVVKbac+CG R6gw== X-Gm-Message-State: AOAM530LlmAexVni+N5dqd1Cqbc2A62QwWQkEV9624xGkYSRtdDr+9yr Ft1gRsQjleqBP/poj5rAJMmoZaENYYk0ow== X-Google-Smtp-Source: ABdhPJyNsiHsr3ai4ailFi6BHrwZ2FIzfLry8wAsmSYAHRtFtpb20MzTEwoKOTxny41h4vqVptXooQ== X-Received: by 2002:a65:458f:: with SMTP id o15mr13853926pgq.111.1616800385764; Fri, 26 Mar 2021 16:13:05 -0700 (PDT) Received: from wildbow.anholt.net ([97.115.138.77]) by smtp.gmail.com with ESMTPSA id a144sm10289325pfd.200.2021.03.26.16.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 16:13:05 -0700 (PDT) From: Eric Anholt To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , Jordan Crouse , Robin Murphy , Will Deacon , Rob Herring , Joerg Roedel , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c. Date: Fri, 26 Mar 2021 16:13:02 -0700 Message-Id: <20210326231303.3071950-1-eric@anholt.net> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" db820c wants to use the qcom smmu path to get HUPCF set (which keeps the GPU from wedging and then sometimes wedging the kernel after a page fault), but it doesn't have separate pagetables support yet in drm/msm so we can't go all the way to the TTBR1 path. Signed-off-by: Eric Anholt --- We've been seeing a flaky test per day or so in Mesa CI where the kernel gets wedged after an iommu fault turns into CP errors. With this patch, the CI isn't throwing the string of CP errors on the faults in any of the ~10 jobs I've run so far. drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index bcda17012aee..51f22193e456 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -130,6 +130,16 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); } +static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) +{ + const struct device_node *np = smmu->dev->of_node; + + if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) + return false; + + return true; +} + static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { @@ -144,7 +154,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, * be AARCH64 stage 1 but double check because the arm-smmu code assumes * that is the case when the TTBR1 quirk is enabled */ - if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && + if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && + (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; -- 2.31.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel